From 78e4312f890a7b648c320c17435e9592aae4b7b7 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 22 Apr 2020 12:59:31 +0530 Subject: [PATCH 1/3] clk: qcom: clk-alpha-pll: Add support for Legacy FSM Mode The Legacy FSM Mode is required to be set when the Fabia PLL needs to be used in non-FSM mode, thus add support for same. Change-Id: I23d491cb33391dce1eb21d9ced298001da9ef907 Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 5 +++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 3e793f227b79..7f742574ee21 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -28,6 +28,7 @@ # define PLL_VOTE_FSM_RESET BIT(21) # define PLL_UPDATE BIT(22) # define PLL_UPDATE_BYPASS BIT(23) +#define PLL_FSM_LEGACY_MODE BIT(24) # define PLL_OFFLINE_ACK BIT(28) # define ALPHA_PLL_ACK_LATCH BIT(29) # define PLL_ACTIVE_FLAG BIT(30) @@ -1995,6 +1996,10 @@ int clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); } + if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) + regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, + PLL_FSM_LEGACY_MODE); + regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, PLL_UPDATE_BYPASS); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index f781d2b602dc..1397bf66e617 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -71,6 +71,7 @@ struct clk_alpha_pll { #define SUPPORTS_OFFLINE_REQ BIT(0) #define SUPPORTS_FSM_MODE BIT(2) #define SUPPORTS_DYNAMIC_UPDATE BIT(3) +#define SUPPORTS_FSM_LEGACY_MODE BIT(4) u8 flags; struct clk_regmap clkr; From 8f23926d01d6f695b56e63ed2b30bad7a0149b53 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 8 Apr 2020 15:35:03 +0530 Subject: [PATCH 2/3] clk: qcom: clk-alpha-pll: Add support for Agera PLL Agera PLL is required to be supported from HLOS clock controller, thus add support for agera pll ops. Change-Id: I77b2a741667accf9bd0eecfcd0dabfaf7596345f Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 113 +++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 4 ++ 2 files changed, 117 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 7f742574ee21..ebcdec17a224 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -192,6 +192,16 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_OPMODE] = 0x28, [PLL_OFF_STATUS] = 0x38, }, + [CLK_ALPHA_PLL_TYPE_AGERA] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_USER_CTL] = 0x0c, + [PLL_OFF_CONFIG_CTL] = 0x10, + [PLL_OFF_CONFIG_CTL_U] = 0x14, + [PLL_OFF_TEST_CTL] = 0x18, + [PLL_OFF_TEST_CTL_U] = 0x1c, + [PLL_OFF_STATUS] = 0x2c, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); @@ -3476,3 +3486,106 @@ const struct clk_ops clk_regera_pll_ops = { #endif }; EXPORT_SYMBOL_GPL(clk_regera_pll_ops); + +int clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + u32 val, mask; + + if (!config) { + pr_err("PLL configuration missing.\n"); + return -EINVAL; + } + + if (config->l) + regmap_write(regmap, PLL_L_VAL(pll), config->l); + + if (config->alpha) + regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); + + if (config->config_ctl_val) + regmap_write(regmap, PLL_CONFIG_CTL(pll), + config->config_ctl_val); + + if (config->config_ctl_hi_val) + regmap_write(regmap, PLL_CONFIG_CTL_U(pll), + config->config_ctl_hi_val); + + val = config->main_output_mask; + val |= config->aux_output_mask; + val |= config->aux2_output_mask; + val |= config->early_output_mask; + + mask = config->main_output_mask; + mask |= config->aux_output_mask; + mask |= config->aux2_output_mask; + mask |= config->early_output_mask; + + regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); + + if (config->post_div_mask) { + mask = config->post_div_mask; + val = config->post_div_val; + regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); + } + + if (config->test_ctl_val) + regmap_write(regmap, PLL_TEST_CTL(pll), + config->test_ctl_val); + + if (config->test_ctl_hi_val) + regmap_write(regmap, PLL_TEST_CTL_U(pll), + config->test_ctl_hi_val); + return 0; +} +EXPORT_SYMBOL(clk_agera_pll_configure); + +static int alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l, alpha_width = pll_alpha_width(pll); + unsigned long rrate; + u64 a; + + rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); + + /* + * Due to limited number of bits for fractional rate + * programming, the rounded up rate could be marginally + * higher than the requested rate. + */ + if (rrate > (rate + PLL_OUT_RATE_MARGIN) || rrate < rate) { + pr_err("Call set rate on the PLL with rounded rates!\n"); + return -EINVAL; + } + + /* change L_VAL without having to go through the power on sequence */ + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); + + /* Ensure that the write above goes through before proceeding. */ + mb(); + + if (clk_hw_is_enabled(hw)) + return wait_for_pll_enable_lock(pll); + + return 0; +} + +const struct clk_ops clk_agera_pll_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, + .enable = clk_alpha_pll_enable, + .disable = clk_alpha_pll_disable, + .is_enabled = clk_alpha_pll_is_enabled, + .recalc_rate = clk_alpha_pll_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = alpha_pll_agera_set_rate, +#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG + .list_rate_vdd_level = clk_list_rate_vdd_level, +#endif +}; +EXPORT_SYMBOL(clk_agera_pll_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 1397bf66e617..594e1901c738 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -22,6 +22,7 @@ enum { CLK_ALPHA_PLL_TYPE_LUCID_5LPE, CLK_ALPHA_PLL_TYPE_ZONDA_5LPE, CLK_ALPHA_PLL_TYPE_REGERA, + CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_MAX, }; @@ -156,6 +157,7 @@ extern const struct clk_ops clk_trion_pll_postdiv_ops; extern const struct clk_ops clk_trion_pll_ops; extern const struct clk_ops clk_regera_pll_ops; +extern const struct clk_ops clk_agera_pll_ops; void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); @@ -175,4 +177,6 @@ int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); +int clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); #endif From dcdabc5d84a29a949737414024a1806b0cf2ade2 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 8 Apr 2020 15:52:07 +0530 Subject: [PATCH 3/3] clk: qcom: clk-alpha-pll: Add support for Agera print registers Agera PLL print registers are required to get the PLL values from the debugfs, thus add support for the same. Change-Id: I4b708958e1125ce7e8eab945a3c15113739230d4 Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 53 ++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index ebcdec17a224..b305c5960883 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -3573,6 +3573,57 @@ static int alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static void clk_agera_pll_list_registers(struct seq_file *f, struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + int size, i, val; + + static struct clk_register_data data[] = { + {"PLL_MODE", PLL_OFF_MODE}, + {"PLL_L_VAL", PLL_OFF_L_VAL}, + {"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL}, + {"PLL_USER_CTL", PLL_OFF_USER_CTL}, + {"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL}, + {"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U}, + {"PLL_TEST_CTL", PLL_OFF_TEST_CTL}, + {"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U}, + {"PLL_STATUS", PLL_OFF_STATUS}, + }; + + static struct clk_register_data data1[] = { + {"APSS_PLL_VOTE", 0x0}, + }; + + + size = ARRAY_SIZE(data); + + for (i = 0; i < size; i++) { + regmap_read(pll->clkr.regmap, pll->offset + + pll->regs[data[i].offset], &val); + seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val); + } + + regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[0].offset], + &val); + if (val & PLL_FSM_ENA) { + regmap_read(pll->clkr.regmap, pll->clkr.enable_reg + + data1[0].offset, &val); + seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val); + } +} + +static struct clk_regmap_ops clk_agera_pll_regmap_ops = { + .list_registers = clk_agera_pll_list_registers, +}; + +static void clk_agera_pll_init(struct clk_hw *hw) +{ + struct clk_regmap *rclk = to_clk_regmap(hw); + + if (!rclk->ops) + rclk->ops = &clk_agera_pll_regmap_ops; +} + const struct clk_ops clk_agera_pll_ops = { .prepare = clk_prepare_regmap, .unprepare = clk_unprepare_regmap, @@ -3584,6 +3635,8 @@ const struct clk_ops clk_agera_pll_ops = { .recalc_rate = clk_alpha_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .set_rate = alpha_pll_agera_set_rate, + .debug_init = clk_common_debug_init, + .init = clk_agera_pll_init, #ifdef CONFIG_COMMON_CLK_QCOM_DEBUG .list_rate_vdd_level = clk_list_rate_vdd_level, #endif