From 47510aa48a3a36e01c023558ca27f0ba2f176394 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 9 Dec 2020 18:54:48 +0800 Subject: [PATCH] ARM: dts: msm: Add QDSS IPA bam connection config for sdxlemur Add QDSS IPA bam connection config for QDSS to pcie hw transfer. Change-Id: Ia129b5f201a44b89d29ef91bb557616183af4c43 --- bindings/arm/coresight.txt | 3 +++ qcom/sdxlemur-coresight.dtsi | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/bindings/arm/coresight.txt b/bindings/arm/coresight.txt index 9991ffa3e0d9..a4d29ec88108 100644 --- a/bindings/arm/coresight.txt +++ b/bindings/arm/coresight.txt @@ -151,6 +151,9 @@ its hardware characteristcs. * cti-flush-trig-num: Specifies the flush CTI trigger number for TMC ETR and TMC ETF. + * qcom,qdss-ipa-support : indicates whether qdss to ipa bam connection + need to support. + * Optional property for CATU and APSS : * interrupts : Exactly one SPI may be listed for reporting the address error for CATU and four interrupts for TGU to get trigger from four diff --git a/qcom/sdxlemur-coresight.dtsi b/qcom/sdxlemur-coresight.dtsi index 073cfa4332f9..2678a9b36f87 100644 --- a/qcom/sdxlemur-coresight.dtsi +++ b/qcom/sdxlemur-coresight.dtsi @@ -148,6 +148,13 @@ arm,buffer-size = <0x400000>; arm,scatter-gather; + qcom,qdss-ipa-support; + ipa-conn-data-base-pa = <0x1468B000>; + ipa-conn-data-size = <0x3000>; + ipa-conn-desc-base-pa = <0x1468E000>; + ipa-conn-desc-size = <0x1000>; + ipa-peer-evt-reg-pa = <0x6077818>; + coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti3_swao>; cti-reset-trig-num = <0>;