From 983f5822e94dc5f578e8ec66146482a10f7173dc Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Fri, 19 Feb 2021 16:28:56 +0800 Subject: [PATCH] ARM: dts: msm: Disable SDCC TPDMs on yupik Disable all SDCC TPDMs on yupik first since there is SDCC internal clock issue. Change-Id: I029e8df0b6519805124a100e94f614790bae934c --- qcom/yupik-coresight.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/yupik-coresight.dtsi b/qcom/yupik-coresight.dtsi index 9cfb1d554902..9d0b985226b8 100644 --- a/qcom/yupik-coresight.dtsi +++ b/qcom/yupik-coresight.dtsi @@ -2351,6 +2351,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-1"; clocks = <&aopcc QDSS_CLK>; @@ -2373,6 +2374,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-4"; clocks = <&aopcc QDSS_CLK>; @@ -2538,6 +2540,7 @@ reg-names = "tpdm-base"; qcom,cmb-msr-skip; + status = "disabled"; coresight-name = "coresight-tpdm-sdcc-2"; clocks = <&aopcc QDSS_CLK>;