diff --git a/qcom/sa8195p-regulator.dtsi b/qcom/sa8195p-regulator.dtsi index 2554e103dc92..5d480a9a464b 100644 --- a/qcom/sa8195p-regulator.dtsi +++ b/qcom/sa8195p-regulator.dtsi @@ -336,12 +336,10 @@ L17A: pm8195_1_l17: regulator-pm8195-1-l17 { regulator-name = "pm8195_1_l17"; qcom,set = ; - regulator-min-microvolt = <2504000>; + regulator-min-microvolt = <1700000>; regulator-max-microvolt = <3544000>; - qcom,init-voltage = <2904000>; + qcom,init-voltage = <1700000>; qcom,init-mode = ; - regulator-system-load = <1>; - regulator-always-on; }; }; @@ -696,7 +694,6 @@ regulator-max-microvolt = <3544000>; qcom,init-voltage = <2500000>; qcom,init-mode = ; - regulator-always-on; }; }; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 9ed8062fb621..10532f45caff 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -59,36 +59,6 @@ status= "ok"; }; -&ufs2phy_mem { - compatible = "qcom,ufs-phy-qmp-v4"; - vdda-phy-supply = <&pm8195_3_l5>; - vdda-pll-supply = <&pm8195_1_l9>; - vdda-phy-max-microamp = <138000>; - vdda-pll-max-microamp = <65100>; - - status = "ok"; -}; - -&ufshc2_mem { - vdd-hba-supply = <&ufs_card_2_gdsc>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm8195_1_l17>; - vcc-voltage-level = <2894000 2904000>; - vcc-low-voltage-sup; - vccq-supply = <&pm8195_2_l5>; - vccq2-supply = <&pm8195_s4>; - vcc-max-microamp = <750000>; - vccq-max-microamp = <750000>; - vccq2-max-microamp = <750000>; - - qcom,vddp-ref-clk-supply = <&pm8195_2_l5>; - qcom,vddp-ref-clk-max-microamp = <100>; - qcom,vccq-parent-supply = <&pm8195_1_s2>; - qcom,vccq-parent-max-microamp = <210000>; - - status= "ok"; -}; - &usb2_phy0 { vdd-supply = <&pm8195_3_l5>; vdda18-supply = <&pm8195_1_l12>; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 500293df7983..300784e45dbf 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -35,7 +35,6 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ - ufshc2 = &ufshc2_mem; /* Embedded 2nd UFS slot */ serial0 = &qupv3_se12_2uart; sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ spi22 = &qupv3_se22_spi; @@ -1432,8 +1431,6 @@ interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; - spm-level = <5>; - rpm-level = <1>; #reset-cells = <1>; lanes-per-direction = <2>; @@ -1539,140 +1536,6 @@ status = "disabled"; }; - ufs2phy_mem: ufsphy_mem@1d67000 { - reg = <0x1d67000 0xe00>; /* PHY regs */ - reg-names = "phy_mem"; - #phy-cells = <0>; - - lanes-per-direction = <2>; - - clock-names = "ref_clk_src", - "ref_clk", - "ref_aux_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_CARD_CLKREF_CLK>, - <&gcc GCC_UFS_CARD_2_PHY_AUX_CLK>; - - resets = <&ufshc2_mem 0>; - status = "disabled"; - }; - - ufshc2_mem: ufshc@1d64000 { - compatible = "qcom,ufshc"; - reg = <0x1d64000 0x3000>, - <0x1d70000 0x8000>; - reg-names = "ufs_mem", "ufs_ice"; - interrupts = ; - phys = <&ufs2phy_mem>; - phy-names = "ufsphy"; - spm-level = <5>; - rpm-level = <1>; - #reset-cells = <1>; - - lanes-per-direction = <2>; - dev-ref-clk-freq = <0>; /* 19.2 MHz */ - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "core_clk_ice", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_CARD_2_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_CARD_2_AXI_CLK>, - <&gcc GCC_UFS_CARD_2_AHB_CLK>, - <&gcc GCC_UFS_CARD_2_UNIPRO_CORE_CLK>, - <&gcc GCC_UFS_CARD_2_ICE_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_CARD_2_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_CARD_2_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_CARD_2_RX_SYMBOL_1_CLK>; - freq-table-hz = - <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, - <37500000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - interconnects = - <&aggre1_noc MASTER_UFS_GEN4 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC - &config_noc SLAVE_UFS_MEM_1_CFG>; - interconnect-names = "ufs-ddr", "cpu-ufs"; - - qcom,ufs-bus-bw,name = "ufshc_mem"; - qcom,ufs-bus-bw,num-cases = <26>; - qcom,ufs-bus-bw,num-paths = <2>; - qcom,ufs-bus-bw,vectors-KBps = - /* - * During HS G3 UFS runs at nominal voltage corner, vote - * higher bandwidth to push other buses in the data path - * to run at nominal to achieve max throughput. - * 4GBps pushes BIMC to run at nominal. - * 200MBps pushes CNOC to run at nominal. - * Vote for half of this bandwidth for HS G3 1-lane. - * For max bandwidth, vote high enough to push the buses - * to run in turbo voltage corner. - */ - <0 0>, <0 0>, /* No vote */ - <922 0>, <1000 0>, /* PWM G1 */ - <1844 0>, <1000 0>, /* PWM G2 */ - <3688 0>, <1000 0>, /* PWM G3 */ - <7376 0>, <1000 0>, /* PWM G4 */ - <1844 0>, <1000 0>, /* PWM G1 L2 */ - <3688 0>, <1000 0>, /* PWM G2 L2 */ - <7376 0>, <1000 0>, /* PWM G3 L2 */ - <14752 0>, <1000 0>, /* PWM G4 L2 */ - <127796 0>, <1000 0>, /* HS G1 RA */ - <255591 0>, <1000 0>, /* HS G2 RA */ - <2097152 0>, <102400 0>, /* HS G3 RA */ - <4194304 0>, <204800 0>, /* HS G4 RA */ - <255591 0>, <1000 0>, /* HS G1 RA L2 */ - <511181 0>, <1000 0>, /* HS G2 RA L2 */ - <4194304 0>, <204800 0>, /* HS G3 RA L2 */ - <8388608 0>, <409600 0>, /* HS G4 RA L2 */ - <149422 0>, <1000 0>, /* HS G1 RB */ - <298189 0>, <1000 0>, /* HS G2 RB */ - <2097152 0>, <102400 0>, /* HS G3 RB */ - <4194304 0>, <204800 0>, /* HS G4 RB */ - <298189 0>, <1000 0>, /* HS G1 RB L2 */ - <596378 0>, <1000 0>, /* HS G2 RB L2 */ - /* As UFS working in HS G3 RB L2 mode, aggregated - * bandwidth (AB) should take care of providing - * optimum throughput requested. However, as tested, - * in order to scale up CNOC clock, instantaneous - * bindwidth (IB) needs to be given a proper value too. - */ - <4194304 0>, <204800 409600>, /* HS G3 RB L2 */ - <8388608 0>, <409600 409600>, /* HS G4 RB L2 */ - <7643136 0>, <307200 0>; /* Max. bandwidth */ - - qcom,bus-vector-names = "MIN", - "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", - "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", - "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", - "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", - "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", - "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", - "MAX"; - - reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; - - resets = <&gcc GCC_UFS_CARD_2_BCR>; - reset-names = "rst"; - - secondary-storage; - status = "disabled"; - }; - spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1000>,