From ffb26ccd6c7382c117e1f351624af1a2d18a6419 Mon Sep 17 00:00:00 2001 From: Zhiqiang Tu Date: Mon, 18 Jan 2021 17:05:15 +0800 Subject: [PATCH] ARM: dts: msm: Add hab and peripherals for sa8155 vm Add hab, pinctrl, qup, sdhci, usb and pcie for sa8155 virtual machine. Change-Id: I16d85f1d18f0e48fa76859f7fdc7092cc448ae13 --- qcom/quin-vm-common.dtsi | 97 ++++++++++- qcom/sa8155-vm-la.dtsi | 24 +++ qcom/sa8155-vm-lv-mt.dtsi | 24 +++ qcom/sa8155-vm-lv.dtsi | 24 +++ qcom/sa8155-vm-pcie.dtsi | 272 +++++++++++++++++++++++++++++ qcom/sa8155-vm-usb.dtsi | 351 ++++++++++++++++++++++++++++++++++++++ qcom/sa8155-vm.dtsi | 127 +++++++++++++- 7 files changed, 913 insertions(+), 6 deletions(-) create mode 100644 qcom/sa8155-vm-pcie.dtsi create mode 100644 qcom/sa8155-vm-usb.dtsi diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index a8993b0c00a1..2f1643b12a3d 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -21,7 +21,7 @@ ranges; /* global autoconfigured region for contiguous allocations */ - linux,cma { + linux_cma: linux,cma { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; @@ -50,24 +50,34 @@ firmware: firmware { android { compatible = "android,firmware"; + boot_devices = "vdevs/1c140000.virtio_blk,vdevs/1c0b0000.virtio_blk,vdevs/1c0f0000.virtio_blk"; + vbmeta { compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; + parts = "vbmeta,system,vendor"; }; fstab { compatible = "android,fstab"; vendor { compatible = "android,vendor"; - dev="/dev/block/platform/vdevs/1c0f0000.virtio_blk/vdc"; + dev="/dev/block/platform/vdevs/1c0f0000.virtio_blk/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait"; + fsmgr_flags = "wait,avb"; status = "ok"; }; }; }; }; + + vdevs { + compatible = "simple-bus"; + virtio_input_keyboard@1c150000 { + compatible = "virtio,mmio"; + virtio,wakeup; + }; + }; }; &soc { @@ -115,7 +125,7 @@ system_heap: qcom,ion-heap@25 { reg = ; - qcom,ion-heap-type = "SYSTEM"; + qcom,ion-heap-type = "MSM_SYSTEM"; }; qcom,ion-heap@27 { /* QSEECOM HEAP */ @@ -131,6 +141,83 @@ }; }; + hab: qcom,hab { + compatible = "qcom,hab"; + vmid = <2>; + + mmidgrp100: mmidgrp100 { + grp-start-id = <100>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp200: mmidgrp200 { + grp-start-id = <200>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp300: mmidgrp300 { + grp-start-id = <300>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp400: mmidgrp400 { + grp-start-id = <400>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp500: mmidgrp500 { + grp-start-id = <500>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp600: mmidgrp600 { + grp-start-id = <600>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp700: mmidgrp700 { + grp-start-id = <700>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp800: mmidgrp800 { + grp-start-id = <800>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp900: mmidgrp900 { + grp-start-id = <900>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1000: mmidgrp1000 { + grp-start-id = <1000>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1100: mmidgrp1100 { + grp-start-id = <1100>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1200: mmidgrp1200 { + grp-start-id = <1200>; + role = "fe"; + remote-vmids = <0>; + }; + }; + qcom,msm-imem@14680000 { compatible = "qcom,msm-imem"; reg = <0x14680000 0x1000>; diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi index c38dc4de64e2..ee0d8a882248 100644 --- a/qcom/sa8155-vm-la.dtsi +++ b/qcom/sa8155-vm-la.dtsi @@ -4,3 +4,27 @@ label = "pmem_shared_mem"; }; }; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&sdhc_2 { + status = "ok"; +}; diff --git a/qcom/sa8155-vm-lv-mt.dtsi b/qcom/sa8155-vm-lv-mt.dtsi index 63e1d6eabba3..509403ae2ea3 100644 --- a/qcom/sa8155-vm-lv-mt.dtsi +++ b/qcom/sa8155-vm-lv-mt.dtsi @@ -1,6 +1,30 @@ +&hab { + vmid = <3>; +}; + &reserved_memory { pmem_shared: pmem_shared_region { reg = <0x1 0x2c200000 0x0 0x53e00000>; label = "pmem_shared_mem"; }; }; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; diff --git a/qcom/sa8155-vm-lv.dtsi b/qcom/sa8155-vm-lv.dtsi index c38dc4de64e2..e1c40cd0133b 100644 --- a/qcom/sa8155-vm-lv.dtsi +++ b/qcom/sa8155-vm-lv.dtsi @@ -1,6 +1,30 @@ +&hab { + vmid = <3>; +}; + &reserved_memory { pmem_shared: pmem_shared_region { reg = <0x1 0x6a500000 0x0 0x51400000>; label = "pmem_shared_mem"; }; }; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; diff --git a/qcom/sa8155-vm-pcie.dtsi b/qcom/sa8155-vm-pcie.dtsi new file mode 100644 index 000000000000..9f935edf9c43 --- /dev/null +++ b/qcom/sa8155-vm-pcie.dtsi @@ -0,0 +1,272 @@ +#include +#include + + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c06000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x60200000 0x100000>, + <0x60300000 0x3d00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x051c 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x1e 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0460 0x30 0x0 + 0x0464 0xc0 0x0 + 0x05bc 0x0c 0x0 + 0x04dc 0x0d 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0cbc 0x00 0x0 + 0x0ce0 0x58 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x88 0x0 + 0x0998 0x0b 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x01 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1p8-supply = <&pm8150_2_l8>; + vreg-0p9-supply = <&pm8150_2_l18>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + qcom,bw-scale = ; + + qcom,no-l0s-supported; + msi-parent = <&pcie0_msi>; + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0x814>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x840>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2110>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d80>; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + qcom,core-preset = <0x77777777>; + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>, + <0x200 &apps_smmu 0x1d82 0x1>, + <0x300 &apps_smmu 0x1d83 0x1>, + <0x400 &apps_smmu 0x1d84 0x1>, + <0x500 &apps_smmu 0x1d85 0x1>, + <0x600 &apps_smmu 0x1d86 0x1>, + <0x700 &apps_smmu 0x1d87 0x1>, + <0x800 &apps_smmu 0x1d88 0x1>, + <0x900 &apps_smmu 0x1d89 0x1>, + <0xa00 &apps_smmu 0x1d8a 0x1>, + <0xb00 &apps_smmu 0x1d8b 0x1>, + <0xc00 &apps_smmu 0x1d8c 0x1>, + <0xd00 &apps_smmu 0x1d8d 0x1>, + <0xe00 &apps_smmu 0x1d8e 0x1>, + <0xf00 &apps_smmu 0x1d8f 0x1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + pcie_rc0: pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; + reg = <0 0 0 0 0>; + pci-ids = "17cb:0108"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + +}; diff --git a/qcom/sa8155-vm-usb.dtsi b/qcom/sa8155-vm-usb.dtsi new file mode 100644 index 000000000000..bab658611352 --- /dev/null +++ b/qcom/sa8155-vm-usb.dtsi @@ -0,0 +1,351 @@ +#include +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-dma = "bypass"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,charging-disabled; + qcom,ignore-wakeup-src-in-hostmode; + + status = "disabled"; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + usb-core-id = <0>; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + status = "disabled"; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e2000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e2000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_1_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_1_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70 + 0x01 0xb0>; + qcom,rcal-mask = <0x1e00000>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2phy_ac_en1_default>; + + status = "disabled"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x160 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + qcom,default-mode-host; + qcom,ignore-wakeup-src-in-hostmode; + + USB3_GDSC-supply = <&usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,charging-disabled; + + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_qmp_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,ssp-u3-u0-quirk; + snps,usb3-u1u2-disable; + usb-core-id = <1>; + tx-fifo-resize; + maximum-speed = "super-speed-plus"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_1_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_1_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70 + 0x01 0xb0>; + qcom,rcal-mask = <0x1e00000>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2phy_ac_en2_default>; + + status = "disabled"; + }; + + /* Secondary USB port related QMP PHY */ + usb_qmp_phy: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88eb000 0x1000>, + <0x088eb88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pm8150_1_l5>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8150_2_l8>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + status = "disabled"; + }; +}; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 6c89f083c055..f4092adea4aa 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -1,5 +1,7 @@ #include +#include #include +#include #include #include #include "quin-vm-common.dtsi" @@ -8,10 +10,24 @@ model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine"; qcom,msm-name = "SA8155 V2"; qcom,msm-id = <362 0x20000>; + + aliases { + hsuart0 = &qupv3_se13_4uart; + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; }; - &soc { + VDD_CX_LEVEL: VDD_MMCX_LEVEL: + S9C_LEVEL: pm8150_2_s9_level: regulator-pm8150-2-s9-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_s9_level"; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + }; + apps_smmu: apps-smmu@0x15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, @@ -107,6 +123,80 @@ , ; }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + bus-width = <4>; + qcom,restore-after-cx-collapse; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 25 MB/s */ + <65360 100000>, <100000 100000>, + /* 50 MB/s */ + <130718 200000>, <133320 133320>, + /* 100 MB/s */ + <261438 200000>, <150000 150000>, + /* 200 MB/s */ + <261438 400000>, <300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 4096000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 201500000>; + + vdd-supply = <&pm8150_1_l17>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150_2_l13>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + broken-cd; + qcom,nonhotplug; + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <44>; + }; + + qos1 { + mask = <0xc0>; + vote = <44>; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8150-pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <6 486 6>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; }; ®ulator { @@ -194,3 +284,38 @@ regulator-max-microvolt = <2040000>; }; }; + +#include "sm8150-pinctrl.dtsi" +#include "sm8150-slpi-pinctrl.dtsi" +#include "sa8155-vm-usb.dtsi" +#include "sa8155-vm-pcie.dtsi" +#include "sm8150-qupv3.dtsi" +#include "sm8150-ssc-qupv3.dtsi" + +&tlmm { + /delete-property/ wakeup-parent; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&qupv3_0 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_1 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_2 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +}; + +&qupv3_3 { + /delete-property/ qcom,msm-bus,num-paths; + /delete-property/ qcom,msm-bus,vectors-bus-ids; +};