mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: (27 commits) [IA64] kdump: Add crash_save_vmcoreinfo for INIT [IA64] Fix NUMA configuration issue [IA64] Itanium Spec updates [IA64] Untangle sync_icache_dcache() page size determination [IA64] arch/ia64/kernel/: use time_* macros [IA64] remove redundant display of free swap space in show_mem() [IA64] make IOMMU respect the segment boundary limits [IA64] kprobes: kprobe-booster for ia64 [IA64] fix getpid and set_tid_address fast system calls for pid namespaces [IA64] Replace explicit jiffies tests with time_* macros. [IA64] use goto to jump out do/while_each_thread [IA64] Fix unlock ordering in smp_callin [IA64] pgd_offset() constfication. [IA64] kdump: crash.c coding style fix [IA64] kdump: add kdump_on_fatal_mca [IA64] Minimize per_cpu reservations. [IA64] Correct pernodesize calculation. [IA64] Kernel parameter for max number of concurrent global TLB purges [IA64] Multiple outstanding ptc.g instruction support [IA64] Implement smp_call_function_mask for ia64 ...
This commit is contained in:
Linus Torvalds
commit
4786b4ee22
50 changed files with 2965 additions and 544 deletions
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@ -35,6 +35,7 @@
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#include <linux/init.h>
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#include <linux/numa.h>
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#include <asm/system.h>
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#include <asm/numa.h>
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#define COMPILER_DEPENDENT_INT64 long
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#define COMPILER_DEPENDENT_UINT64 unsigned long
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@ -115,7 +116,11 @@ extern unsigned int is_cpu_cpei_target(unsigned int cpu);
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extern void set_cpei_target_cpu(unsigned int cpu);
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extern unsigned int get_cpei_target_cpu(void);
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extern void prefill_possible_map(void);
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#ifdef CONFIG_ACPI_HOTPLUG_CPU
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extern int additional_cpus;
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#else
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#define additional_cpus 0
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#endif
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#ifdef CONFIG_ACPI_NUMA
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#if MAX_NUMNODES > 256
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@ -129,6 +134,34 @@ extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
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#define acpi_unlazy_tlb(x)
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#ifdef CONFIG_ACPI_NUMA
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extern cpumask_t early_cpu_possible_map;
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#define for_each_possible_early_cpu(cpu) \
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for_each_cpu_mask((cpu), early_cpu_possible_map)
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static inline void per_cpu_scan_finalize(int min_cpus, int reserve_cpus)
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{
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int low_cpu, high_cpu;
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int cpu;
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int next_nid = 0;
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low_cpu = cpus_weight(early_cpu_possible_map);
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high_cpu = max(low_cpu, min_cpus);
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high_cpu = min(high_cpu + reserve_cpus, NR_CPUS);
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for (cpu = low_cpu; cpu < high_cpu; cpu++) {
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cpu_set(cpu, early_cpu_possible_map);
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if (node_cpuid[cpu].nid == NUMA_NO_NODE) {
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node_cpuid[cpu].nid = next_nid;
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next_nid++;
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if (next_nid >= num_online_nodes())
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next_nid = 0;
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}
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}
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}
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#endif /* CONFIG_ACPI_NUMA */
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#endif /*__KERNEL__*/
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#endif /*_ASM_ACPI_H*/
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@ -1,6 +1,110 @@
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/*
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* include/asm-ia64/cputime.h:
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* Definitions for measuring cputime on ia64 machines.
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*
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* Based on <asm-powerpc/cputime.h>.
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*
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* Copyright (C) 2007 FUJITSU LIMITED
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* Copyright (C) 2007 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* If we have CONFIG_VIRT_CPU_ACCOUNTING, we measure cpu time in nsec.
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* Otherwise we measure cpu time in jiffies using the generic definitions.
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*/
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#ifndef __IA64_CPUTIME_H
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#define __IA64_CPUTIME_H
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#ifndef CONFIG_VIRT_CPU_ACCOUNTING
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#include <asm-generic/cputime.h>
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#else
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#include <linux/time.h>
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#include <linux/jiffies.h>
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#include <asm/processor.h>
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typedef u64 cputime_t;
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typedef u64 cputime64_t;
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#define cputime_zero ((cputime_t)0)
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#define cputime_max ((~((cputime_t)0) >> 1) - 1)
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#define cputime_add(__a, __b) ((__a) + (__b))
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#define cputime_sub(__a, __b) ((__a) - (__b))
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#define cputime_div(__a, __n) ((__a) / (__n))
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#define cputime_halve(__a) ((__a) >> 1)
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#define cputime_eq(__a, __b) ((__a) == (__b))
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#define cputime_gt(__a, __b) ((__a) > (__b))
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#define cputime_ge(__a, __b) ((__a) >= (__b))
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#define cputime_lt(__a, __b) ((__a) < (__b))
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#define cputime_le(__a, __b) ((__a) <= (__b))
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#define cputime64_zero ((cputime64_t)0)
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#define cputime64_add(__a, __b) ((__a) + (__b))
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#define cputime64_sub(__a, __b) ((__a) - (__b))
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#define cputime_to_cputime64(__ct) (__ct)
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/*
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* Convert cputime <-> jiffies (HZ)
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*/
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#define cputime_to_jiffies(__ct) ((__ct) / (NSEC_PER_SEC / HZ))
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#define jiffies_to_cputime(__jif) ((__jif) * (NSEC_PER_SEC / HZ))
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#define cputime64_to_jiffies64(__ct) ((__ct) / (NSEC_PER_SEC / HZ))
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#define jiffies64_to_cputime64(__jif) ((__jif) * (NSEC_PER_SEC / HZ))
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/*
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* Convert cputime <-> milliseconds
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*/
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#define cputime_to_msecs(__ct) ((__ct) / NSEC_PER_MSEC)
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#define msecs_to_cputime(__msecs) ((__msecs) * NSEC_PER_MSEC)
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/*
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* Convert cputime <-> seconds
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*/
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#define cputime_to_secs(__ct) ((__ct) / NSEC_PER_SEC)
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#define secs_to_cputime(__secs) ((__secs) * NSEC_PER_SEC)
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/*
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* Convert cputime <-> timespec (nsec)
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*/
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static inline cputime_t timespec_to_cputime(const struct timespec *val)
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{
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cputime_t ret = val->tv_sec * NSEC_PER_SEC;
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return (ret + val->tv_nsec);
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}
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static inline void cputime_to_timespec(const cputime_t ct, struct timespec *val)
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{
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val->tv_sec = ct / NSEC_PER_SEC;
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val->tv_nsec = ct % NSEC_PER_SEC;
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}
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/*
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* Convert cputime <-> timeval (msec)
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*/
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static inline cputime_t timeval_to_cputime(struct timeval *val)
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{
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cputime_t ret = val->tv_sec * NSEC_PER_SEC;
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return (ret + val->tv_usec * NSEC_PER_USEC);
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}
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static inline void cputime_to_timeval(const cputime_t ct, struct timeval *val)
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{
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val->tv_sec = ct / NSEC_PER_SEC;
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val->tv_usec = (ct % NSEC_PER_SEC) / NSEC_PER_USEC;
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}
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/*
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* Convert cputime <-> clock (USER_HZ)
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*/
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#define cputime_to_clock_t(__ct) ((__ct) / (NSEC_PER_SEC / USER_HZ))
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#define clock_t_to_cputime(__x) ((__x) * (NSEC_PER_SEC / USER_HZ))
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/*
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* Convert cputime64 to clock.
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*/
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#define cputime64_to_clock_t(__ct) cputime_to_clock_t((cputime_t)__ct)
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#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
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#endif /* __IA64_CPUTIME_H */
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@ -26,6 +26,7 @@
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#define ELF_ARCH EM_IA_64
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#define USE_ELF_CORE_DUMP
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#define CORE_DUMP_USE_REGSET
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/* Least-significant four bits of ELF header's e_flags are OS-specific. The bits are
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interpreted as follows by Linux: */
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@ -154,6 +155,30 @@ extern void ia64_init_addr_space (void);
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#define ELF_NGREG 128 /* we really need just 72 but let's leave some headroom... */
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#define ELF_NFPREG 128 /* f0 and f1 could be omitted, but so what... */
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/* elf_gregset_t register offsets */
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#define ELF_GR_0_OFFSET 0
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#define ELF_NAT_OFFSET (32 * sizeof(elf_greg_t))
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#define ELF_PR_OFFSET (33 * sizeof(elf_greg_t))
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#define ELF_BR_0_OFFSET (34 * sizeof(elf_greg_t))
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#define ELF_CR_IIP_OFFSET (42 * sizeof(elf_greg_t))
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#define ELF_CFM_OFFSET (43 * sizeof(elf_greg_t))
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#define ELF_CR_IPSR_OFFSET (44 * sizeof(elf_greg_t))
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#define ELF_GR_OFFSET(i) (ELF_GR_0_OFFSET + i * sizeof(elf_greg_t))
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#define ELF_BR_OFFSET(i) (ELF_BR_0_OFFSET + i * sizeof(elf_greg_t))
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#define ELF_AR_RSC_OFFSET (45 * sizeof(elf_greg_t))
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#define ELF_AR_BSP_OFFSET (46 * sizeof(elf_greg_t))
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#define ELF_AR_BSPSTORE_OFFSET (47 * sizeof(elf_greg_t))
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#define ELF_AR_RNAT_OFFSET (48 * sizeof(elf_greg_t))
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#define ELF_AR_CCV_OFFSET (49 * sizeof(elf_greg_t))
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#define ELF_AR_UNAT_OFFSET (50 * sizeof(elf_greg_t))
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#define ELF_AR_FPSR_OFFSET (51 * sizeof(elf_greg_t))
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#define ELF_AR_PFS_OFFSET (52 * sizeof(elf_greg_t))
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#define ELF_AR_LC_OFFSET (53 * sizeof(elf_greg_t))
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#define ELF_AR_EC_OFFSET (54 * sizeof(elf_greg_t))
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#define ELF_AR_CSD_OFFSET (55 * sizeof(elf_greg_t))
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#define ELF_AR_SSD_OFFSET (56 * sizeof(elf_greg_t))
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#define ELF_AR_END_OFFSET (57 * sizeof(elf_greg_t))
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typedef unsigned long elf_fpxregset_t;
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typedef unsigned long elf_greg_t;
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@ -183,12 +208,6 @@ extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst);
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struct task_struct;
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extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
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extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *);
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#define ELF_CORE_COPY_TASK_REGS(tsk, elf_gregs) dump_task_regs(tsk, elf_gregs)
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#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
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#define GATE_EHDR ((const struct elfhdr *) GATE_ADDR)
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/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
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@ -30,8 +30,12 @@
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#include <asm/break.h>
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#define __ARCH_WANT_KPROBES_INSN_SLOT
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#define MAX_INSN_SIZE 1
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#define MAX_INSN_SIZE 2 /* last half is for kprobe-booster */
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#define BREAK_INST (long)(__IA64_BREAK_KPROBE << 6)
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#define NOP_M_INST (long)(1<<27)
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#define BRL_INST(i1, i2) ((long)((0xcL << 37) | /* brl */ \
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(0x1L << 12) | /* many */ \
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(((i1) & 1) << 36) | ((i2) << 13))) /* imm */
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typedef union cmp_inst {
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struct {
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@ -112,6 +116,7 @@ struct arch_specific_insn {
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#define INST_FLAG_FIX_RELATIVE_IP_ADDR 1
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#define INST_FLAG_FIX_BRANCH_REG 2
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#define INST_FLAG_BREAK_INST 4
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#define INST_FLAG_BOOSTABLE 8
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unsigned long inst_flag;
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unsigned short target_br_reg;
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unsigned short slot;
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|
|
|
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|
|
@ -31,6 +31,9 @@
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#define IA64_TR_PALCODE 1 /* itr1: maps PALcode as required by EFI */
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#define IA64_TR_CURRENT_STACK 1 /* dtr1: maps kernel's memory- & register-stacks */
|
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|
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#define IA64_TR_ALLOC_BASE 2 /* itr&dtr: Base of dynamic TR resource*/
|
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#define IA64_TR_ALLOC_MAX 32 /* Max number for dynamic use*/
|
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|
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/* Processor status register bits: */
|
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#define IA64_PSR_BE_BIT 1
|
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#define IA64_PSR_UP_BIT 2
|
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|
|
|
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|
|
@ -35,6 +35,7 @@ extern void find_memory (void);
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extern void reserve_memory (void);
|
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extern void find_initrd (void);
|
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extern int filter_rsvd_memory (unsigned long start, unsigned long end, void *arg);
|
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extern int filter_memory (unsigned long start, unsigned long end, void *arg);
|
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extern unsigned long efi_memmap_init(unsigned long *s, unsigned long *e);
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extern int find_max_min_low_pfn (unsigned long , unsigned long, void *);
|
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|
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|
|
@ -56,7 +57,7 @@ extern int reserve_elfcorehdr(unsigned long *start, unsigned long *end);
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|
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#define IGNORE_PFN0 1 /* XXX fix me: ignore pfn 0 until TLB miss handler is updated... */
|
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|
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extern int register_active_ranges(u64 start, u64 end, void *arg);
|
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extern int register_active_ranges(u64 start, u64 len, int nid);
|
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|
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#ifdef CONFIG_VIRTUAL_MEM_MAP
|
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# define LARGE_GAP 0x40000000 /* Use virtual mem map if hole is > than this */
|
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|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
|
||||
#include <asm/mmzone.h>
|
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|
||||
#define NUMA_NO_NODE -1
|
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|
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extern u16 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
|
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extern cpumask_t node_to_cpu_mask[MAX_NUMNODES] __cacheline_aligned;
|
||||
extern pg_data_t *pgdat_list[MAX_NUMNODES];
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
* Copyright (C) 1999 VA Linux Systems
|
||||
* Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
|
||||
* Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
|
||||
* Copyright (C) 2008 Silicon Graphics, Inc. (SGI)
|
||||
*
|
||||
* 99/10/01 davidm Make sure we pass zero for reserved parameters.
|
||||
* 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
|
||||
|
|
@ -73,6 +74,8 @@
|
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#define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */
|
||||
#define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */
|
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#define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */
|
||||
#define PAL_VP_INFO 50 /* Information about virtual processor features */
|
||||
#define PAL_MC_HW_TRACKING 51 /* Hardware tracking status */
|
||||
|
||||
#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
|
||||
#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
|
||||
|
|
@ -504,7 +507,8 @@ typedef struct pal_cache_check_info_s {
|
|||
wiv : 1, /* Way field valid */
|
||||
reserved2 : 1,
|
||||
dp : 1, /* Data poisoned on MBE */
|
||||
reserved3 : 8,
|
||||
reserved3 : 6,
|
||||
hlth : 2, /* Health indicator */
|
||||
|
||||
index : 20, /* Cache line index */
|
||||
reserved4 : 2,
|
||||
|
|
@ -542,7 +546,9 @@ typedef struct pal_tlb_check_info_s {
|
|||
dtc : 1, /* Fail in data TC */
|
||||
itc : 1, /* Fail in inst. TC */
|
||||
op : 4, /* Cache operation */
|
||||
reserved3 : 30,
|
||||
reserved3 : 6,
|
||||
hlth : 2, /* Health indicator */
|
||||
reserved4 : 22,
|
||||
|
||||
is : 1, /* instruction set (1 == ia32) */
|
||||
iv : 1, /* instruction set field valid */
|
||||
|
|
@ -633,7 +639,8 @@ typedef struct pal_uarch_check_info_s {
|
|||
way : 6, /* Way of structure */
|
||||
wv : 1, /* way valid */
|
||||
xv : 1, /* index valid */
|
||||
reserved1 : 8,
|
||||
reserved1 : 6,
|
||||
hlth : 2, /* Health indicator */
|
||||
index : 8, /* Index or set of the uarch
|
||||
* structure that failed.
|
||||
*/
|
||||
|
|
@ -1213,14 +1220,12 @@ ia64_pal_mc_drain (void)
|
|||
|
||||
/* Return the machine check dynamic processor state */
|
||||
static inline s64
|
||||
ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
|
||||
ia64_pal_mc_dynamic_state (u64 info_type, u64 dy_buffer, u64 *size)
|
||||
{
|
||||
struct ia64_pal_retval iprv;
|
||||
PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
|
||||
PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, info_type, dy_buffer, 0);
|
||||
if (size)
|
||||
*size = iprv.v0;
|
||||
if (pds)
|
||||
*pds = iprv.v1;
|
||||
return iprv.status;
|
||||
}
|
||||
|
||||
|
|
@ -1281,15 +1286,41 @@ ia64_pal_mc_expected (u64 expected, u64 *previous)
|
|||
return iprv.status;
|
||||
}
|
||||
|
||||
typedef union pal_hw_tracking_u {
|
||||
u64 pht_data;
|
||||
struct {
|
||||
u64 itc :4, /* Instruction cache tracking */
|
||||
dct :4, /* Date cache tracking */
|
||||
itt :4, /* Instruction TLB tracking */
|
||||
ddt :4, /* Data TLB tracking */
|
||||
reserved:48;
|
||||
} pal_hw_tracking_s;
|
||||
} pal_hw_tracking_u_t;
|
||||
|
||||
/*
|
||||
* Hardware tracking status.
|
||||
*/
|
||||
static inline s64
|
||||
ia64_pal_mc_hw_tracking (u64 *status)
|
||||
{
|
||||
struct ia64_pal_retval iprv;
|
||||
PAL_CALL(iprv, PAL_MC_HW_TRACKING, 0, 0, 0);
|
||||
if (status)
|
||||
*status = iprv.v0;
|
||||
return iprv.status;
|
||||
}
|
||||
|
||||
/* Register a platform dependent location with PAL to which it can save
|
||||
* minimal processor state in the event of a machine check or initialization
|
||||
* event.
|
||||
*/
|
||||
static inline s64
|
||||
ia64_pal_mc_register_mem (u64 physical_addr)
|
||||
ia64_pal_mc_register_mem (u64 physical_addr, u64 size, u64 *req_size)
|
||||
{
|
||||
struct ia64_pal_retval iprv;
|
||||
PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
|
||||
PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, size, 0);
|
||||
if (req_size)
|
||||
*req_size = iprv.v0;
|
||||
return iprv.status;
|
||||
}
|
||||
|
||||
|
|
@ -1631,6 +1662,29 @@ ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
|
|||
return iprv.status;
|
||||
}
|
||||
|
||||
typedef union pal_vp_info_u {
|
||||
u64 pvi_val;
|
||||
struct {
|
||||
u64 index: 48, /* virtual feature set info */
|
||||
vmm_id: 16; /* feature set id */
|
||||
} pal_vp_info_s;
|
||||
} pal_vp_info_u_t;
|
||||
|
||||
/*
|
||||
* Returns infomation about virtual processor features
|
||||
*/
|
||||
static inline s64
|
||||
ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id)
|
||||
{
|
||||
struct ia64_pal_retval iprv;
|
||||
PAL_CALL(iprv, PAL_VP_INFO, feature_set, vp_buffer, 0);
|
||||
if (vp_info)
|
||||
*vp_info = iprv.v0;
|
||||
if (vmm_id)
|
||||
*vmm_id = iprv.v1;
|
||||
return iprv.status;
|
||||
}
|
||||
|
||||
typedef union pal_itr_valid_u {
|
||||
u64 piv_val;
|
||||
struct {
|
||||
|
|
|
|||
|
|
@ -371,7 +371,7 @@ pgd_index (unsigned long address)
|
|||
/* The offset in the 1-level directory is given by the 3 region bits
|
||||
(61..63) and the level-1 bits. */
|
||||
static inline pgd_t*
|
||||
pgd_offset (struct mm_struct *mm, unsigned long address)
|
||||
pgd_offset (const struct mm_struct *mm, unsigned long address)
|
||||
{
|
||||
return mm->pgd + pgd_index(address);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -296,6 +296,9 @@ enum {
|
|||
EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
|
||||
#define SAL_PLAT_BUS_ERR_SECT_GUID \
|
||||
EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
|
||||
#define PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID \
|
||||
EFI_GUID(0x6cb0a200, 0x893a, 0x11da, 0x96, 0xd2, 0x0, 0x10, 0x83, 0xff, \
|
||||
0xca, 0x4d)
|
||||
|
||||
#define MAX_CACHE_ERRORS 6
|
||||
#define MAX_TLB_ERRORS 6
|
||||
|
|
@ -879,6 +882,24 @@ extern void ia64_jump_to_sal(struct sal_to_os_boot *);
|
|||
|
||||
extern void ia64_sal_handler_init(void *entry_point, void *gpval);
|
||||
|
||||
#define PALO_MAX_TLB_PURGES 0xFFFF
|
||||
#define PALO_SIG "PALO"
|
||||
|
||||
struct palo_table {
|
||||
u8 signature[4]; /* Should be "PALO" */
|
||||
u32 length;
|
||||
u8 minor_revision;
|
||||
u8 major_revision;
|
||||
u8 checksum;
|
||||
u8 reserved1[5];
|
||||
u16 max_tlb_purges;
|
||||
u8 reserved2[6];
|
||||
};
|
||||
|
||||
#define NPTCG_FROM_PAL 0
|
||||
#define NPTCG_FROM_PALO 1
|
||||
#define NPTCG_FROM_KERNEL_PARAMETER 2
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_IA64_SAL_H */
|
||||
|
|
|
|||
|
|
@ -38,6 +38,9 @@ ia64_get_lid (void)
|
|||
return lid.f.id << 8 | lid.f.eid;
|
||||
}
|
||||
|
||||
extern int smp_call_function_mask(cpumask_t mask, void (*func)(void *),
|
||||
void *info, int wait);
|
||||
|
||||
#define hard_smp_processor_id() ia64_get_lid()
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
|
|
|||
|
|
@ -210,6 +210,13 @@ struct task_struct;
|
|||
extern void ia64_save_extra (struct task_struct *task);
|
||||
extern void ia64_load_extra (struct task_struct *task);
|
||||
|
||||
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
||||
extern void ia64_account_on_switch (struct task_struct *prev, struct task_struct *next);
|
||||
# define IA64_ACCOUNT_ON_SWITCH(p,n) ia64_account_on_switch(p,n)
|
||||
#else
|
||||
# define IA64_ACCOUNT_ON_SWITCH(p,n)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PERFMON
|
||||
DECLARE_PER_CPU(unsigned long, pfm_syst_info);
|
||||
# define PERFMON_IS_SYSWIDE() (__get_cpu_var(pfm_syst_info) & 0x1)
|
||||
|
|
@ -222,6 +229,7 @@ extern void ia64_load_extra (struct task_struct *task);
|
|||
|| IS_IA32_PROCESS(task_pt_regs(t)) || PERFMON_IS_SYSWIDE())
|
||||
|
||||
#define __switch_to(prev,next,last) do { \
|
||||
IA64_ACCOUNT_ON_SWITCH(prev, next); \
|
||||
if (IA64_HAS_EXTRA_STATE(prev)) \
|
||||
ia64_save_extra(prev); \
|
||||
if (IA64_HAS_EXTRA_STATE(next)) \
|
||||
|
|
@ -266,6 +274,10 @@ void cpu_idle_wait(void);
|
|||
|
||||
void default_idle(void);
|
||||
|
||||
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
||||
extern void account_system_vtime(struct task_struct *);
|
||||
#endif
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
|
|
|||
|
|
@ -31,6 +31,12 @@ struct thread_info {
|
|||
mm_segment_t addr_limit; /* user-level address space limit */
|
||||
int preempt_count; /* 0=premptable, <0=BUG; will also serve as bh-counter */
|
||||
struct restart_block restart_block;
|
||||
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
||||
__u64 ac_stamp;
|
||||
__u64 ac_leave;
|
||||
__u64 ac_stime;
|
||||
__u64 ac_utime;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define THREAD_SIZE KERNEL_STACK_SIZE
|
||||
|
|
@ -62,9 +68,17 @@ struct thread_info {
|
|||
#define task_stack_page(tsk) ((void *)(tsk))
|
||||
|
||||
#define __HAVE_THREAD_FUNCTIONS
|
||||
#ifdef CONFIG_VIRT_CPU_ACCOUNTING
|
||||
#define setup_thread_stack(p, org) \
|
||||
*task_thread_info(p) = *task_thread_info(org); \
|
||||
task_thread_info(p)->ac_stime = 0; \
|
||||
task_thread_info(p)->ac_utime = 0; \
|
||||
task_thread_info(p)->task = (p);
|
||||
#else
|
||||
#define setup_thread_stack(p, org) \
|
||||
*task_thread_info(p) = *task_thread_info(org); \
|
||||
task_thread_info(p)->task = (p);
|
||||
#endif
|
||||
#define end_of_stack(p) (unsigned long *)((void *)(p) + IA64_RBS_OFFSET)
|
||||
|
||||
#define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR
|
||||
|
|
|
|||
|
|
@ -64,6 +64,32 @@ struct mmu_gather {
|
|||
struct page *pages[FREE_PTE_NR];
|
||||
};
|
||||
|
||||
struct ia64_tr_entry {
|
||||
u64 ifa;
|
||||
u64 itir;
|
||||
u64 pte;
|
||||
u64 rr;
|
||||
}; /*Record for tr entry!*/
|
||||
|
||||
extern int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size);
|
||||
extern void ia64_ptr_entry(u64 target_mask, int slot);
|
||||
|
||||
extern struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];
|
||||
|
||||
/*
|
||||
region register macros
|
||||
*/
|
||||
#define RR_TO_VE(val) (((val) >> 0) & 0x0000000000000001)
|
||||
#define RR_VE(val) (((val) & 0x0000000000000001) << 0)
|
||||
#define RR_VE_MASK 0x0000000000000001L
|
||||
#define RR_VE_SHIFT 0
|
||||
#define RR_TO_PS(val) (((val) >> 2) & 0x000000000000003f)
|
||||
#define RR_PS(val) (((val) & 0x000000000000003f) << 2)
|
||||
#define RR_PS_MASK 0x00000000000000fcL
|
||||
#define RR_PS_SHIFT 2
|
||||
#define RR_RID_MASK 0x00000000ffffff00L
|
||||
#define RR_TO_RID(val) ((val >> 8) & 0xffffff)
|
||||
|
||||
/* Users of the generic TLB shootdown code must declare this storage space. */
|
||||
DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
|
||||
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
* Now for some TLB flushing routines. This is the kind of stuff that
|
||||
* can be very expensive, so try to avoid them whenever possible.
|
||||
*/
|
||||
extern void setup_ptcg_sem(int max_purges, int from_palo);
|
||||
|
||||
/*
|
||||
* Flush everything (kernel mapping may also have changed due to
|
||||
|
|
|
|||
Loading…
Reference in a new issue