From 478ac0717ca0681cc1342dec15804f38665c0b8d Mon Sep 17 00:00:00 2001
From: Guru Das Srinagesh <gurus@quicinc.com>
Date: Fri, 24 Jul 2020 12:38:53 -0700
Subject: [PATCH] ARM: dts: msm: Add PMX65 PMIC devices

Add SPMI slave device for PMX65, and also a few of its peripherals.

Change-Id: I333140629b18cbea7e7a9c8f34c8b59b118b120b
---
 qcom/pmx65.dtsi | 67 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 qcom/pmx65.dtsi

diff --git a/qcom/pmx65.dtsi b/qcom/pmx65.dtsi
new file mode 100644
index 000000000000..813eed17ef68
--- /dev/null
+++ b/qcom/pmx65.dtsi
@@ -0,0 +1,67 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pmx65@1 {
+		compatible = "qcom,spmi-pmic";
+		reg = <1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmx65_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmx65_pwm: pwms@e800 {
+			compatible = "qcom,pwm-lpg";
+			reg = <0xe800>;
+			reg-names = "lpg-base";
+			#pwm-cells = <2>;
+			qcom,num-lpg-channels = <4>;
+		};
+
+		pmx65_gpios: pinctrl@8800 {
+			compatible = "qcom,pmx65-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
+
+&thermal_zones {
+	pmx65_temp_alarm: pmx65_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pmx65_tz>;
+
+		trips {
+			pmx65_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pmx65_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			pmx65_trip2: trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+};