From 4acf052c6eb57e65d88bb2a93ce61cb862ecef1d Mon Sep 17 00:00:00 2001 From: Srinivas Rao L Date: Fri, 14 Feb 2020 11:56:22 +0530 Subject: [PATCH 1/2] drivers: irqchip: qcom-pdc: Add PDC IRQ chip support for shima Add PDC interrupt controller chip support for shima. Change-Id: I8d92ccba39ac09eede3236780f0509f6a4b117f1 Signed-off-by: Srinivas Rao L --- drivers/irqchip/qcom-pdc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 3f6886e130b6..79b745ec273f 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -538,3 +538,4 @@ fail: IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init); IRQCHIP_DECLARE(pdc_lahaina, "qcom,lahaina-pdc", qcom_pdc_init); +IRQCHIP_DECLARE(pdc_shima, "qcom,shima-pdc", qcom_pdc_init); From 12e3fa438e7eef6e79a8d23ed02b055eabb5474a Mon Sep 17 00:00:00 2001 From: Srinivas Rao L Date: Fri, 21 Feb 2020 16:58:49 +0530 Subject: [PATCH 2/2] pinctrl: qcom: Add GPIO wakeup interrupt map for Shima GPIOs that can be configured as wakeup sources, have their interrupt lines routed to PDC interrupt controller. Add the interrupt map of the GPIO's to its wakeup capable interrupt parent. Change-Id: I6680a6d55f53936ace4daab1f2365de055a89a06 Signed-off-by: Srinivas Rao L --- drivers/pinctrl/qcom/pinctrl-shima.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-shima.c b/drivers/pinctrl/qcom/pinctrl-shima.c index 1dd5562e88cd..e2b74025cec9 100644 --- a/drivers/pinctrl/qcom/pinctrl-shima.c +++ b/drivers/pinctrl/qcom/pinctrl-shima.c @@ -1872,6 +1872,23 @@ static struct pinctrl_qup shima_qup_regs[] = { QUP_I3C(9, QUP_I3C_9_MODE_OFFSET), }; +static const struct msm_gpio_wakeirq_map shima_pdc_map[] = { + { 2, 103 }, { 3, 104 }, { 7, 82 }, { 10, 163 }, { 11, 83 }, + { 15, 146 }, { 16, 155 }, { 17, 154 }, { 19, 121 }, { 23, 84 }, + { 26, 86 }, { 27, 75 }, { 31, 85 }, { 32, 95 }, { 34, 98 }, + { 36, 79 }, { 38, 99 }, { 39, 92 }, { 40, 101 }, { 43, 137 }, + { 45, 133 }, { 46, 96 }, { 47, 93 }, { 48, 127 }, { 50, 108 }, + { 56, 81 }, { 59, 112 }, { 60, 119 }, { 63, 73 }, { 66, 74 }, + { 80, 126 }, { 81, 139 }, { 82, 140 }, { 83, 141 }, { 84, 124 }, + { 87, 138 }, { 88, 122 }, { 89, 113 }, { 90, 114 }, { 91, 115 }, + { 93, 117 }, { 95, 147 }, { 96, 148 }, { 98, 149 }, { 99, 150 }, + { 105, 161 }, { 107, 160 }, { 110, 159 }, { 113, 158 }, { 114, 157 }, + { 116, 106 }, { 117, 105 }, { 118, 116 }, { 119, 123 }, { 130, 145 }, + { 136, 72 }, { 140, 100 }, { 151, 110 }, { 155, 107 }, { 156, 94 }, + { 159, 118 }, { 162, 77 }, { 169, 70 }, { 172, 132 }, { 174, 87 }, + { 177, 89 }, { 179, 120 }, { 180, 129 }, { 183, 90 }, { 185, 136 }, +}; + static const struct msm_pinctrl_soc_data shima_pinctrl = { .pins = shima_pins, .npins = ARRAY_SIZE(shima_pins), @@ -1882,6 +1899,8 @@ static const struct msm_pinctrl_soc_data shima_pinctrl = { .ngpios = 204, .qup_regs = shima_qup_regs, .nqup_regs = ARRAY_SIZE(shima_qup_regs), + .wakeirq_map = shima_pdc_map, + .nwakeirq_map = ARRAY_SIZE(shima_pdc_map), }; static int shima_pinctrl_probe(struct platform_device *pdev)