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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-07 20:33:58 -04:00
iommu: arm-smmu: update access to SMMU TCU testbus registers with scm call
Update access to SMMU TCU testbus and testbus_sel registers using scm. Change-Id: I5a125070977ffa061a8ee94fdbd9f56603c00a82 Signed-off-by: Faiyaz Mohammed <faiyazm@codeaurora.org> [guptap@codeaurora.org: resolved trival merge conflicts] Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
This commit is contained in:
Faiyaz Mohammed
Prakash Gupta
parent
d989e632a5
commit
47b2cb7ab2
3 changed files with 83 additions and 51 deletions
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/kernel.h>
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@ -8,6 +8,7 @@
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#include <linux/device.h>
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#include "arm-smmu.h"
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#include "arm-smmu-debug.h"
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#include <linux/qcom_scm.h>
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u32 arm_smmu_debug_tbu_testbus_select(void __iomem *tbu_base,
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@ -28,33 +29,59 @@ u32 arm_smmu_debug_tbu_testbus_output(void __iomem *tbu_base)
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return readl_relaxed(tbu_base + DEBUG_TESTBUS_TBU);
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}
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u32 arm_smmu_debug_tcu_testbus_select(void __iomem *base,
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u32 arm_smmu_debug_tcu_testbus_select(phys_addr_t phys_addr,
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void __iomem *tcu_base, enum tcu_testbus testbus,
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bool write, u32 val)
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{
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int offset;
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u32 testbus_sel;
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int ret = 0;
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if (testbus == CLK_TESTBUS) {
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base = tcu_base;
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offset = ARM_SMMU_TESTBUS_SEL_HLOS1_NS;
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if (write) {
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writel_relaxed(val, tcu_base + offset);
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/* Make sure tcu select register is written to */
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wmb();
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} else {
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return readl_relaxed(tcu_base + offset);
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}
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} else {
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offset = ARM_SMMU_TESTBUS_SEL;
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}
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if (write) {
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ret = qcom_scm_io_writel((phys_addr + offset), val);
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if (ret)
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pr_err_ratelimited("SCM write of TESTBUS SEL fails: %d\n",
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ret);
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if (write) {
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writel_relaxed(val, base + offset);
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/* Make sure tcu select register is written to */
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wmb();
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} else {
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return readl_relaxed(base + offset);
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/* Make sure tcu select register is written to */
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wmb();
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} else {
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ret = qcom_scm_io_readl(phys_addr + offset,
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&testbus_sel);
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if (ret)
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pr_err_ratelimited("SCM write of TESTBUS SEL fails: %d\n",
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ret);
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else
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return testbus_sel;
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}
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}
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return 0;
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}
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u32 arm_smmu_debug_tcu_testbus_output(void __iomem *base)
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u32 arm_smmu_debug_tcu_testbus_output(phys_addr_t phys_addr)
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{
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return readl_relaxed(base + ARM_SMMU_TESTBUS);
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u32 testbus_output;
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int ret;
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ret = qcom_scm_io_readl(phys_addr + ARM_SMMU_TESTBUS, &testbus_output);
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if (!ret)
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return testbus_output;
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pr_err_ratelimited("SCM write of TESTBUS output fails: %d\n", ret);
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return 0;
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}
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static void arm_smmu_debug_dump_tbu_qns4_testbus(struct device *dev,
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@ -123,7 +150,7 @@ void arm_smmu_debug_dump_tbu_testbus(struct device *dev, void __iomem *tbu_base,
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}
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static void arm_smmu_debug_program_tcu_testbus(struct device *dev,
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void __iomem *base, void __iomem *tcu_base,
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phys_addr_t phys_addr, void __iomem *tcu_base,
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unsigned long mask, int start, int end, int shift,
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bool print)
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{
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@ -131,30 +158,30 @@ static void arm_smmu_debug_program_tcu_testbus(struct device *dev,
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int i;
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for (i = start; i < end; i++) {
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reg = arm_smmu_debug_tcu_testbus_select(base, tcu_base,
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reg = arm_smmu_debug_tcu_testbus_select(phys_addr, tcu_base,
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PTW_AND_CACHE_TESTBUS, READ, 0);
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reg &= mask;
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reg |= i << shift;
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arm_smmu_debug_tcu_testbus_select(base, tcu_base,
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arm_smmu_debug_tcu_testbus_select(phys_addr, tcu_base,
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PTW_AND_CACHE_TESTBUS, WRITE, reg);
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if (print)
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dev_info(dev, "testbus_sel: 0x%lx Index: %d val: 0x%lx\n",
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arm_smmu_debug_tcu_testbus_select(base,
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tcu_base, PTW_AND_CACHE_TESTBUS, READ, 0),
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i, arm_smmu_debug_tcu_testbus_output(base));
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arm_smmu_debug_tcu_testbus_select(phys_addr,
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tcu_base, PTW_AND_CACHE_TESTBUS, READ, 0), i,
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arm_smmu_debug_tcu_testbus_output(phys_addr));
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}
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}
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void arm_smmu_debug_dump_tcu_testbus(struct device *dev, void __iomem *base,
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void __iomem *tcu_base, int tcu_testbus_sel)
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void arm_smmu_debug_dump_tcu_testbus(struct device *dev, phys_addr_t phys_addr,
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void __iomem *tcu_base, int tcu_testbus_sel)
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{
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int i;
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if (tcu_testbus_sel & TCU_CACHE_TESTBUS_SEL) {
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dev_info(dev, "Dumping TCU cache testbus:\n");
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,
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arm_smmu_debug_program_tcu_testbus(dev, phys_addr, tcu_base,
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TCU_CACHE_TESTBUS, 0, 1, 0, false);
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,
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arm_smmu_debug_program_tcu_testbus(dev, phys_addr, tcu_base,
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~TCU_PTW_QUEUE_MASK, 0,
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TCU_CACHE_LOOKUP_QUEUE_SIZE,
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2, true);
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@ -162,32 +189,37 @@ void arm_smmu_debug_dump_tcu_testbus(struct device *dev, void __iomem *base,
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if (tcu_testbus_sel & TCU_PTW_TESTBUS_SEL) {
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dev_info(dev, "Dumping TCU PTW test bus:\n");
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base, 1,
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arm_smmu_debug_program_tcu_testbus(dev, phys_addr, tcu_base, 1,
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TCU_PTW_TESTBUS, TCU_PTW_TESTBUS + 1, 0, false);
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,
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arm_smmu_debug_program_tcu_testbus(dev, phys_addr, tcu_base,
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~TCU_PTW_INTERNAL_STATES_MASK,
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0, TCU_PTW_INTERNAL_STATES,
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2, true);
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for (i = TCU_PTW_QUEUE_START;
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i < TCU_PTW_QUEUE_START + TCU_PTW_QUEUE_SIZE; ++i) {
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,
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~TCU_PTW_QUEUE_MASK, i, i + 1, 2, true);
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arm_smmu_debug_program_tcu_testbus(dev, base, tcu_base,
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~TCU_PTW_TESTBUS_SEL2_MASK, TCU_PTW_TESTBUS_SEL2,
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TCU_PTW_TESTBUS_SEL2 + 1, 0, false);
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arm_smmu_debug_program_tcu_testbus(dev, phys_addr,
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tcu_base,
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~TCU_PTW_QUEUE_MASK,
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i, i + 1, 2, true);
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arm_smmu_debug_program_tcu_testbus(dev, phys_addr,
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tcu_base,
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~TCU_PTW_TESTBUS_SEL2_MASK,
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TCU_PTW_TESTBUS_SEL2,
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TCU_PTW_TESTBUS_SEL2 + 1, 0,
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false);
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dev_info(dev, "testbus_sel: 0x%lx Index: %d val: 0x%lx\n",
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arm_smmu_debug_tcu_testbus_select(base,
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tcu_base, PTW_AND_CACHE_TESTBUS, READ, 0),
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i, arm_smmu_debug_tcu_testbus_output(base));
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arm_smmu_debug_tcu_testbus_select(phys_addr,
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tcu_base, PTW_AND_CACHE_TESTBUS, READ, 0), i,
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arm_smmu_debug_tcu_testbus_output(phys_addr));
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}
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}
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/* program ARM_SMMU_TESTBUS_SEL_HLOS1_NS to select TCU clk testbus*/
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arm_smmu_debug_tcu_testbus_select(base, tcu_base,
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arm_smmu_debug_tcu_testbus_select(phys_addr, tcu_base,
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CLK_TESTBUS, WRITE, TCU_CLK_TESTBUS_SEL);
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dev_info(dev, "Programming Tcu clk gate controller: testbus_sel: 0x%lx\n",
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arm_smmu_debug_tcu_testbus_select(base, tcu_base,
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arm_smmu_debug_tcu_testbus_select(phys_addr, tcu_base,
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CLK_TESTBUS, READ, 0));
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}
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#define ARM_SMMU_TESTBUS_SEL 0x25E4
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@ -58,13 +58,13 @@ enum testbus_ops {
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u32 arm_smmu_debug_tbu_testbus_select(void __iomem *tbu_base,
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bool write, u32 val);
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u32 arm_smmu_debug_tbu_testbus_output(void __iomem *tbu_base);
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u32 arm_smmu_debug_tcu_testbus_select(void __iomem *base,
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u32 arm_smmu_debug_tcu_testbus_select(phys_addr_t phys_addr,
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void __iomem *tcu_base, enum tcu_testbus testbus,
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bool write, u32 val);
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u32 arm_smmu_debug_tcu_testbus_output(void __iomem *base);
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u32 arm_smmu_debug_tcu_testbus_output(phys_addr_t phys_addr);
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void arm_smmu_debug_dump_tbu_testbus(struct device *dev, void __iomem *tbu_base,
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int tbu_testbus_sel);
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void arm_smmu_debug_dump_tcu_testbus(struct device *dev, void __iomem *base,
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void arm_smmu_debug_dump_tcu_testbus(struct device *dev, phys_addr_t phys_addr,
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void __iomem *tcu_base, int tcu_testbus_sel);
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#else
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@ -77,12 +77,12 @@ static inline u32 arm_smmu_debug_tbu_testbus_output(void __iomem *tbu_base)
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{
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return 0;
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}
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u32 arm_smmu_debug_tcu_testbus_select(void __iomem *base,
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void __iomem *tcu_base, enum tcu_testbus testbus,
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u32 arm_smmu_debug_tcu_testbus_select(phys_addr_t phys_addr,
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void __iomem *tcu_base, enum tcu_testbus testbus,
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bool write, u32 val)
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{
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}
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static inline u32 arm_smmu_debug_tcu_testbus_output(void __iomem *base)
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static inline u32 arm_smmu_debug_tcu_testbus_output(phys_addr_t phys_addr)
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{
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return 0;
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}
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@ -91,7 +91,7 @@ static inline void arm_smmu_debug_dump_tbu_testbus(struct device *dev,
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{
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}
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static inline void arm_smmu_debug_dump_tcu_testbus(struct device *dev,
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void __iomem *base, void __iomem *tcu_base,
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phys_addr_t phys_addr, void __iomem *tcu_base,
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int tcu_testbus_sel)
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{
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}
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@ -462,23 +462,23 @@ static ssize_t arm_smmu_debug_testbus_read(struct file *file,
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struct arm_smmu_device *smmu = file->private_data;
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struct qsmmuv500_archdata *data = to_qsmmuv500_archdata(smmu);
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void __iomem *base = arm_smmu_page(smmu, ARM_SMMU_GR0);
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phys_addr_t phys_addr = smmu->phys_addr;
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void __iomem *tcu_base = data->tcu_base;
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arm_smmu_power_on(smmu->pwr);
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if (ops == TESTBUS_SELECT) {
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scnprintf(buf, buf_len, "TCU clk testbus sel: 0x%0x\n",
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arm_smmu_debug_tcu_testbus_select(base,
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arm_smmu_debug_tcu_testbus_select(phys_addr,
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tcu_base, CLK_TESTBUS, READ, 0));
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scnprintf(buf + strlen(buf), buf_len - strlen(buf),
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"TCU testbus sel : 0x%0x\n",
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arm_smmu_debug_tcu_testbus_select(base,
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arm_smmu_debug_tcu_testbus_select(phys_addr,
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tcu_base, PTW_AND_CACHE_TESTBUS,
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READ, 0));
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} else {
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scnprintf(buf, buf_len, "0x%0x\n",
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arm_smmu_debug_tcu_testbus_output(base));
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arm_smmu_debug_tcu_testbus_output(phys_addr));
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}
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arm_smmu_power_off(smmu, smmu->pwr);
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@ -501,7 +501,7 @@ static ssize_t arm_smmu_debug_tcu_testbus_sel_write(struct file *file,
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struct arm_smmu_device *smmu = file->private_data;
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struct qsmmuv500_archdata *data = to_qsmmuv500_archdata(smmu);
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void __iomem *tcu_base = data->tcu_base;
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void __iomem *base = arm_smmu_page(smmu, ARM_SMMU_GR0);
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phys_addr_t phys_addr = smmu->phys_addr;
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char *comma;
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char buf[100];
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u64 sel, val;
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@ -537,10 +537,10 @@ static ssize_t arm_smmu_debug_tcu_testbus_sel_write(struct file *file,
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arm_smmu_power_on(smmu->pwr);
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if (sel == 1)
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arm_smmu_debug_tcu_testbus_select(base,
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arm_smmu_debug_tcu_testbus_select(phys_addr,
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tcu_base, CLK_TESTBUS, WRITE, val);
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else if (sel == 2)
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arm_smmu_debug_tcu_testbus_select(base,
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arm_smmu_debug_tcu_testbus_select(phys_addr,
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tcu_base, PTW_AND_CACHE_TESTBUS, WRITE, val);
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arm_smmu_power_off(smmu, smmu->pwr);
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@ -743,7 +743,7 @@ static void arm_smmu_testbus_dump(struct arm_smmu_device *smmu, u16 sid)
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tbu_testbus_sel);
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else
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arm_smmu_debug_dump_tcu_testbus(smmu->dev,
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smmu->base,
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smmu->phys_addr,
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data->tcu_base,
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tcu_testbus_sel);
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spin_unlock(&testbus_lock);
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