mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
mfd: Align ab8500 with the abx500 interface
This patch makes the ab8500 mixed signal chip expose the same interface for register access as the ab3100, ab3550 and ab5500 chip. The ab8500_read() and ab8500_write() is removed and replaced with abx500_get_register_interruptible() and abx500_set_register_interruptible(). Signed-off-by: Mattias Wallin <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Mark Brown <[email protected]> Signed-off-by: Samuel Ortiz <[email protected]>
This commit is contained in:
Mattias Wallin
Samuel Ortiz
parent
f4ebcab360
commit
47c1697508
6 changed files with 296 additions and 209 deletions
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@ -434,7 +434,7 @@ config PCF50633_GPIO
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config ABX500_CORE
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bool "ST-Ericsson ABX500 Mixed Signal Circuit register functions"
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default y if ARCH_U300
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default y if ARCH_U300 || ARCH_U8500
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help
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Say yes here if you have the ABX500 Mixed Signal IC family
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chips. This core driver expose register access functions.
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@ -475,7 +475,7 @@ config EZX_PCAP
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config AB8500_CORE
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bool "ST-Ericsson AB8500 Mixed Signal Power Management chip"
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depends on SPI=y && GENERIC_HARDIRQS
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depends on SPI=y && GENERIC_HARDIRQS && ABX500_CORE
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select MFD_CORE
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help
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Select this option to enable access to AB8500 power management
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@ -4,6 +4,7 @@
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* License Terms: GNU General Public License v2
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* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
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* Author: Rabin Vincent <rabin.vincent@stericsson.com>
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* Changes: Mattias Wallin <mattias.wallin@stericsson.com>
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*/
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#include <linux/kernel.h>
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@ -15,6 +16,7 @@
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/abx500.h>
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#include <linux/mfd/ab8500.h>
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#include <linux/regulator/ab8500.h>
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@ -22,71 +24,71 @@
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* Interrupt register offsets
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* Bank : 0x0E
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*/
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#define AB8500_IT_SOURCE1_REG 0x0E00
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#define AB8500_IT_SOURCE2_REG 0x0E01
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#define AB8500_IT_SOURCE3_REG 0x0E02
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#define AB8500_IT_SOURCE4_REG 0x0E03
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#define AB8500_IT_SOURCE5_REG 0x0E04
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#define AB8500_IT_SOURCE6_REG 0x0E05
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#define AB8500_IT_SOURCE7_REG 0x0E06
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#define AB8500_IT_SOURCE8_REG 0x0E07
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#define AB8500_IT_SOURCE19_REG 0x0E12
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#define AB8500_IT_SOURCE20_REG 0x0E13
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#define AB8500_IT_SOURCE21_REG 0x0E14
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#define AB8500_IT_SOURCE22_REG 0x0E15
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#define AB8500_IT_SOURCE23_REG 0x0E16
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#define AB8500_IT_SOURCE24_REG 0x0E17
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#define AB8500_IT_SOURCE1_REG 0x00
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#define AB8500_IT_SOURCE2_REG 0x01
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#define AB8500_IT_SOURCE3_REG 0x02
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#define AB8500_IT_SOURCE4_REG 0x03
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#define AB8500_IT_SOURCE5_REG 0x04
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#define AB8500_IT_SOURCE6_REG 0x05
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#define AB8500_IT_SOURCE7_REG 0x06
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#define AB8500_IT_SOURCE8_REG 0x07
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#define AB8500_IT_SOURCE19_REG 0x12
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#define AB8500_IT_SOURCE20_REG 0x13
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#define AB8500_IT_SOURCE21_REG 0x14
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#define AB8500_IT_SOURCE22_REG 0x15
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#define AB8500_IT_SOURCE23_REG 0x16
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#define AB8500_IT_SOURCE24_REG 0x17
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/*
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* latch registers
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*/
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#define AB8500_IT_LATCH1_REG 0x0E20
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#define AB8500_IT_LATCH2_REG 0x0E21
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#define AB8500_IT_LATCH3_REG 0x0E22
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#define AB8500_IT_LATCH4_REG 0x0E23
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#define AB8500_IT_LATCH5_REG 0x0E24
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#define AB8500_IT_LATCH6_REG 0x0E25
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#define AB8500_IT_LATCH7_REG 0x0E26
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#define AB8500_IT_LATCH8_REG 0x0E27
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#define AB8500_IT_LATCH9_REG 0x0E28
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#define AB8500_IT_LATCH10_REG 0x0E29
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#define AB8500_IT_LATCH19_REG 0x0E32
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#define AB8500_IT_LATCH20_REG 0x0E33
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#define AB8500_IT_LATCH21_REG 0x0E34
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#define AB8500_IT_LATCH22_REG 0x0E35
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#define AB8500_IT_LATCH23_REG 0x0E36
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#define AB8500_IT_LATCH24_REG 0x0E37
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#define AB8500_IT_LATCH1_REG 0x20
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#define AB8500_IT_LATCH2_REG 0x21
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#define AB8500_IT_LATCH3_REG 0x22
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#define AB8500_IT_LATCH4_REG 0x23
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#define AB8500_IT_LATCH5_REG 0x24
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#define AB8500_IT_LATCH6_REG 0x25
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#define AB8500_IT_LATCH7_REG 0x26
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#define AB8500_IT_LATCH8_REG 0x27
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#define AB8500_IT_LATCH9_REG 0x28
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#define AB8500_IT_LATCH10_REG 0x29
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#define AB8500_IT_LATCH19_REG 0x32
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#define AB8500_IT_LATCH20_REG 0x33
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#define AB8500_IT_LATCH21_REG 0x34
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#define AB8500_IT_LATCH22_REG 0x35
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#define AB8500_IT_LATCH23_REG 0x36
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#define AB8500_IT_LATCH24_REG 0x37
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/*
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* mask registers
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*/
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#define AB8500_IT_MASK1_REG 0x0E40
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#define AB8500_IT_MASK2_REG 0x0E41
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#define AB8500_IT_MASK3_REG 0x0E42
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#define AB8500_IT_MASK4_REG 0x0E43
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#define AB8500_IT_MASK5_REG 0x0E44
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#define AB8500_IT_MASK6_REG 0x0E45
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#define AB8500_IT_MASK7_REG 0x0E46
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#define AB8500_IT_MASK8_REG 0x0E47
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#define AB8500_IT_MASK9_REG 0x0E48
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#define AB8500_IT_MASK10_REG 0x0E49
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#define AB8500_IT_MASK11_REG 0x0E4A
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#define AB8500_IT_MASK12_REG 0x0E4B
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#define AB8500_IT_MASK13_REG 0x0E4C
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#define AB8500_IT_MASK14_REG 0x0E4D
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#define AB8500_IT_MASK15_REG 0x0E4E
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#define AB8500_IT_MASK16_REG 0x0E4F
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#define AB8500_IT_MASK17_REG 0x0E50
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#define AB8500_IT_MASK18_REG 0x0E51
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#define AB8500_IT_MASK19_REG 0x0E52
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#define AB8500_IT_MASK20_REG 0x0E53
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#define AB8500_IT_MASK21_REG 0x0E54
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#define AB8500_IT_MASK22_REG 0x0E55
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#define AB8500_IT_MASK23_REG 0x0E56
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#define AB8500_IT_MASK24_REG 0x0E57
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#define AB8500_IT_MASK1_REG 0x40
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#define AB8500_IT_MASK2_REG 0x41
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#define AB8500_IT_MASK3_REG 0x42
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#define AB8500_IT_MASK4_REG 0x43
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#define AB8500_IT_MASK5_REG 0x44
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#define AB8500_IT_MASK6_REG 0x45
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#define AB8500_IT_MASK7_REG 0x46
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#define AB8500_IT_MASK8_REG 0x47
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#define AB8500_IT_MASK9_REG 0x48
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#define AB8500_IT_MASK10_REG 0x49
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#define AB8500_IT_MASK11_REG 0x4A
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#define AB8500_IT_MASK12_REG 0x4B
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#define AB8500_IT_MASK13_REG 0x4C
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#define AB8500_IT_MASK14_REG 0x4D
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#define AB8500_IT_MASK15_REG 0x4E
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#define AB8500_IT_MASK16_REG 0x4F
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#define AB8500_IT_MASK17_REG 0x50
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#define AB8500_IT_MASK18_REG 0x51
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#define AB8500_IT_MASK19_REG 0x52
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#define AB8500_IT_MASK20_REG 0x53
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#define AB8500_IT_MASK21_REG 0x54
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#define AB8500_IT_MASK22_REG 0x55
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#define AB8500_IT_MASK23_REG 0x56
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#define AB8500_IT_MASK24_REG 0x57
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#define AB8500_REV_REG 0x1080
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#define AB8500_REV_REG 0x80
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/*
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* Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
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@ -99,96 +101,132 @@ static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
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0, 1, 2, 3, 4, 6, 7, 8, 9, 18, 19, 20, 21,
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};
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static int __ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data)
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static int ab8500_get_chip_id(struct device *dev)
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{
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struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
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return (int)ab8500->chip_id;
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}
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static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
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u8 reg, u8 data)
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{
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int ret;
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/*
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* Put the u8 bank and u8 register together into a an u16.
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* The bank on higher 8 bits and register in lower 8 bits.
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* */
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u16 addr = ((u16)bank) << 8 | reg;
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dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
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ret = mutex_lock_interruptible(&ab8500->lock);
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if (ret)
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return ret;
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ret = ab8500->write(ab8500, addr, data);
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if (ret < 0)
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dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
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addr, ret);
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mutex_unlock(&ab8500->lock);
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return ret;
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}
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static int ab8500_set_register(struct device *dev, u8 bank,
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u8 reg, u8 value)
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{
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struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
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return set_register_interruptible(ab8500, bank, reg, value);
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}
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static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
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u8 reg, u8 *value)
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{
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int ret;
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/* put the u8 bank and u8 reg together into a an u16.
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* bank on higher 8 bits and reg in lower */
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u16 addr = ((u16)bank) << 8 | reg;
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ret = mutex_lock_interruptible(&ab8500->lock);
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if (ret)
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return ret;
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ret = ab8500->read(ab8500, addr);
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if (ret < 0)
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dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
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addr, ret);
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else
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*value = ret;
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mutex_unlock(&ab8500->lock);
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dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
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return ret;
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}
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static int ab8500_get_register(struct device *dev, u8 bank,
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u8 reg, u8 *value)
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{
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struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
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return get_register_interruptible(ab8500, bank, reg, value);
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}
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static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
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u8 reg, u8 bitmask, u8 bitvalues)
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{
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int ret;
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u8 data;
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/* put the u8 bank and u8 reg together into a an u16.
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* bank on higher 8 bits and reg in lower */
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u16 addr = ((u16)bank) << 8 | reg;
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ret = mutex_lock_interruptible(&ab8500->lock);
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if (ret)
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return ret;
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ret = ab8500->read(ab8500, addr);
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if (ret < 0) {
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dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
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addr, ret);
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goto out;
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}
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data = (u8)ret;
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data = (~bitmask & data) | (bitmask & bitvalues);
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ret = ab8500->write(ab8500, addr, data);
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if (ret < 0)
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dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
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addr, ret);
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return ret;
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}
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/**
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* ab8500_write() - write an AB8500 register
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* @ab8500: device to write to
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* @addr: address of the register
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* @data: value to write
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*/
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int ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data)
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{
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int ret;
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mutex_lock(&ab8500->lock);
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ret = __ab8500_write(ab8500, addr, data);
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mutex_unlock(&ab8500->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ab8500_write);
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static int __ab8500_read(struct ab8500 *ab8500, u16 addr)
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{
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int ret;
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ret = ab8500->read(ab8500, addr);
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if (ret < 0)
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dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
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addr, ret);
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dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
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return ret;
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}
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/**
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* ab8500_read() - read an AB8500 register
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* @ab8500: device to read from
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* @addr: address of the register
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*/
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int ab8500_read(struct ab8500 *ab8500, u16 addr)
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{
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int ret;
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mutex_lock(&ab8500->lock);
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ret = __ab8500_read(ab8500, addr);
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mutex_unlock(&ab8500->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ab8500_read);
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/**
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* ab8500_set_bits() - set a bitfield in an AB8500 register
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* @ab8500: device to read from
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* @addr: address of the register
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* @mask: mask of the bitfield to modify
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* @data: value to set to the bitfield
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*/
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int ab8500_set_bits(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data)
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{
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int ret;
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mutex_lock(&ab8500->lock);
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ret = __ab8500_read(ab8500, addr);
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if (ret < 0)
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goto out;
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ret &= ~mask;
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ret |= data;
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ret = __ab8500_write(ab8500, addr, ret);
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dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr, data);
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out:
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mutex_unlock(&ab8500->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ab8500_set_bits);
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static int ab8500_mask_and_set_register(struct device *dev,
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u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
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{
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struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
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return mask_and_set_register_interruptible(ab8500, bank, reg,
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bitmask, bitvalues);
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}
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static struct abx500_ops ab8500_ops = {
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.get_chip_id = ab8500_get_chip_id,
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.get_register = ab8500_get_register,
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.set_register = ab8500_set_register,
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.get_register_page = NULL,
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.set_register_page = NULL,
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.mask_and_set_register = ab8500_mask_and_set_register,
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.event_registers_startup_state_get = NULL,
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.startup_irq_enabled = NULL,
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};
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static void ab8500_irq_lock(unsigned int irq)
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{
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@ -213,7 +251,7 @@ static void ab8500_irq_sync_unlock(unsigned int irq)
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ab8500->oldmask[i] = new;
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reg = AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i];
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ab8500_write(ab8500, reg, new);
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set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
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}
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mutex_unlock(&ab8500->irq_lock);
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@ -257,9 +295,11 @@ static irqreturn_t ab8500_irq(int irq, void *dev)
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for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
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int regoffset = ab8500_irq_regoffset[i];
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int status;
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u8 value;
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status = ab8500_read(ab8500, AB8500_IT_LATCH1_REG + regoffset);
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if (status <= 0)
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status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
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AB8500_IT_LATCH1_REG + regoffset, &value);
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if (status < 0 || value == 0)
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continue;
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do {
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@ -267,8 +307,8 @@ static irqreturn_t ab8500_irq(int irq, void *dev)
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int line = i * 8 + bit;
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handle_nested_irq(ab8500->irq_base + line);
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status &= ~(1 << bit);
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} while (status);
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value &= ~(1 << bit);
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} while (value);
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}
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return IRQ_HANDLED;
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@ -381,6 +421,7 @@ int __devinit ab8500_init(struct ab8500 *ab8500)
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struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev);
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int ret;
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int i;
|
||||
u8 value;
|
||||
|
||||
if (plat)
|
||||
ab8500->irq_base = plat->irq_base;
|
||||
|
|
@ -388,7 +429,8 @@ int __devinit ab8500_init(struct ab8500 *ab8500)
|
|||
mutex_init(&ab8500->lock);
|
||||
mutex_init(&ab8500->irq_lock);
|
||||
|
||||
ret = ab8500_read(ab8500, AB8500_REV_REG);
|
||||
ret = get_register_interruptible(ab8500, AB8500_MISC,
|
||||
AB8500_REV_REG, &value);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
@ -397,28 +439,37 @@ int __devinit ab8500_init(struct ab8500 *ab8500)
|
|||
* 0x10 - Cut 1.0
|
||||
* 0x11 - Cut 1.1
|
||||
*/
|
||||
if (ret == 0x0 || ret == 0x10 || ret == 0x11) {
|
||||
ab8500->revision = ret;
|
||||
dev_info(ab8500->dev, "detected chip, revision: %#x\n", ret);
|
||||
if (value == 0x0 || value == 0x10 || value == 0x11) {
|
||||
ab8500->revision = value;
|
||||
dev_info(ab8500->dev, "detected chip, revision: %#x\n", value);
|
||||
} else {
|
||||
dev_err(ab8500->dev, "unknown chip, revision: %#x\n", ret);
|
||||
dev_err(ab8500->dev, "unknown chip, revision: %#x\n", value);
|
||||
return -EINVAL;
|
||||
}
|
||||
ab8500->chip_id = value;
|
||||
|
||||
if (plat && plat->init)
|
||||
plat->init(ab8500);
|
||||
|
||||
/* Clear and mask all interrupts */
|
||||
for (i = 0; i < 10; i++) {
|
||||
ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i);
|
||||
ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff);
|
||||
get_register_interruptible(ab8500, AB8500_INTERRUPT,
|
||||
AB8500_IT_LATCH1_REG + i, &value);
|
||||
set_register_interruptible(ab8500, AB8500_INTERRUPT,
|
||||
AB8500_IT_MASK1_REG + i, 0xff);
|
||||
}
|
||||
|
||||
for (i = 18; i < 24; i++) {
|
||||
ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i);
|
||||
ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff);
|
||||
get_register_interruptible(ab8500, AB8500_INTERRUPT,
|
||||
AB8500_IT_LATCH1_REG + i, &value);
|
||||
set_register_interruptible(ab8500, AB8500_INTERRUPT,
|
||||
AB8500_IT_MASK1_REG + i, 0xff);
|
||||
}
|
||||
|
||||
ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < AB8500_NUM_IRQ_REGS; i++)
|
||||
ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue