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irqchip: qcom-pdc: Add IPC logging support

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Add IPC logging support for debugging PDC interrupts.

Change-Id: I541acccc44cdc617a72d44ac8b3528bbc05b2e69
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
This commit is contained in:
Lina Iyer 2019-05-31 09:22:08 -07:00 • committed by Maulik Shah
commit 47e18613bc
1 changed files with 24 additions and 0 deletions
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24
drivers/irqchip/qcom-pdc.c
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@ -11,6 +11,7 @@
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
@ -20,8 +21,10 @@
#include <linux/types.h>
#include <linux/qcom_scm.h>
#include <linux/ipc_logging.h>
#define PDC_MAX_IRQS 168
#define PDC_IPC_LOG_SZ 2
#define PDC_MAX_GPIO_IRQS 256
#define CLEAR_INTR(reg, intr) (reg & ~(1 << intr))
@ -50,6 +53,7 @@ static void __iomem *pdc_base;
static struct pdc_pin_region *pdc_region;
static int pdc_region_cnt;
static struct spi_cfg_regs *spi_cfg;
static void *pdc_ipc_log;
static void pdc_reg_write(int reg, u32 i, u32 val)
{
@ -94,6 +98,7 @@ static void pdc_enable_intr(struct irq_data *d, bool on)
enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
ipc_log_string(pdc_ipc_log, "PIN=%d enable=%d", d->hwirq, on);
raw_spin_unlock(&pdc_lock);
}
@ -120,6 +125,7 @@ static void qcom_pdc_gic_mask(struct irq_data *d)
if (d->hwirq == GPIO_NO_WAKE_IRQ)
return;
ipc_log_string(pdc_ipc_log, "PIN=%d mask", d->hwirq);
irq_chip_mask_parent(d);
}
@ -128,6 +134,7 @@ static void qcom_pdc_gic_unmask(struct irq_data *d)
if (d->hwirq == GPIO_NO_WAKE_IRQ)
return;
ipc_log_string(pdc_ipc_log, "PIN=%d unmask", d->hwirq);
irq_chip_unmask_parent(d);
}
@ -177,6 +184,9 @@ static int spi_configure_type(irq_hw_number_t hwirq, unsigned int type)
if (type & IRQ_TYPE_LEVEL_MASK)
val |= mask;
__spi_pin_write(pin, val);
ipc_log_string(pdc_ipc_log,
"SPI config: GIC-SPI=%d (reg=%d,bit=%d) val=%d",
spi, pin, spi % 32, type & IRQ_TYPE_LEVEL_MASK);
raw_spin_unlock_irqrestore(&pdc_lock, flags);
return 0;
@ -251,6 +261,8 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
}
pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type);
ipc_log_string(pdc_ipc_log, "Set type: PIN=%d pdc_type=%d gic_type=%d",
pin_out, pdc_type, type);
/* Additionally, configure (only) the GPIO in the f/w */
if (irq_domain_qcom_handle_wakeup(d->domain)) {
@ -344,6 +356,8 @@ static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
parent_fwspec.param[1] = parent_hwirq;
parent_fwspec.param[2] = type;
ipc_log_string(pdc_ipc_log, "Alloc: PIN=%d GIC-SPI=%d",
hwirq, parent_hwirq);
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
&parent_fwspec);
}
@ -391,6 +405,8 @@ static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
parent_fwspec.param[1] = parent_hwirq;
parent_fwspec.param[2] = type;
ipc_log_string(pdc_ipc_log, "GPIO alloc: PIN=%d GIC-SPI=%d",
hwirq, parent_hwirq);
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
&parent_fwspec);
}
@ -444,6 +460,14 @@ static int pdc_setup_pin_mapping(struct device_node *np)
return 0;
}
static int __init qcom_pdc_early_init(void)
{
pdc_ipc_log = ipc_log_context_create(PDC_IPC_LOG_SZ, "pdc", 0);
return 0;
}
module_init(qcom_pdc_early_init);
static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
{
struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;