Merge "defconfig: arm64: Enable msm_show_resume_irq for Lahaina"

arch/arm64/configs/vendor/lahaina_QGKI.config

@@ -20,6 +20,7 @@ CONFIG_REGMAP_QTI_DEBUG=y
 CONFIG_IPC_LOGGING=y
 CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_QCOM_SHOW_RESUME_IRQ=y
 CONFIG_QCOM_SOC_SLEEP_STATS=y
 CONFIG_QCOM_RUN_QUEUE_STATS=y
 CONFIG_QTI_RPM_STATS_LOG=y

drivers/base/power/power.h

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 #include <linux/pm_qos.h>
+#include <linux/msm_show_resume_irq.h>
 
 static inline void device_pm_init_common(struct device *dev)
 {
@@ -99,12 +100,6 @@ extern int pm_async_enabled;
 /* drivers/base/power/main.c */
 extern struct list_head dpm_list;	/* The active device list */
 
-#ifdef CONFIG_QCOM_SHOW_RESUME_IRQ
-extern int msm_show_resume_irq_mask;
-#else
-#define msm_show_resume_irq_mask 0
-#endif
-
 static inline struct device *to_device(struct list_head *entry)
 {
 	return container_of(entry, struct device, power.entry);

drivers/irqchip/irq-gic-common.h

@@ -10,6 +10,8 @@
 #include <linux/irqdomain.h>
 #include <linux/irqchip/arm-gic-common.h>
 
+#include <linux/msm_show_resume_irq.h>
+
 struct gic_quirk {
 	const char *desc;
 	const char *compatible;
@@ -18,12 +20,6 @@ struct gic_quirk {
 	u32 mask;
 };
 
-#ifdef CONFIG_QCOM_SHOW_RESUME_IRQ
-extern int msm_show_resume_irq_mask;
-#else
-#define msm_show_resume_irq_mask 0
-#endif
-
 int gic_configure_irq(unsigned int irq, unsigned int type,
                        void __iomem *base, void (*sync_access)(void));
 void gic_dist_config(void __iomem *base, int gic_irqs,

include/linux/msm_show_resume_irq.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __MSM_SHOW_RESUME_IRQ_H
+#define __MSM_SHOW_RESUME_IRQ_H
+
+#ifdef CONFIG_QCOM_SHOW_RESUME_IRQ
+extern int msm_show_resume_irq_mask;
+#else
+#define msm_show_resume_irq_mask 0
+#endif
+
+#endif
+
+