diff --git a/hif/src/adrastea_reg_def.h b/hif/src/adrastea_reg_def.h index 1e88b0581cc5..58ac87346368 100644 --- a/hif/src/adrastea_reg_def.h +++ b/hif/src/adrastea_reg_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, 2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2016, 2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2825,6 +2825,111 @@ struct ce_reg_def genoa_ce_targetdef = { MISSING_FOR_ADRASTEA, }; +#ifdef QCN7605_PCIE_SHADOW_REG_SUPPORT + +#define PCIE_SHADOW_REG_VALUE_0 0x2F024 +#define PCIE_SHADOW_REG_VALUE_1 0x2F028 +#define PCIE_SHADOW_REG_VALUE_2 0x2F02C +#define PCIE_SHADOW_REG_VALUE_3 0x2F030 +#define PCIE_SHADOW_REG_VALUE_4 0x2F034 +#define PCIE_SHADOW_REG_VALUE_5 0x2F038 +#define PCIE_SHADOW_REG_VALUE_6 0x2F03C +#define PCIE_SHADOW_REG_VALUE_7 0x2F040 +#define PCIE_SHADOW_REG_VALUE_8 0x2F044 +#define PCIE_SHADOW_REG_VALUE_9 0x2F048 +#define PCIE_SHADOW_REG_VALUE_10 0x2F04C +#define PCIE_SHADOW_REG_VALUE_11 0x2F050 +#define PCIE_SHADOW_REG_VALUE_12 0x2F054 +#define PCIE_SHADOW_REG_VALUE_13 0x2F058 +#define PCIE_SHADOW_REG_VALUE_14 0x2F05C +#define PCIE_SHADOW_REG_VALUE_15 0x2F060 +#define PCIE_SHADOW_REG_VALUE_16 0x2F064 +#define PCIE_SHADOW_REG_VALUE_17 0x2F068 +#define PCIE_SHADOW_REG_VALUE_18 0x2F06C +#define PCIE_SHADOW_REG_VALUE_19 0x2F070 +#define PCIE_SHADOW_REG_VALUE_20 0x2F074 +#define PCIE_SHADOW_REG_VALUE_21 0x2F078 +#define PCIE_SHADOW_REG_VALUE_22 0x2F07C +#define PCIE_SHADOW_REG_VALUE_23 0x2F080 + +#define PCIE_SHADOW_REG_INTER_ADDR_0 0x21000 +#define PCIE_SHADOW_REG_INTER_ADDR_1 0x21004 +#define PCIE_SHADOW_REG_INTER_ADDR_2 0x21008 +#define PCIE_SHADOW_REG_INTER_ADDR_3 0x2100C +#define PCIE_SHADOW_REG_INTER_ADDR_4 0x21010 +#define PCIE_SHADOW_REG_INTER_ADDR_5 0x21014 +#define PCIE_SHADOW_REG_INTER_ADDR_6 0x21018 +#define PCIE_SHADOW_REG_INTER_ADDR_7 0x2101C +#define PCIE_SHADOW_REG_INTER_ADDR_8 0x21020 +#define PCIE_SHADOW_REG_INTER_ADDR_9 0x21024 +#define PCIE_SHADOW_REG_INTER_ADDR_10 0x21028 +#define PCIE_SHADOW_REG_INTER_ADDR_11 0x2102C +#define PCIE_SHADOW_REG_INTER_ADDR_12 0x21030 +#define PCIE_SHADOW_REG_INTER_ADDR_13 0x21034 +#define PCIE_SHADOW_REG_INTER_ADDR_14 0x21038 +#define PCIE_SHADOW_REG_INTER_ADDR_15 0x2103C +#define PCIE_SHADOW_REG_INTER_ADDR_16 0x21040 +#define PCIE_SHADOW_REG_INTER_ADDR_17 0x21044 +#define PCIE_SHADOW_REG_INTER_ADDR_18 0x21048 +#define PCIE_SHADOW_REG_INTER_ADDR_19 0x2104C +#define PCIE_SHADOW_REG_INTER_ADDR_20 0x21050 +#define PCIE_SHADOW_REG_INTER_ADDR_21 0x21054 +#define PCIE_SHADOW_REG_INTER_ADDR_22 0x21058 +#define PCIE_SHADOW_REG_INTER_ADDR_23 0x2105C + +struct host_shadow_regs_s genoa_host_shadow_regs = { + .d_A_LOCAL_SHADOW_REG_VALUE_0 = PCIE_SHADOW_REG_VALUE_0, + .d_A_LOCAL_SHADOW_REG_VALUE_1 = PCIE_SHADOW_REG_VALUE_1, + .d_A_LOCAL_SHADOW_REG_VALUE_2 = PCIE_SHADOW_REG_VALUE_2, + .d_A_LOCAL_SHADOW_REG_VALUE_3 = PCIE_SHADOW_REG_VALUE_3, + .d_A_LOCAL_SHADOW_REG_VALUE_4 = PCIE_SHADOW_REG_VALUE_4, + .d_A_LOCAL_SHADOW_REG_VALUE_5 = PCIE_SHADOW_REG_VALUE_5, + .d_A_LOCAL_SHADOW_REG_VALUE_6 = PCIE_SHADOW_REG_VALUE_6, + .d_A_LOCAL_SHADOW_REG_VALUE_7 = PCIE_SHADOW_REG_VALUE_7, + .d_A_LOCAL_SHADOW_REG_VALUE_8 = PCIE_SHADOW_REG_VALUE_8, + .d_A_LOCAL_SHADOW_REG_VALUE_9 = PCIE_SHADOW_REG_VALUE_9, + .d_A_LOCAL_SHADOW_REG_VALUE_10 = PCIE_SHADOW_REG_VALUE_10, + .d_A_LOCAL_SHADOW_REG_VALUE_11 = PCIE_SHADOW_REG_VALUE_11, + .d_A_LOCAL_SHADOW_REG_VALUE_12 = PCIE_SHADOW_REG_VALUE_12, + .d_A_LOCAL_SHADOW_REG_VALUE_13 = PCIE_SHADOW_REG_VALUE_13, + .d_A_LOCAL_SHADOW_REG_VALUE_14 = PCIE_SHADOW_REG_VALUE_14, + .d_A_LOCAL_SHADOW_REG_VALUE_15 = PCIE_SHADOW_REG_VALUE_15, + .d_A_LOCAL_SHADOW_REG_VALUE_16 = PCIE_SHADOW_REG_VALUE_16, + .d_A_LOCAL_SHADOW_REG_VALUE_17 = PCIE_SHADOW_REG_VALUE_17, + .d_A_LOCAL_SHADOW_REG_VALUE_18 = PCIE_SHADOW_REG_VALUE_18, + .d_A_LOCAL_SHADOW_REG_VALUE_19 = PCIE_SHADOW_REG_VALUE_19, + .d_A_LOCAL_SHADOW_REG_VALUE_20 = PCIE_SHADOW_REG_VALUE_20, + .d_A_LOCAL_SHADOW_REG_VALUE_21 = PCIE_SHADOW_REG_VALUE_21, + .d_A_LOCAL_SHADOW_REG_VALUE_22 = PCIE_SHADOW_REG_VALUE_22, + .d_A_LOCAL_SHADOW_REG_VALUE_23 = PCIE_SHADOW_REG_VALUE_23, + .d_A_LOCAL_SHADOW_REG_ADDRESS_0 = PCIE_SHADOW_REG_INTER_ADDR_0, + .d_A_LOCAL_SHADOW_REG_ADDRESS_1 = PCIE_SHADOW_REG_INTER_ADDR_1, + .d_A_LOCAL_SHADOW_REG_ADDRESS_2 = PCIE_SHADOW_REG_INTER_ADDR_2, + .d_A_LOCAL_SHADOW_REG_ADDRESS_3 = PCIE_SHADOW_REG_INTER_ADDR_3, + .d_A_LOCAL_SHADOW_REG_ADDRESS_4 = PCIE_SHADOW_REG_INTER_ADDR_4, + .d_A_LOCAL_SHADOW_REG_ADDRESS_5 = PCIE_SHADOW_REG_INTER_ADDR_5, + .d_A_LOCAL_SHADOW_REG_ADDRESS_6 = PCIE_SHADOW_REG_INTER_ADDR_6, + .d_A_LOCAL_SHADOW_REG_ADDRESS_7 = PCIE_SHADOW_REG_INTER_ADDR_7, + .d_A_LOCAL_SHADOW_REG_ADDRESS_8 = PCIE_SHADOW_REG_INTER_ADDR_8, + .d_A_LOCAL_SHADOW_REG_ADDRESS_9 = PCIE_SHADOW_REG_INTER_ADDR_9, + .d_A_LOCAL_SHADOW_REG_ADDRESS_10 = PCIE_SHADOW_REG_INTER_ADDR_10, + .d_A_LOCAL_SHADOW_REG_ADDRESS_11 = PCIE_SHADOW_REG_INTER_ADDR_11, + .d_A_LOCAL_SHADOW_REG_ADDRESS_12 = PCIE_SHADOW_REG_INTER_ADDR_12, + .d_A_LOCAL_SHADOW_REG_ADDRESS_13 = PCIE_SHADOW_REG_INTER_ADDR_13, + .d_A_LOCAL_SHADOW_REG_ADDRESS_14 = PCIE_SHADOW_REG_INTER_ADDR_14, + .d_A_LOCAL_SHADOW_REG_ADDRESS_15 = PCIE_SHADOW_REG_INTER_ADDR_15, + .d_A_LOCAL_SHADOW_REG_ADDRESS_16 = PCIE_SHADOW_REG_INTER_ADDR_16, + .d_A_LOCAL_SHADOW_REG_ADDRESS_17 = PCIE_SHADOW_REG_INTER_ADDR_17, + .d_A_LOCAL_SHADOW_REG_ADDRESS_18 = PCIE_SHADOW_REG_INTER_ADDR_18, + .d_A_LOCAL_SHADOW_REG_ADDRESS_19 = PCIE_SHADOW_REG_INTER_ADDR_19, + .d_A_LOCAL_SHADOW_REG_ADDRESS_20 = PCIE_SHADOW_REG_INTER_ADDR_20, + .d_A_LOCAL_SHADOW_REG_ADDRESS_21 = PCIE_SHADOW_REG_INTER_ADDR_21, + .d_A_LOCAL_SHADOW_REG_ADDRESS_22 = PCIE_SHADOW_REG_INTER_ADDR_22, + .d_A_LOCAL_SHADOW_REG_ADDRESS_23 = PCIE_SHADOW_REG_INTER_ADDR_23, +}; + +#else + struct host_shadow_regs_s genoa_host_shadow_regs = { .d_A_LOCAL_SHADOW_REG_VALUE_0 = GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_0, @@ -2923,5 +3028,6 @@ struct host_shadow_regs_s genoa_host_shadow_regs = { .d_A_LOCAL_SHADOW_REG_ADDRESS_23 = GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_23 }; +#endif #endif /* ADRASTEA_REG_DEF_H */