From fec94ae9db519314db8e48f1bb74016b7dd132d7 Mon Sep 17 00:00:00 2001 From: Govindaraj Rajagopal Date: Thu, 2 Apr 2020 10:45:37 +0530 Subject: [PATCH 1/3] dt-bindings: media: Add video driver bindings for Shima Add the video driver device tree bindings for Shima. Change-Id: Ife676bd354d9ac5a4f68dda9f415695770e95572 --- bindings/media/video/msm-vidc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/media/video/msm-vidc.txt b/bindings/media/video/msm-vidc.txt index 4b3c2dd4d884..06827a874391 100644 --- a/bindings/media/video/msm-vidc.txt +++ b/bindings/media/video/msm-vidc.txt @@ -7,6 +7,7 @@ Required properties: - compatible : one of: - "qcom,msm-vidc" - "qcom,lahaina-vidc" : Invokes driver-specific data for LAHAINA. + - "qcom,shima-vidc" : Invokes driver-specific data for SHIMA. Optional properties: - reg : offset and length of the register set for the device. From e3ccfb3440498f8f957e9a0b4fc0a9535bca4f90 Mon Sep 17 00:00:00 2001 From: Govindaraj Rajagopal Date: Wed, 1 Apr 2020 21:41:15 +0530 Subject: [PATCH 2/3] ARM: dts: msm: Add venus pil node for shima Add venus pil node to facilitate VENUS subsystem loading for shima target. Change-Id: Ie8fc213043b264ae89c1e2a7aec7174eb3505144 --- qcom/shima.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 25a2e7145ddf..d455b100dccc 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -870,6 +870,32 @@ }; }; + qcom,venus@aab0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaab0000 0x2000>; + + vdd-supply = <&video_cc_mvs0c_gdsc>; + qcom,proxy-reg-names = "vdd"; + qcom,complete-ramdump; + + clocks = <&videocc VIDEO_CC_XO_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_AHB_CLK>; + clock-names = "xo", "core", "ahb"; + qcom,proxy-clock-names = "xo", "core", "ahb"; + + qcom,core-freq = <200000000>; + qcom,ahb-freq = <200000000>; + + qcom,pas-id = <9>; + interconnect-names = "pil-venus"; + interconnects = <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; + qmp_aop: qcom,qmp-aop@c300000 { compatible = "qcom,qmp-mbox"; mboxes = <&ipcc_mproc IPCC_CLIENT_AOP From df640759cfbc0792e9ce02fe8ba5ea7a749eb220 Mon Sep 17 00:00:00 2001 From: Govindaraj Rajagopal Date: Thu, 26 Mar 2020 17:32:02 +0530 Subject: [PATCH 3/3] ARM: dts: msm: Add video device for shima Add video device node for shima. Change-Id: I2b934e61336802eb5c5998752273fe81a33362b5 --- qcom/shima-vidc.dtsi | 294 +++++++++++++++++++++++++++++++++++++++++++ qcom/shima.dtsi | 1 + 2 files changed, 295 insertions(+) create mode 100644 qcom/shima-vidc.dtsi diff --git a/qcom/shima-vidc.dtsi b/qcom/shima-vidc.dtsi new file mode 100644 index 000000000000..3b6894c007c2 --- /dev/null +++ b/qcom/shima-vidc.dtsi @@ -0,0 +1,294 @@ +&soc { + msm_vidc0: qcom,vidc0 { + compatible = "qcom,msm-vidc", "qcom,shima-vidc"; + status = "okay"; + sku-index = <1>; + reg = <0x0aa00000 0x00100000>; + interrupts = ; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + /* Supply */ + iris-ctl-supply = <&video_cc_mvs0c_gdsc>; + vcodec-supply = <&video_cc_mvs0_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axi0", + "core_clk", "vcodec_clk"; + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + qcom,proxy-clock-names = "gcc_video_axi0", + "core_clk", "vcodec_clk"; + /* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/ + qcom,clock-configs = <0x0 0x1 0x1>; + qcom,allowed-clock-rates = <240000000 338000000 + 364800000>; + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names = "video_axi_reset", "video_core_reset"; + + qcom,reg-presets = <0xB0088 0x0 0x11>; + + /* Video Firmware ELF image name */ + vidc,firmware-name = "vpu20_2v"; + + /* Bus Interconnects */ + interconnect-names = "venus-cnoc", "venus-ddr"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_VENUS_CFG>, + <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + /* Bus BW range (low, high) for each bus */ + qcom,bus-range-kbps = <1000 1000 + 1000 15000000>; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = <&apps_smmu 0x2900 0x0400>; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x25800000 0xba800000>; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&apps_smmu 0x2904 0x0400>; + qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */ + buffer-types = <0x480>; + virtual-addr-pool = <0x01000000 0x24800000>; + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&apps_smmu 0x2901 0x0404>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + buffer-types = <0x241>; + virtual-addr-pool = <0x00500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&apps_smmu 0x2903 0x0400>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + buffer-types = <0x106>; + virtual-addr-pool = <0x00500000 0xdfb00000>; + qcom,secure-context-bank; + }; + }; + + msm_vidc1: qcom,vidc1 { + compatible = "qcom,msm-vidc", "qcom,shima-vidc"; + status = "okay"; + sku-index = <2>; + reg = <0x0aa00000 0x00100000>; + interrupts = ; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + /* Supply */ + iris-ctl-supply = <&video_cc_mvs0c_gdsc>; + vcodec-supply = <&video_cc_mvs0_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axi0", + "core_clk", "vcodec_clk"; + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + qcom,proxy-clock-names = "gcc_video_axi0", + "core_clk", "vcodec_clk"; + /* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/ + qcom,clock-configs = <0x0 0x1 0x1>; + qcom,allowed-clock-rates = <201600000>; + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names = "video_axi_reset", "video_core_reset"; + + qcom,reg-presets = <0xB0088 0x0 0x11>; + + /* Video Firmware ELF image name */ + vidc,firmware-name = "vpu20_2v"; + + /* Bus Interconnects */ + interconnect-names = "venus-cnoc", "venus-ddr"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_VENUS_CFG>, + <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + /* Bus BW range (low, high) for each bus */ + qcom,bus-range-kbps = <1000 1000 + 1000 15000000>; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = <&apps_smmu 0x2900 0x0400>; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x25800000 0xba800000>; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&apps_smmu 0x2904 0x0400>; + qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */ + buffer-types = <0x480>; + virtual-addr-pool = <0x01000000 0x24800000>; + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&apps_smmu 0x2901 0x0404>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + buffer-types = <0x241>; + virtual-addr-pool = <0x00500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&apps_smmu 0x2903 0x0400>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + buffer-types = <0x106>; + virtual-addr-pool = <0x00500000 0xdfb00000>; + qcom,secure-context-bank; + }; + }; + + msm_vidc2: qcom,vidc2 { + compatible = "qcom,msm-vidc", "qcom,shima-vidc"; + status = "okay"; + sku-index = <0>; + reg = <0x0aa00000 0x00100000>; + interrupts = ; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + /* Supply */ + iris-ctl-supply = <&video_cc_mvs0c_gdsc>; + vcodec-supply = <&video_cc_mvs0_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axi0", + "core_clk", "vcodec_clk"; + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + qcom,proxy-clock-names = "gcc_video_axi0", + "core_clk", "vcodec_clk"; + /* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/ + qcom,clock-configs = <0x0 0x1 0x1>; + qcom,allowed-clock-rates = <240000000 338000000 + 366000000 444000000>; + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names = "video_axi_reset", "video_core_reset"; + + qcom,reg-presets = <0xB0088 0x0 0x11>; + + /* Video Firmware ELF image name */ + vidc,firmware-name = "vpu20_2v"; + + /* Bus Interconnects */ + interconnect-names = "venus-cnoc", "venus-ddr"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_VENUS_CFG>, + <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + /* Bus BW range (low, high) for each bus */ + qcom,bus-range-kbps = <1000 1000 + 1000 15000000>; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = <&apps_smmu 0x2900 0x0400>; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x25800000 0xba800000>; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&apps_smmu 0x2904 0x0400>; + qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */ + buffer-types = <0x480>; + virtual-addr-pool = <0x01000000 0x24800000>; + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&apps_smmu 0x2901 0x0404>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + buffer-types = <0x241>; + virtual-addr-pool = <0x00500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&apps_smmu 0x2903 0x0400>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + buffer-types = <0x106>; + virtual-addr-pool = <0x00500000 0xdfb00000>; + qcom,secure-context-bank; + }; + }; +}; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index d455b100dccc..fe1529d89969 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1491,6 +1491,7 @@ #include "shima-usb.dtsi" #include "ipcc-test-shima.dtsi" #include "msm-arm-smmu-shima.dtsi" +#include "shima-vidc.dtsi" &gcc_pcie_0_gdsc { status = "ok";