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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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sar: add aw9610 driver
add the driver of aw9610, modify the build scripts. Change-Id: Ic2be827fd281759c6184e68cfe5690f76642cc46 Signed-off-by: zhangh12 <zhangh12@motorola.com> Reviewed-on: https://gerrit.mot.com/2110739 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver Tested-by: Jira Key Reviewed-by: Xiangpo Zhao <zhaoxp3@motorola.com> Submit-Approved: Jira Key
This commit is contained in:
zhangh12
Hong Zhang
parent
73f818f4b5
commit
484bae18fd
8 changed files with 3757 additions and 0 deletions
14
drivers/misc/aw9610x/Android.mk
Normal file
14
drivers/misc/aw9610x/Android.mk
Normal file
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@ -0,0 +1,14 @@
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DLKM_DIR := motorola/kernel/modules
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LOCAL_PATH := $(call my-dir)
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ifeq ($(SX933X_USB_USE_ONLINE),true)
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KBUILD_OPTIONS += CONFIG_SX933X_POWER_SUPPLY_ONLINE=y
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endif
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include $(CLEAR_VARS)
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LOCAL_MODULE := aw9610x.ko
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LOCAL_MODULE_TAGS := optional
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LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
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LOCAL_ADDITIONAL_DEPENDENCIES := $(KERNEL_MODULES_OUT)/sensors_class.ko
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KBUILD_OPTIONS_GKI += GKI_OBJ_MODULE_DIR=gki
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include $(DLKM_DIR)/AndroidKernelModule.mk
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29
drivers/misc/aw9610x/Kbuild
Normal file
29
drivers/misc/aw9610x/Kbuild
Normal file
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@ -0,0 +1,29 @@
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KERNEL_DIR_PATH = $(shell find $(ANDROID_BUILD_TOP)/kernel/ -name "msm-*" -type d | head -1 | grep -i "kernel/msm-*")
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KERNEL_VERSION_NAME = $(shell basename $(KERNEL_DIR_PATH))
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KERNEL_PLATFORM_PATH = $(shell find $(ANDROID_BUILD_TOP) -maxdepth 1 -name "kernel_platform" -type d)
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# add -Wall to try to catch everything we can.
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EXTRA_CFLAGS += -Wall
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EXTRA_CFLAGS += -I$(ANDROID_BUILD_TOP)/motorola/kernel/modules/include
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ifneq ($(filter m y,$(CONFIG_SX933X_POWER_SUPPLY_ONLINE)),)
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EXTRA_CFLAGS += -DCONFIG_USE_POWER_SUPPLY_ONLINE
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endif
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ifneq (,$(KERNEL_DIR_PATH))
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EXTRA_CFLAGS += -I$(ANDROID_BUILD_TOP)/kernel/$(KERNEL_VERSION_NAME)/drivers/base
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else ifneq (,$(KERNEL_PLATFORM_PATH))
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EXTRA_CFLAGS += -I$(KERNEL_PLATFORM_PATH)/common/drivers/base
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else
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EXTRA_CFLAGS += -I$(ANDROID_BUILD_TOP)/kernel/drivers/base
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endif
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KBUILD_EXTRA_SYMBOLS += $(CURDIR)/$(KBUILD_EXTMOD)/../../sensors/$(GKI_OBJ_MODULE_DIR)/Module.symvers
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obj-m := aw9610x.o
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aw9610x-objs += aw9610x_sar.o
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aw9610x-objs += aw_bin_parse.o
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11
drivers/misc/aw9610x/Makefile
Normal file
11
drivers/misc/aw9610x/Makefile
Normal file
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@ -0,0 +1,11 @@
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KERNEL_SRC ?= /lib/modules/$(shell uname -r)/build
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all:
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$(MAKE) -C $(KERNEL_SRC) M=$(shell pwd) modules $(KBUILD_OPTIONS)
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modules_install:
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$(MAKE) INSTALL_MOD_STRIP=1 -C $(KERNEL_SRC) M=$(shell pwd) modules_install
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clean:
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$(MAKE) -C $(KERNEL_SRC) M=$(PWD) clean
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2288
drivers/misc/aw9610x/aw9610x_sar.c
Normal file
2288
drivers/misc/aw9610x/aw9610x_sar.c
Normal file
File diff suppressed because it is too large
Load diff
516
drivers/misc/aw9610x/aw_bin_parse.c
Normal file
516
drivers/misc/aw9610x/aw_bin_parse.c
Normal file
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@ -0,0 +1,516 @@
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/*
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* aw_bin_parse.c
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*
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* Copyright (c) 2020 AWINIC Technology CO., LTD
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/i2c.h>
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#include <linux/of_gpio.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/firmware.h>
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#include <linux/slab.h>
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#include <linux/version.h>
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#include <linux/input.h>
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#include <linux/interrupt.h>
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#include <linux/debugfs.h>
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#include <linux/miscdevice.h>
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#include <asm/uaccess.h>
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#include <linux/regmap.h>
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#include <linux/timer.h>
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#include <linux/workqueue.h>
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#include <linux/hrtimer.h>
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#include <linux/mutex.h>
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#include <linux/cdev.h>
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#include <linux/list.h>
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#include <linux/string.h>
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#include <linux/input/aw_bin_parse.h>
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#define AWINIC_CODE_VERSION "V0.0.7-V1.0.4" /* "code version"-"excel version" */
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#define DEBUG_LOG_LEVEL
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#ifdef DEBUG_LOG_LEVEL
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#define DBG(fmt, arg...) do {\
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printk("AWINIC_BIN %s,line= %d,"fmt, __func__, __LINE__, ##arg);\
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} while (0)
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#define DBG_ERR(fmt, arg...) do {\
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printk("AWINIC_BIN_ERR %s,line= %d,"fmt, __func__, __LINE__, ##arg);\
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} while (0)
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#else
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#define DBG(fmt, arg...) do {} while (0)
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#define DBG_ERR(fmt, arg...) do {} while (0)
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#endif
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#define printing_data_code
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typedef unsigned short int aw_uint16;
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typedef unsigned long int aw_uint32;
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#define BigLittleSwap16(A) ((((aw_uint16)(A) & 0xff00) >> 8) | \
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(((aw_uint16)(A) & 0x00ff) << 8))
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#define BigLittleSwap32(A) ((((aw_uint32)(A) & 0xff000000) >> 24) | \
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(((aw_uint32)(A) & 0x00ff0000) >> 8) | \
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(((aw_uint32)(A) & 0x0000ff00) << 8) | \
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(((aw_uint32)(A) & 0x000000ff) << 24))
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/**
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*
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* Interface function
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*
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* return value:
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* value = 0 :success;
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* value = -1 :check bin header version
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* value = -2 :check bin data type
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* value = -3 :check sum or check bin data len error
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* value = -4 :check data version
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* value = -5 :check register num
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* value = -6 :check dsp reg num
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* value = -7 :check soc app num
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* value = -8 :bin is NULL point
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*
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**/
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/********************************************************
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*
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* check sum data
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*
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********************************************************/
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int aw_check_sum(struct aw_bin *bin, int bin_num)
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{
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unsigned int i = 0;
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unsigned int sum_data = 0;
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unsigned int check_sum = 0;
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char *p_check_sum = NULL;
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DBG("enter\n");
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p_check_sum =
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&(bin->info.data[(bin->header_info[bin_num].valid_data_addr -
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bin->header_info[bin_num].header_len)]);
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DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum);
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check_sum = GET_32_DATA(*(p_check_sum + 3),
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*(p_check_sum + 2),
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*(p_check_sum + 1), *(p_check_sum));
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for (i = 4;
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i <
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bin->header_info[bin_num].bin_data_len +
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bin->header_info[bin_num].header_len; i++) {
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sum_data += *(p_check_sum + i);
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}
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DBG("aw_bin_parse bin_num=%d, check_sum = 0x%x, sum_data = 0x%x\n",
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bin_num, check_sum, sum_data);
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if (sum_data != check_sum) {
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p_check_sum = NULL;
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DBG_ERR("aw_bin_parse check sum or check bin data len error\n");
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DBG_ERR("aw_bin_parse bin_num=%d, check_sum = 0x%x, sum_data = 0x%x\n", bin_num, check_sum, sum_data);
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return -3;
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}
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p_check_sum = NULL;
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return 0;
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}
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int aw_check_data_version(struct aw_bin *bin, int bin_num)
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{
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int i = 0;
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DBG("enter\n");
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for (i = DATA_VERSION_V1; i < DATA_VERSION_MAX; i++) {
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if (bin->header_info[bin_num].bin_data_ver == i) {
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return 0;
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}
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}
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DBG_ERR("aw_bin_parse Unrecognized this bin data version\n");
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return -4;
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}
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int aw_check_register_num_v1(struct aw_bin *bin, int bin_num)
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{
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unsigned int check_register_num = 0;
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unsigned int parse_register_num = 0;
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char *p_check_sum = NULL;
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DBG("enter\n");
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p_check_sum =
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&(bin->info.data[(bin->header_info[bin_num].valid_data_addr)]);
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DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum);
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parse_register_num = GET_32_DATA(*(p_check_sum + 3),
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*(p_check_sum + 2),
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*(p_check_sum + 1), *(p_check_sum));
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check_register_num = (bin->header_info[bin_num].bin_data_len - 4) /
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(bin->header_info[bin_num].reg_byte_len +
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bin->header_info[bin_num].data_byte_len);
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DBG
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("aw_bin_parse bin_num=%d, parse_register_num = 0x%x, check_register_num = 0x%x\n",
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bin_num, parse_register_num, check_register_num);
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if (parse_register_num != check_register_num) {
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p_check_sum = NULL;
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DBG_ERR("aw_bin_parse register num is error\n");
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DBG_ERR("aw_bin_parse bin_num=%d, parse_register_num = 0x%x, check_register_num = 0x%x\n", bin_num, parse_register_num, check_register_num);
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return -5;
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}
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bin->header_info[bin_num].reg_num = parse_register_num;
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bin->header_info[bin_num].valid_data_len =
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bin->header_info[bin_num].bin_data_len - 4;
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p_check_sum = NULL;
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bin->header_info[bin_num].valid_data_addr =
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bin->header_info[bin_num].valid_data_addr + 4;
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return 0;
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}
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int aw_check_dsp_reg_num_v1(struct aw_bin *bin, int bin_num)
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{
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unsigned int check_dsp_reg_num = 0;
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unsigned int parse_dsp_reg_num = 0;
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char *p_check_sum = NULL;
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DBG("enter\n");
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p_check_sum =
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&(bin->info.data[(bin->header_info[bin_num].valid_data_addr)]);
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DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum);
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parse_dsp_reg_num = GET_32_DATA(*(p_check_sum + 7),
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*(p_check_sum + 6),
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*(p_check_sum + 5), *(p_check_sum + 4));
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bin->header_info[bin_num].reg_data_byte_len =
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GET_32_DATA(*(p_check_sum + 11), *(p_check_sum + 10),
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*(p_check_sum + 9), *(p_check_sum + 8));
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check_dsp_reg_num =
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(bin->header_info[bin_num].bin_data_len -
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12) / bin->header_info[bin_num].reg_data_byte_len;
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DBG
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("aw_bin_parse bin_num=%d, parse_dsp_reg_num = 0x%x, check_dsp_reg_num = 0x%x\n",
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bin_num, parse_dsp_reg_num, check_dsp_reg_num);
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if (parse_dsp_reg_num != check_dsp_reg_num) {
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p_check_sum = NULL;
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DBG_ERR("aw_bin_parse dsp reg num is error\n");
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DBG_ERR("aw_bin_parse bin_num=%d, parse_dsp_reg_num = 0x%x, check_dsp_reg_num = 0x%x\n", bin_num, parse_dsp_reg_num, check_dsp_reg_num);
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return -6;
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}
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bin->header_info[bin_num].download_addr =
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GET_32_DATA(*(p_check_sum + 3), *(p_check_sum + 2),
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*(p_check_sum + 1), *(p_check_sum));
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bin->header_info[bin_num].reg_num = parse_dsp_reg_num;
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bin->header_info[bin_num].valid_data_len =
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bin->header_info[bin_num].bin_data_len - 12;
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p_check_sum = NULL;
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bin->header_info[bin_num].valid_data_addr =
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bin->header_info[bin_num].valid_data_addr + 12;
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return 0;
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}
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int aw_check_soc_app_num_v1(struct aw_bin *bin, int bin_num)
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{
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unsigned int check_soc_app_num = 0;
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unsigned int parse_soc_app_num = 0;
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char *p_check_sum = NULL;
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DBG("enter\n");
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p_check_sum =
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&(bin->info.data[(bin->header_info[bin_num].valid_data_addr)]);
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DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum);
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bin->header_info[bin_num].app_version = GET_32_DATA(*(p_check_sum + 3),
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*(p_check_sum + 2),
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*(p_check_sum + 1),
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*(p_check_sum));
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parse_soc_app_num = GET_32_DATA(*(p_check_sum + 11),
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*(p_check_sum + 10),
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*(p_check_sum + 9), *(p_check_sum + 8));
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check_soc_app_num = bin->header_info[bin_num].bin_data_len - 12;
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DBG
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("aw_bin_parse bin_num=%d, parse_soc_app_num = 0x%x, check_soc_app_num = 0x%x\n",
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bin_num, parse_soc_app_num, check_soc_app_num);
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if (parse_soc_app_num != check_soc_app_num) {
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p_check_sum = NULL;
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DBG_ERR("aw_bin_parse soc app num is error\n");
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DBG_ERR("aw_bin_parse bin_num=%d, parse_soc_app_num = 0x%x, check_soc_app_num = 0x%x\n", bin_num, parse_soc_app_num, check_soc_app_num);
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return -7;
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}
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bin->header_info[bin_num].reg_num = parse_soc_app_num;
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bin->header_info[bin_num].download_addr =
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GET_32_DATA(*(p_check_sum + 7), *(p_check_sum + 6),
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*(p_check_sum + 5), *(p_check_sum + 4));
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bin->header_info[bin_num].valid_data_len =
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bin->header_info[bin_num].bin_data_len - 12;
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p_check_sum = NULL;
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bin->header_info[bin_num].valid_data_addr =
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bin->header_info[bin_num].valid_data_addr + 12;
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return 0;
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}
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/************************
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***
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***bin header 1_0_0
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***
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************************/
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void aw_get_single_bin_header_1_0_0(struct aw_bin *bin)
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{
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int i;
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DBG("enter %s\n", __func__);
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bin->header_info[bin->all_bin_parse_num].header_len = 60;
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bin->header_info[bin->all_bin_parse_num].check_sum =
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GET_32_DATA(*(bin->p_addr + 3), *(bin->p_addr + 2),
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*(bin->p_addr + 1), *(bin->p_addr));
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bin->header_info[bin->all_bin_parse_num].header_ver =
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GET_32_DATA(*(bin->p_addr + 7), *(bin->p_addr + 6),
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*(bin->p_addr + 5), *(bin->p_addr + 4));
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bin->header_info[bin->all_bin_parse_num].bin_data_type =
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GET_32_DATA(*(bin->p_addr + 11), *(bin->p_addr + 10),
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*(bin->p_addr + 9), *(bin->p_addr + 8));
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bin->header_info[bin->all_bin_parse_num].bin_data_ver =
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GET_32_DATA(*(bin->p_addr + 15), *(bin->p_addr + 14),
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*(bin->p_addr + 13), *(bin->p_addr + 12));
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bin->header_info[bin->all_bin_parse_num].bin_data_len =
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GET_32_DATA(*(bin->p_addr + 19), *(bin->p_addr + 18),
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*(bin->p_addr + 17), *(bin->p_addr + 16));
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bin->header_info[bin->all_bin_parse_num].ui_ver =
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GET_32_DATA(*(bin->p_addr + 23), *(bin->p_addr + 22),
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*(bin->p_addr + 21), *(bin->p_addr + 20));
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bin->header_info[bin->all_bin_parse_num].reg_byte_len =
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GET_32_DATA(*(bin->p_addr + 35), *(bin->p_addr + 34),
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*(bin->p_addr + 33), *(bin->p_addr + 32));
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bin->header_info[bin->all_bin_parse_num].data_byte_len =
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GET_32_DATA(*(bin->p_addr + 39), *(bin->p_addr + 38),
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*(bin->p_addr + 37), *(bin->p_addr + 36));
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bin->header_info[bin->all_bin_parse_num].device_addr =
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GET_32_DATA(*(bin->p_addr + 43), *(bin->p_addr + 42),
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*(bin->p_addr + 41), *(bin->p_addr + 40));
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for (i = 0; i < 8; i++) {
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bin->header_info[bin->all_bin_parse_num].chip_type[i] =
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*(bin->p_addr + 24 + i);
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}
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bin->header_info[bin->all_bin_parse_num].chip_type[i] = '\0';
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DBG("%s : enter chip_type is %s\n", __func__,
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bin->header_info[bin->all_bin_parse_num].chip_type);
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bin->header_info[bin->all_bin_parse_num].reg_num = 0x00000000;
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bin->header_info[bin->all_bin_parse_num].reg_data_byte_len = 0x00000000;
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bin->header_info[bin->all_bin_parse_num].download_addr = 0x00000000;
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bin->header_info[bin->all_bin_parse_num].app_version = 0x00000000;
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bin->header_info[bin->all_bin_parse_num].valid_data_len = 0x00000000;
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bin->all_bin_parse_num += 1;
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}
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|
||||
int aw_parse_each_of_multi_bins_1_0_0(unsigned int bin_num, int bin_serial_num,
|
||||
struct aw_bin *bin)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned int bin_start_addr = 0;
|
||||
unsigned int valid_data_len = 0;
|
||||
DBG("aw_bin_parse enter multi bin branch -- %s\n", __func__);
|
||||
if (!bin_serial_num) {
|
||||
bin_start_addr = GET_32_DATA(*(bin->p_addr + 67),
|
||||
*(bin->p_addr + 66),
|
||||
*(bin->p_addr + 65),
|
||||
*(bin->p_addr + 64));
|
||||
bin->p_addr += (60 + bin_start_addr);
|
||||
bin->header_info[bin->all_bin_parse_num].valid_data_addr =
|
||||
bin->header_info[bin->all_bin_parse_num -
|
||||
1].valid_data_addr + 4 + 8 * bin_num + 60;
|
||||
} else {
|
||||
valid_data_len =
|
||||
bin->header_info[bin->all_bin_parse_num - 1].bin_data_len;
|
||||
bin->p_addr += (60 + valid_data_len);
|
||||
bin->header_info[bin->all_bin_parse_num].valid_data_addr =
|
||||
bin->header_info[bin->all_bin_parse_num -
|
||||
1].valid_data_addr +
|
||||
bin->header_info[bin->all_bin_parse_num - 1].bin_data_len +
|
||||
60;
|
||||
}
|
||||
|
||||
ret = aw_parse_bin_header_1_0_0(bin);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Get the number of bins in multi bins, and set a for loop, loop processing each bin data */
|
||||
int aw_get_multi_bin_header_1_0_0(struct aw_bin *bin)
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
unsigned int bin_num = 0;
|
||||
DBG("aw_bin_parse enter multi bin branch -- %s\n", __func__);
|
||||
bin_num = GET_32_DATA(*(bin->p_addr + 63),
|
||||
*(bin->p_addr + 62),
|
||||
*(bin->p_addr + 61), *(bin->p_addr + 60));
|
||||
if (bin->multi_bin_parse_num == 1) {
|
||||
bin->header_info[bin->all_bin_parse_num].valid_data_addr = 60;
|
||||
}
|
||||
aw_get_single_bin_header_1_0_0(bin);
|
||||
|
||||
for (i = 0; i < bin_num; i++) {
|
||||
DBG("aw_bin_parse enter multi bin for is %d\n", i);
|
||||
ret = aw_parse_each_of_multi_bins_1_0_0(bin_num, i, bin);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
*
|
||||
* If the bin framework header version is 1.0.0,
|
||||
determine the data type of bin, and then perform different processing
|
||||
according to the data type
|
||||
If it is a single bin data type, write the data directly into the structure array
|
||||
If it is a multi-bin data type, first obtain the number of bins,
|
||||
and then recursively call the bin frame header processing function
|
||||
according to the bin number to process the frame header information of each bin separately
|
||||
*
|
||||
********************************************************/
|
||||
int aw_parse_bin_header_1_0_0(struct aw_bin *bin)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned int bin_data_type;
|
||||
DBG("enter %s\n", __func__);
|
||||
bin_data_type = GET_32_DATA(*(bin->p_addr + 11),
|
||||
*(bin->p_addr + 10),
|
||||
*(bin->p_addr + 9), *(bin->p_addr + 8));
|
||||
DBG("aw_bin_parse bin_data_type 0x%x\n", bin_data_type);
|
||||
switch (bin_data_type) {
|
||||
case DATA_TYPE_REGISTER:
|
||||
case DATA_TYPE_DSP_REG:
|
||||
case DATA_TYPE_SOC_APP:
|
||||
/* Divided into two processing methods,
|
||||
one is single bin processing,
|
||||
and the other is single bin processing in multi bin */
|
||||
DBG("aw_bin_parse enter single bin branch\n");
|
||||
bin->single_bin_parse_num += 1;
|
||||
DBG("%s bin->single_bin_parse_num is %d\n", __func__,
|
||||
bin->single_bin_parse_num);
|
||||
if (!bin->multi_bin_parse_num) {
|
||||
bin->header_info[bin->
|
||||
all_bin_parse_num].valid_data_addr =
|
||||
60;
|
||||
}
|
||||
aw_get_single_bin_header_1_0_0(bin);
|
||||
break;
|
||||
case DATA_TYPE_MULTI_BINS:
|
||||
/* Get the number of times to enter multi bins */
|
||||
DBG("aw_bin_parse enter multi bin branch\n");
|
||||
bin->multi_bin_parse_num += 1;
|
||||
DBG("%s bin->multi_bin_parse_num is %d\n", __func__,
|
||||
bin->multi_bin_parse_num);
|
||||
ret = aw_get_multi_bin_header_1_0_0(bin);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DBG_ERR("aw_bin_parse Unrecognized this bin data type\n");
|
||||
return -2;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* get the bin's header version */
|
||||
static int aw_check_bin_header_version(struct aw_bin *bin)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned int header_version = 0;
|
||||
|
||||
header_version = GET_32_DATA(*(bin->p_addr + 7),
|
||||
*(bin->p_addr + 6),
|
||||
*(bin->p_addr + 5), *(bin->p_addr + 4));
|
||||
|
||||
DBG("aw_bin_parse header_version 0x%x\n", header_version);
|
||||
|
||||
/* Write data to the corresponding structure array
|
||||
according to different formats of the bin frame header version */
|
||||
switch (header_version) {
|
||||
case HEADER_VERSION_1_0_0:
|
||||
ret = aw_parse_bin_header_1_0_0(bin);
|
||||
return ret;
|
||||
default:
|
||||
DBG_ERR("aw_bin_parse Unrecognized this bin header version \n");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
int aw_parsing_bin_file(struct aw_bin *bin)
|
||||
{
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
|
||||
DBG("aw_bin_parse code version:%s\n", AWINIC_CODE_VERSION);
|
||||
if (!bin) {
|
||||
DBG_ERR("aw_bin_parse bin is NULL\n");
|
||||
return -8;
|
||||
}
|
||||
bin->p_addr = bin->info.data;
|
||||
bin->all_bin_parse_num = 0;
|
||||
bin->multi_bin_parse_num = 0;
|
||||
bin->single_bin_parse_num = 0;
|
||||
|
||||
/* filling bins header info */
|
||||
ret = aw_check_bin_header_version(bin);
|
||||
if (ret < 0) {
|
||||
DBG_ERR("aw_bin_parse check bin header version error\n");
|
||||
return ret;
|
||||
}
|
||||
bin->p_addr = NULL;
|
||||
|
||||
/* check bin header info */
|
||||
for (i = 0; i < bin->all_bin_parse_num; i++) {
|
||||
/* check sum */
|
||||
ret = aw_check_sum(bin, i);
|
||||
if (ret < 0) {
|
||||
DBG_ERR("aw_bin_parse check sum data error\n");
|
||||
return ret;
|
||||
}
|
||||
/* check bin data version */
|
||||
ret = aw_check_data_version(bin, i);
|
||||
if (ret < 0) {
|
||||
DBG_ERR("aw_bin_parse check data version error\n");
|
||||
return ret;
|
||||
}
|
||||
/* check valid data */
|
||||
if (bin->header_info[i].bin_data_ver == DATA_VERSION_V1) {
|
||||
/* check register num */
|
||||
if (bin->header_info[i].bin_data_type ==
|
||||
DATA_TYPE_REGISTER) {
|
||||
ret = aw_check_register_num_v1(bin, i);
|
||||
if (ret < 0) {
|
||||
DBG_ERR
|
||||
("aw_bin_parse check register num error\n");
|
||||
return ret;
|
||||
}
|
||||
/* check dsp reg num */
|
||||
} else if (bin->header_info[i].bin_data_type ==
|
||||
DATA_TYPE_DSP_REG) {
|
||||
ret = aw_check_dsp_reg_num_v1(bin, i);
|
||||
if (ret < 0) {
|
||||
DBG_ERR
|
||||
("aw_bin_parse check dsp reg num error\n");
|
||||
return ret;
|
||||
}
|
||||
/* check soc app num */
|
||||
} else if (bin->header_info[i].bin_data_type ==
|
||||
DATA_TYPE_SOC_APP) {
|
||||
ret = aw_check_soc_app_num_v1(bin, i);
|
||||
if (ret < 0) {
|
||||
DBG_ERR
|
||||
("aw_bin_parse check soc app num error\n");
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
bin->header_info[i].valid_data_len =
|
||||
bin->header_info[i].bin_data_len;
|
||||
}
|
||||
}
|
||||
}
|
||||
DBG("aw_bin_parse parsing success\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
476
include/linux/input/aw9610x.h
Normal file
476
include/linux/input/aw9610x.h
Normal file
|
|
@ -0,0 +1,476 @@
|
|||
#ifndef _AW9610X_H_
|
||||
#define _AW9610X_H_
|
||||
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/hrtimer.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/cdev.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#define AW_POWER_ON
|
||||
|
||||
#define AW9610X_CHIP_ID (0xa961)
|
||||
#define AW_SAR_SUCCESS (0)
|
||||
#define AW_VCC_MIN_UV (1700000)
|
||||
#define AW_VCC_MAX_UV (3600000)
|
||||
#define AW_SPE_REG_NUM (8)
|
||||
#define AW_CLA1_SPE_REG_NUM (6)
|
||||
#define AW_SPE_REG_DWORD (8)
|
||||
#define AW_DATA_PROCESS_FACTOR (1024)
|
||||
#define AW_CHANNEL_NUMBER_TWO 0x02
|
||||
#define AW_CHANNEL_NUMBER_THREE 0x03
|
||||
#define AW_CHANNEL_NUMBER_FOUR 0x04
|
||||
#define AW_CHANNEL_NUMBER_FIVE 0x05
|
||||
|
||||
#if 0
|
||||
#define AWLOGD(dev, format, arg...) \
|
||||
do {\
|
||||
dev_printk(KERN_DEBUG, dev, \
|
||||
"[%s:%d] "format"\n", __func__, __LINE__, ##arg);\
|
||||
} while (0)
|
||||
|
||||
#define AWLOGI(dev, format, arg...) \
|
||||
do {\
|
||||
dev_printk(KERN_INFO, dev, \
|
||||
"[%s:%d] "format"\n", __func__, __LINE__, ##arg);\
|
||||
} while (0)
|
||||
|
||||
#define AWLOGE(dev, format, arg...) \
|
||||
do {\
|
||||
dev_printk(KERN_ERR, dev, \
|
||||
"[%s:%d] "format"\n", __func__, __LINE__, ##arg);\
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
/**********************************************
|
||||
* cfg load situation
|
||||
**********************************************/
|
||||
enum aw9610x_cfg_situ {
|
||||
AW_CFG_UNLOAD,
|
||||
AW_CFG_LOADED,
|
||||
};
|
||||
|
||||
/**********************************************
|
||||
*spereg cali flag
|
||||
**********************************************/
|
||||
enum aw9610x_cali_flag {
|
||||
AW_NO_CALI,
|
||||
AW_CALI,
|
||||
};
|
||||
|
||||
enum aw9610x_sar_vers {
|
||||
AW9610X = 2,
|
||||
AW9610XA = 6,
|
||||
AW9610XB = 0xa,
|
||||
};
|
||||
|
||||
enum aw9610x_operation_mode {
|
||||
AW9610X_ACTIVE_MODE = 1,
|
||||
AW9610X_SLEEP_MODE,
|
||||
AW9610X_DEEPSLEEP_MODE,
|
||||
};
|
||||
|
||||
enum aw9610x_operation_ap_mode {
|
||||
AW9610X_SLEEP_AP_MODE = 0,
|
||||
AW9610X_ACTIVE_AP_MODE,
|
||||
AW9610X_DEEPSLEEP_AP_MODE,
|
||||
};
|
||||
/**********************************************
|
||||
*spereg addr offset
|
||||
**********************************************/
|
||||
enum aw9610x_spereg_addr_offset {
|
||||
AW_CL1SPE_CALI_OS = 20,
|
||||
AW_CL1SPE_DEAL_OS = 60,
|
||||
AW_CL2SPE_CALI_OS = 4,
|
||||
AW_CL2SPE_DEAL_OS = 4,
|
||||
};
|
||||
|
||||
/**********************************************
|
||||
*the flag of i2c read/write
|
||||
**********************************************/
|
||||
enum aw9610x_function_flag {
|
||||
AW9610X_FUNC_OFF,
|
||||
AW9610X_FUNC_ON,
|
||||
};
|
||||
|
||||
/**********************************************
|
||||
*the flag of i2c read/write
|
||||
**********************************************/
|
||||
enum aw9610x_i2c_flags {
|
||||
AW9610X_I2C_WR,
|
||||
AW9610X_I2C_RD,
|
||||
};
|
||||
|
||||
/*********************************************************
|
||||
* aw9610x error flag:
|
||||
* @AW_MALLOC_FAILED: malloc space failed.
|
||||
* @AW_CHIPID_FAILED: the chipid is error.
|
||||
* @AW_IRQIO_FAILED: irq gpio invalid.
|
||||
* @AW_IRQ_REQUEST_FAILED: irq requst failed.
|
||||
* @AW_INPUT_ALLOCATE_FILED : inpt malloc failed.
|
||||
* @AW_INPUT_REGISTER_FAILED : inpt_dev register failed.
|
||||
* @AW_CFG_LOAD_TIME_FAILED : cfg situation not confirmed.
|
||||
* @AW_TRIM_ERROR : the chip no trim.
|
||||
* @AW_IRQGPIO_FAILED : irq gpio is invalid.
|
||||
* @AW_MULTIPLE_SAR_FAILED : sar-num is error in aw9610x.dtsi
|
||||
**********************************************************/
|
||||
enum aw9610x_err_flags {
|
||||
AW_MALLOC_FAILED = 200,
|
||||
AW_CHIPID_FAILED,
|
||||
AW_IRQIO_FAILED,
|
||||
AW_IRQ_REQUEST_FAILED,
|
||||
AW_INPUT_ALLOCATE_FILED,
|
||||
AW_INPUT_REGISTER_FAILED,
|
||||
AW_CFG_LOAD_TIME_FAILED,
|
||||
AW_TRIM_ERROR,
|
||||
AW_IRQGPIO_FAILED,
|
||||
AW_MULTIPLE_SAR_FAILED,
|
||||
AW_VERS_ERR,
|
||||
};
|
||||
|
||||
/**********************************************
|
||||
* mutiple sar define
|
||||
**********************************************/
|
||||
enum aw9610x_multiple_sar {
|
||||
AW_SAR0,
|
||||
AW_SAR1,
|
||||
AW_SAR_MAX,
|
||||
};
|
||||
|
||||
/**********************************************
|
||||
* mutiple channel define
|
||||
**********************************************/
|
||||
enum aw9610x_ichannel {
|
||||
AW_CHANNEL0,
|
||||
AW_CHANNEL1,
|
||||
AW_CHANNEL2,
|
||||
AW_CHANNEL3,
|
||||
AW_CHANNEL4,
|
||||
AW_CHANNEL5,
|
||||
AW_CHANNEL_MAX,
|
||||
};
|
||||
|
||||
/************************************************************
|
||||
* Interrupts near or far from the threshold will be triggered
|
||||
*************************************************************/
|
||||
enum aw9610x_irq_trigger_position {
|
||||
FAR,
|
||||
TRIGGER_TH0,
|
||||
TRIGGER_TH1 = 0x03,
|
||||
TRIGGER_TH2 = 0x07,
|
||||
TRIGGER_TH3 = 0x0f,
|
||||
};
|
||||
|
||||
|
||||
struct aw_i2c_package {
|
||||
uint8_t addr_bytes;
|
||||
uint8_t data_bytes;
|
||||
uint8_t reg_num;
|
||||
uint8_t init_addr[4];
|
||||
uint8_t *p_reg_data;
|
||||
};
|
||||
|
||||
struct aw_pad {
|
||||
uint8_t curr_state;
|
||||
uint8_t last_state;
|
||||
struct input_dev *input;
|
||||
uint8_t *name;
|
||||
};
|
||||
|
||||
struct aw9610x {
|
||||
uint8_t cali_flag;
|
||||
uint8_t power_prox;
|
||||
uint8_t vers;
|
||||
uint8_t mode_flag0;
|
||||
uint8_t mode_flag1;
|
||||
uint8_t pad;
|
||||
uint32_t aw_channel_number;
|
||||
const char *aw_ch_name[12];
|
||||
|
||||
uint32_t sar_num;
|
||||
int32_t irq_gpio;
|
||||
int32_t to_irq;
|
||||
uint32_t irq_status;
|
||||
uint32_t hostirqen;
|
||||
uint32_t first_irq_flag;
|
||||
uint32_t mode;
|
||||
uint32_t int_state;
|
||||
uint16_t read_reg;
|
||||
bool read_flag;
|
||||
bool pwprox_dete;
|
||||
bool firmware_flag;
|
||||
bool satu_release;
|
||||
bool power_enable;
|
||||
|
||||
struct work_struct ps_notify_work;
|
||||
struct notifier_block ps_notif;
|
||||
bool ps_is_present;
|
||||
|
||||
struct delayed_work cfg_work;
|
||||
struct i2c_client *i2c;
|
||||
struct device *dev;
|
||||
struct delayed_work dworker; /* work struct for worker function */
|
||||
struct aw_bin *aw_bin;
|
||||
struct aw_i2c_package aw_i2c_package;
|
||||
struct aw_pad *aw_pad;
|
||||
struct regulator *vcc;
|
||||
uint8_t satu_flag[6];
|
||||
uint32_t spedata[8];
|
||||
uint32_t satu_data[6];
|
||||
uint32_t nvspe_data[8];
|
||||
uint8_t chip_name[9];
|
||||
uint8_t cfg_name[20];
|
||||
uint8_t cfg_vers[2];
|
||||
};
|
||||
|
||||
struct aw9610x_cfg {
|
||||
int len;
|
||||
unsigned int data[];
|
||||
};
|
||||
|
||||
struct aw_pad pad_event[] =
|
||||
{
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar0_pad0",
|
||||
},
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar0_pad1",
|
||||
},
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar0_pad2",
|
||||
},
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar0_pad3",
|
||||
},
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar0_pad4",
|
||||
},
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar0_pad5",
|
||||
},
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar1_pad0",
|
||||
},
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar1_pad1",
|
||||
},
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar1_pad2",
|
||||
},
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar1_pad3",
|
||||
},
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar1_pad4",
|
||||
},
|
||||
{
|
||||
.curr_state = 0,
|
||||
.last_state = 0,
|
||||
//.name = "sar1_pad5",
|
||||
},
|
||||
};
|
||||
|
||||
uint32_t attr_buf[] = {
|
||||
8, 10,
|
||||
9, 100,
|
||||
10, 1000,
|
||||
};
|
||||
|
||||
#ifdef USE_SENSORS_CLASS
|
||||
struct sensors_classdev sensors_capsensor_chs[AW_CHANNEL_MAX] = {
|
||||
[0 ... AW_CHANNEL_MAX-1] = {
|
||||
//.name = "sar0_pad0",
|
||||
.vendor = "awinic",
|
||||
.version = 1,
|
||||
.type = SENSOR_TYPE_MOTO_CAPSENSE,
|
||||
.max_range = "5",
|
||||
.resolution = "5.0",
|
||||
.sensor_power = "0.12",
|
||||
.min_delay = 0, /* in microseconds */
|
||||
.fifo_reserved_event_count = 0,
|
||||
.fifo_max_event_count = 0,
|
||||
.enabled = 0,
|
||||
.delay_msec = 100,
|
||||
.sensors_enable = NULL,
|
||||
.sensors_poll_delay = NULL,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
/******************************************************
|
||||
* Register Detail
|
||||
******************************************************/
|
||||
uint32_t aw9610x_reg_default[] = {
|
||||
0x0000, 0x00003f3f,
|
||||
0x0004, 0x00000064,
|
||||
0x0008, 0x0017c11e,
|
||||
0x000c, 0x05000000,
|
||||
0x0010, 0x00093ffd,
|
||||
0x0014, 0x19240009,
|
||||
0x0018, 0xd81c0207,
|
||||
0x001c, 0xff000000,
|
||||
0x0020, 0x00241900,
|
||||
0x0024, 0x00093ff7,
|
||||
0x0028, 0x58020009,
|
||||
0x002c, 0xd81c0207,
|
||||
0x0030, 0xff000000,
|
||||
0x0034, 0x00025800,
|
||||
0x0038, 0x00093fdf,
|
||||
0x003c, 0x7d3b0009,
|
||||
0x0040, 0xd81c0207,
|
||||
0x0044, 0xff000000,
|
||||
0x0048, 0x003b7d00,
|
||||
0x004c, 0x00093f7f,
|
||||
0x0050, 0xe9310009,
|
||||
0x0054, 0xd81c0207,
|
||||
0x0058, 0xff000000,
|
||||
0x005c, 0x0031e900,
|
||||
0x0060, 0x00093dff,
|
||||
0x0064, 0x1a0c0009,
|
||||
0x0068, 0xd81c0207,
|
||||
0x006c, 0xff000000,
|
||||
0x0070, 0x000c1a00,
|
||||
0x0074, 0x80093fff,
|
||||
0x0078, 0x043d0009,
|
||||
0x007c, 0xd81c0207,
|
||||
0x0080, 0xff000000,
|
||||
0x0084, 0x003d0400,
|
||||
0x00a0, 0xe6400000,
|
||||
0x00a4, 0x00000000,
|
||||
0x00a8, 0x010408d2,
|
||||
0x00ac, 0x00000000,
|
||||
0x00b0, 0x00000000,
|
||||
0x00b8, 0x00005fff,
|
||||
0x00bc, 0x00000000,
|
||||
0x00c0, 0x00000000,
|
||||
0x00c4, 0x00000000,
|
||||
0x00c8, 0x00000000,
|
||||
0x00cc, 0x00000000,
|
||||
0x00d0, 0x00000000,
|
||||
0x00d4, 0x00000000,
|
||||
0x00d8, 0x00000000,
|
||||
0x00dc, 0xe6447800,
|
||||
0x00e0, 0x78000000,
|
||||
0x00e4, 0x010408d2,
|
||||
0x00e8, 0x00000000,
|
||||
0x00ec, 0x00000000,
|
||||
0x00f4, 0x00005fff,
|
||||
0x00f8, 0x00000000,
|
||||
0x00fc, 0x00000000,
|
||||
0x0100, 0x00000000,
|
||||
0x0104, 0x00000000,
|
||||
0x0108, 0x00000000,
|
||||
0x010c, 0x02000000,
|
||||
0x0110, 0x00000000,
|
||||
0x0114, 0x00000000,
|
||||
0x0118, 0xe6447800,
|
||||
0x011c, 0x78000000,
|
||||
0x0120, 0x010408d2,
|
||||
0x0124, 0x00000000,
|
||||
0x0128, 0x00000000,
|
||||
0x0130, 0x00005fff,
|
||||
0x0134, 0x00000000,
|
||||
0x0138, 0x00000000,
|
||||
0x013c, 0x00000000,
|
||||
0x0140, 0x00000000,
|
||||
0x0144, 0x00000000,
|
||||
0x0148, 0x02000000,
|
||||
0x014c, 0x00000000,
|
||||
0x0150, 0x00000000,
|
||||
0x0154, 0xe6447800,
|
||||
0x0158, 0x78000000,
|
||||
0x015c, 0x010408d2,
|
||||
0x0160, 0x00000000,
|
||||
0x0164, 0x00000000,
|
||||
0x016c, 0x00005fff,
|
||||
0x0170, 0x00000000,
|
||||
0x0174, 0x00000000,
|
||||
0x0178, 0x00000000,
|
||||
0x017c, 0x00000000,
|
||||
0x0180, 0x00000000,
|
||||
0x0184, 0x02000000,
|
||||
0x0188, 0x00000000,
|
||||
0x018c, 0x00000000,
|
||||
0x0190, 0xe6447800,
|
||||
0x0194, 0x78000000,
|
||||
0x0198, 0x010408d2,
|
||||
0x019c, 0x00000000,
|
||||
0x01a0, 0x00000000,
|
||||
0x01a8, 0x00005fff,
|
||||
0x01ac, 0x00000000,
|
||||
0x01b0, 0x00000000,
|
||||
0x01b4, 0x00000000,
|
||||
0x01b8, 0x00000000,
|
||||
0x01bc, 0x00000000,
|
||||
0x01c0, 0x02000000,
|
||||
0x01c4, 0x00000000,
|
||||
0x01c8, 0x00000000,
|
||||
0x01cc, 0xe6407800,
|
||||
0x01d0, 0x78000000,
|
||||
0x01d4, 0x010408d2,
|
||||
0x01d8, 0x00000000,
|
||||
0x01dc, 0x00000000,
|
||||
0x01e4, 0x00005fff,
|
||||
0x01e8, 0x00000000,
|
||||
0x01ec, 0x00000000,
|
||||
0x01f0, 0x00000000,
|
||||
0x01f4, 0x00000000,
|
||||
0x01f8, 0x00000000,
|
||||
0x01fc, 0x02000000,
|
||||
0x0200, 0x00000000,
|
||||
0x0204, 0x00000000,
|
||||
0x0208, 0x00000008,
|
||||
0x020c, 0x0000000d,
|
||||
0x41fc, 0x00000000,
|
||||
0x4400, 0x00000000,
|
||||
0x4410, 0x00000000,
|
||||
0x4420, 0x00000000,
|
||||
0x4430, 0x00000000,
|
||||
0x4440, 0x00000000,
|
||||
0x4450, 0x00000000,
|
||||
0x4460, 0x00000000,
|
||||
0x4470, 0x00000000,
|
||||
0xf080, 0x00003018,
|
||||
0xf084, 0x00000fff,
|
||||
0xf800, 0x00000000,
|
||||
0xf804, 0x00002e00,
|
||||
0xf8d0, 0x00000001,
|
||||
0xf8d4, 0x00000000,
|
||||
0xff00, 0x00000301,
|
||||
0xff0c, 0x01000000,
|
||||
0xffe0, 0x00000000,
|
||||
0xfff4, 0x00004011,
|
||||
0x0090, 0x00000000,
|
||||
0x0094, 0x00000000,
|
||||
0x0098, 0x00000000,
|
||||
0x009c, 0x3f3f3f3f,
|
||||
};
|
||||
#endif
|
||||
350
include/linux/input/aw9610x_reg.h
Normal file
350
include/linux/input/aw9610x_reg.h
Normal file
|
|
@ -0,0 +1,350 @@
|
|||
#ifndef _AW9610X_REG_H_
|
||||
#define _AW9610X_REG_H_
|
||||
|
||||
/********************************************
|
||||
* Register List
|
||||
********************************************/
|
||||
#define REG_SCANCTRL0 0x0000
|
||||
#define REG_SCANCTRL1 0x0004
|
||||
#define REG_SCANCTRL2 0x0008
|
||||
#define REG_SCANCTRL3 0x000C
|
||||
#define REG_AFECFG0_CH0 0x0010
|
||||
#define REG_AFECFG1_CH0 0x0014
|
||||
#define REG_AFECFG2_CH0 0x0018
|
||||
#define REG_AFECFG3_CH0 0x001C
|
||||
#define REG_AFECFG4_CH0 0x0020
|
||||
#define REG_AFECFG0_CH1 0x0024
|
||||
#define REG_AFECFG1_CH1 0x0028
|
||||
#define REG_AFECFG2_CH1 0x002C
|
||||
#define REG_AFECFG3_CH1 0x0030
|
||||
#define REG_AFECFG4_CH1 0x0034
|
||||
#define REG_AFECFG0_CH2 0x0038
|
||||
#define REG_AFECFG1_CH2 0x003C
|
||||
#define REG_AFECFG2_CH2 0x0040
|
||||
#define REG_AFECFG3_CH2 0x0044
|
||||
#define REG_AFECFG4_CH2 0x0048
|
||||
#define REG_AFECFG0_CH3 0x004C
|
||||
#define REG_AFECFG1_CH3 0x0050
|
||||
#define REG_AFECFG2_CH3 0x0054
|
||||
#define REG_AFECFG3_CH3 0x0058
|
||||
#define REG_AFECFG4_CH3 0x005C
|
||||
#define REG_AFECFG0_CH4 0x0060
|
||||
#define REG_AFECFG1_CH4 0x0064
|
||||
#define REG_AFECFG2_CH4 0x0068
|
||||
#define REG_AFECFG3_CH4 0x006C
|
||||
#define REG_AFECFG4_CH4 0x0070
|
||||
#define REG_AFECFG0_CH5 0x0074
|
||||
#define REG_AFECFG1_CH5 0x0078
|
||||
#define REG_AFECFG2_CH5 0x007C
|
||||
#define REG_AFECFG3_CH5 0x0080
|
||||
#define REG_AFECFG4_CH5 0x0084
|
||||
#define REG_FIRMVERSION 0x0088
|
||||
#define REG_STAT0 0x0090
|
||||
#define REG_STAT1 0x0094
|
||||
#define REG_STAT2 0x0098
|
||||
#define REG_PROXINTEN 0x009C
|
||||
#define REG_FILTREF0_CH0 0x00A0
|
||||
#define REG_FILTREF1_CH0 0x00A4
|
||||
#define REG_BLFILT1_CH0 0x00A8
|
||||
#define REG_BLFILT2_CH0 0x00AC
|
||||
#define REG_PROXCTRL_CH0 0x00B0
|
||||
#define REG_PROXTH0_CH0 0x00B8
|
||||
#define REG_PROXTH1_CH0 0x00BC
|
||||
#define REG_PROXTH2_CH0 0x00C0
|
||||
#define REG_PROXTH3_CH0 0x00C4
|
||||
#define REG_STDDET_CH0 0x00C8
|
||||
#define REG_INITPROX0_CH0 0x00CC
|
||||
#define REG_INITPROX1_CH0 0x00D0
|
||||
#define REG_DATAOFFSET_CH0 0x00D4
|
||||
#define REG_CORRTARDATA_CH0 0x00D8
|
||||
#define REG_FILTREF0_CH1 0x00DC
|
||||
#define REG_FILTREF1_CH1 0x00E0
|
||||
#define REG_BLFILT1_CH1 0x00E4
|
||||
#define REG_BLFILT2_CH1 0x00E8
|
||||
#define REG_PROXCTRL_CH1 0x00EC
|
||||
#define REG_PROXTH0_CH1 0x00F4
|
||||
#define REG_PROXTH1_CH1 0x00F8
|
||||
#define REG_PROXTH2_CH1 0x00FC
|
||||
#define REG_PROXTH3_CH1 0x0100
|
||||
#define REG_STDDET_CH1 0x0104
|
||||
#define REG_INITPROX0_CH1 0x0108
|
||||
#define REG_INITPROX1_CH1 0x010C
|
||||
#define REG_DATAOFFSET_CH1 0x0110
|
||||
#define REG_CORRTARDATA_CH1 0x0114
|
||||
#define REG_FILTREF0_CH2 0x0118
|
||||
#define REG_FILTREF1_CH2 0x011C
|
||||
#define REG_BLFILT1_CH2 0x0120
|
||||
#define REG_BLFILT2_CH2 0x0124
|
||||
#define REG_PROXCTRL_CH2 0x0128
|
||||
#define REG_PROXTH0_CH2 0x0130
|
||||
#define REG_PROXTH1_CH2 0x0134
|
||||
#define REG_PROXTH2_CH2 0x0138
|
||||
#define REG_PROXTH3_CH2 0x013C
|
||||
#define REG_STDDET_CH2 0x0140
|
||||
#define REG_INITPROX0_CH2 0x0144
|
||||
#define REG_INITPROX1_CH2 0x0148
|
||||
#define REG_DATAOFFSET_CH2 0x014C
|
||||
#define REG_BASELINE_CH2 0x0150
|
||||
#define REG_FILTREF0_CH3 0x0154
|
||||
#define REG_FILTREF1_CH3 0x0158
|
||||
#define REG_BLFILT1_CH3 0x015C
|
||||
#define REG_BLFILT2_CH3 0x0160
|
||||
#define REG_PROXCTRL_CH3 0x0164
|
||||
#define REG_PROXTH0_CH3 0x016C
|
||||
#define REG_PROXTH1_CH3 0x0170
|
||||
#define REG_PROXTH2_CH3 0x0174
|
||||
#define REG_PROXTH3_CH3 0x0178
|
||||
#define REG_STDDET_CH3 0x017C
|
||||
#define REG_INITPROX0_CH3 0x0180
|
||||
#define REG_INITPROX1_CH3 0x0184
|
||||
#define REG_DATAOFFSET_CH3 0x0188
|
||||
#define REG_CORRTARDATA_CH3 0x018C
|
||||
#define REG_FILTREF0_CH4 0x0190
|
||||
#define REG_FILTREF1_CH4 0x0194
|
||||
#define REG_BLFILT1_CH4 0x0198
|
||||
#define REG_BLFILT2_CH4 0x019C
|
||||
#define REG_PROXCTRL_CH4 0x01A0
|
||||
#define REG_PROXTH0_CH4 0x01A8
|
||||
#define REG_PROXTH1_CH4 0x01AC
|
||||
#define REG_PROXTH2_CH4 0x01B0
|
||||
#define REG_PROXTH3_CH4 0x01B4
|
||||
#define REG_STDDET_CH4 0x01B8
|
||||
#define REG_INITPROX0_CH4 0x01BC
|
||||
#define REG_INITPROX1_CH4 0x01C0
|
||||
#define REG_DATAOFFSET_CH4 0x01C4
|
||||
#define REG_CORRTARDATA_CH4 0x01C8
|
||||
#define REG_FILTREF0_CH5 0x01CC
|
||||
#define REG_FILTREF1_CH5 0x01D0
|
||||
#define REG_BLFILT1_CH5 0x01D4
|
||||
#define REG_BLFILT2_CH5 0x01D8
|
||||
#define REG_PROXCTRL_CH5 0x01DC
|
||||
#define REG_PROXTH0_CH5 0x01E4
|
||||
#define REG_PROXTH1_CH5 0x01E8
|
||||
#define REG_PROXTH2_CH5 0x01EC
|
||||
#define REG_PROXTH3_CH5 0x01F0
|
||||
#define REG_STDDET_CH5 0x01F4
|
||||
#define REG_INITPROX0_CH5 0x01F8
|
||||
#define REG_INITPROX1_CH5 0x01FC
|
||||
#define REG_DATAOFFSET_CH5 0x0200
|
||||
#define REG_CORRTARDATA_CH5 0x0204
|
||||
#define REG_REFACFG 0x0208
|
||||
#define REG_REFBCFG 0x020C
|
||||
#define REG_VALID_CH0 0x0210
|
||||
#define REG_VALID_CH1 0x0214
|
||||
#define REG_VALID_CH2 0x0218
|
||||
#define REG_VALID_CH3 0x021C
|
||||
#define REG_VALID_CH4 0x0220
|
||||
#define REG_VALID_CH5 0x0224
|
||||
#define REG_BASELINE_CH0 0x0228
|
||||
#define REG_DIFF_CH0 0x0240
|
||||
#define REG_AMID_CH0 0x0258
|
||||
#define REG_AMAD_CH0 0x0270
|
||||
#define REG_AAMD_CH0 0x0288
|
||||
#define REG_SMID_CH0 0x02A0
|
||||
#define REG_SMAD_CH0 0x02B8
|
||||
#define REG_RAW_CH0 0x02D0
|
||||
#define REG_LOPT_CH0 0x02E8
|
||||
#define REG_VAPD_CH0 0x0300
|
||||
#define REG_VADD_CH0 0x0318
|
||||
#define REG_PSCBD_CH0 0x0330
|
||||
#define REG_AFD_CH0 0x0348
|
||||
#define REG_EEDA0 0x0408
|
||||
#define REG_EEDA1 0x040C
|
||||
#define REG_DARE 0x41FC
|
||||
#define REG_DICR 0x4400
|
||||
#define REG_ITRE 0x4410
|
||||
#define REG_PUUC 0x4420
|
||||
#define REG_PUDN 0x4430
|
||||
#define REG_IEB 0x4440
|
||||
#define REG_PSR0 0x4450
|
||||
#define REG_PSR1 0x4460
|
||||
#define REG_CONRG 0x4470
|
||||
#define REG_CMD 0xF008
|
||||
#define REG_HOSTIRQSRC 0xF080
|
||||
#define REG_HOSTIRQEN 0xF084
|
||||
#define REG_MCR 0xF800
|
||||
#define REG_ACR 0xF804
|
||||
#define REG_HOSTCTRL1 0xFF00
|
||||
#define REG_HOSTCTRL2 0xFF0C
|
||||
#define REG_CHIP_ID 0xFF10
|
||||
#define REG_ATN 0xFFE0
|
||||
#define REG_HAAPEREN 0xFFF4
|
||||
/********************************************
|
||||
* Register Access
|
||||
*******************************************/
|
||||
#define REG_NONE_ACCESS 0
|
||||
#define REG_RD_ACCESS (1 << 0)
|
||||
#define REG_WR_ACCESS (1 << 1)
|
||||
|
||||
/**************************************
|
||||
* define platform data
|
||||
*
|
||||
**************************************/
|
||||
struct aw_reg_data {
|
||||
unsigned int reg;
|
||||
unsigned int val;
|
||||
unsigned char rw;
|
||||
};
|
||||
|
||||
static const struct aw_reg_data aw9610x_reg_access[] = {
|
||||
{.reg = REG_SCANCTRL0, .rw = REG_RD_ACCESS|REG_WR_ACCESS,},
|
||||
{.reg = REG_SCANCTRL1, .rw = REG_RD_ACCESS|REG_WR_ACCESS,},
|
||||
{.reg = REG_SCANCTRL2, .rw = REG_RD_ACCESS|REG_WR_ACCESS,},
|
||||
{.reg = REG_SCANCTRL3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG0_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG1_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG2_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG3_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG4_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG0_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG1_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG2_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG3_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG4_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG0_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG1_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG2_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG3_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG4_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG0_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG1_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG2_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG3_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG4_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG0_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG1_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG2_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG3_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG4_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG0_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG1_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG2_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG3_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_AFECFG4_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_STAT0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_STAT1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_STAT2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXINTEN, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF0_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF1_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT1_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT2_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXCTRL_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH0_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH1_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH2_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH3_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_STDDET_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX0_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX1_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_DATAOFFSET_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_CORRTARDATA_CH0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF0_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF1_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT1_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT2_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXCTRL_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH0_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH1_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH2_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH3_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_STDDET_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX0_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX1_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_DATAOFFSET_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_CORRTARDATA_CH1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF0_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF1_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT1_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT2_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXCTRL_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH0_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH1_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH2_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH3_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_STDDET_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX0_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX1_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_DATAOFFSET_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BASELINE_CH2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF0_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF1_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT1_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT2_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXCTRL_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH0_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH1_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH2_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH3_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_STDDET_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX0_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX1_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_DATAOFFSET_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_CORRTARDATA_CH3, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF0_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF1_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT1_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT2_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXCTRL_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH0_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH1_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH2_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH3_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_STDDET_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX0_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX1_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_DATAOFFSET_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_CORRTARDATA_CH4, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF0_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_FILTREF1_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT1_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_BLFILT2_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXCTRL_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH0_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH1_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH2_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PROXTH3_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_STDDET_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX0_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_INITPROX1_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_DATAOFFSET_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_CORRTARDATA_CH5, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_REFACFG, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_REFBCFG, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_VALID_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_BASELINE_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_DIFF_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_AMID_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_AMAD_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_AAMD_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_SMID_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_SMAD_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_RAW_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_LOPT_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_VAPD_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_VADD_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_PSCBD_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_AFD_CH0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_EEDA0, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_EEDA1, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_DARE, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_DICR, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_ITRE, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PUUC, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PUDN, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_IEB, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PSR0, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_PSR1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_CONRG, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_HOSTIRQSRC, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_HOSTIRQEN, .rw = REG_WR_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_MCR, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_ACR, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_HOSTCTRL1, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_HOSTCTRL2, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_CHIP_ID, .rw = REG_RD_ACCESS,},
|
||||
{.reg = REG_ATN, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
{.reg = REG_HAAPEREN, .rw = REG_RD_ACCESS | REG_WR_ACCESS,},
|
||||
};
|
||||
|
||||
#endif
|
||||
73
include/linux/input/aw_bin_parse.h
Normal file
73
include/linux/input/aw_bin_parse.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
#ifndef __AW_BIN_PARSE_H__
|
||||
#define __AW_BIN_PARSE_H__
|
||||
|
||||
#define NULL ((void *)0)
|
||||
#define GET_32_DATA(w, x, y, z) ((unsigned int)(((w) << 24) | ((x) << 16) | ((y) << 8) | (z)))
|
||||
#define BIN_NUM_MAX 100
|
||||
#define HEADER_LEN 60
|
||||
/*********************************************************
|
||||
*
|
||||
* header information
|
||||
*
|
||||
********************************************************/
|
||||
enum bin_header_version_enum {
|
||||
HEADER_VERSION_1_0_0 = 0x01000000,
|
||||
};
|
||||
|
||||
enum data_type_enum {
|
||||
DATA_TYPE_REGISTER = 0x00000000,
|
||||
DATA_TYPE_DSP_REG = 0x00000010,
|
||||
DATA_TYPE_DSP_CFG = 0x00000011,
|
||||
DATA_TYPE_SOC_REG = 0x00000020,
|
||||
DATA_TYPE_SOC_APP = 0x00000021,
|
||||
DATA_TYPE_MULTI_BINS = 0x00002000,
|
||||
};
|
||||
|
||||
enum data_version_enum {
|
||||
DATA_VERSION_V1 = 0X00000001, /*default little edian */
|
||||
DATA_VERSION_MAX,
|
||||
};
|
||||
|
||||
struct bin_header_info {
|
||||
unsigned int header_len; /* Frame header length */
|
||||
unsigned int check_sum; /* Frame header information-Checksum */
|
||||
unsigned int header_ver; /* Frame header information-Frame header version */
|
||||
unsigned int bin_data_type; /* Frame header information-Data type */
|
||||
unsigned int bin_data_ver; /* Frame header information-Data version */
|
||||
unsigned int bin_data_len; /* Frame header information-Data length */
|
||||
unsigned int ui_ver; /* Frame header information-ui version */
|
||||
unsigned char chip_type[20]; /* Frame header information-chip type */
|
||||
unsigned int reg_byte_len; /* Frame header information-reg byte len */
|
||||
unsigned int data_byte_len; /* Frame header information-data byte len */
|
||||
unsigned int device_addr; /* Frame header information-device addr */
|
||||
unsigned int valid_data_len; /* Length of valid data obtained after parsing */
|
||||
unsigned int valid_data_addr; /* The offset address of the valid data obtained after parsing relative to info */
|
||||
|
||||
unsigned int reg_num; /* The number of registers obtained after parsing */
|
||||
unsigned int reg_data_byte_len; /* The byte length of the register obtained after parsing */
|
||||
unsigned int download_addr; /* The starting address or download address obtained after parsing */
|
||||
unsigned int app_version; /* The software version number obtained after parsing */
|
||||
};
|
||||
|
||||
/************************************************************
|
||||
*
|
||||
* function define
|
||||
*
|
||||
************************************************************/
|
||||
struct bin_container {
|
||||
unsigned int len; /* The size of the bin file obtained from the firmware */
|
||||
unsigned char data[]; /* Store the bin file obtained from the firmware */
|
||||
};
|
||||
|
||||
struct aw_bin {
|
||||
char *p_addr; /* Offset pointer (backward offset pointer to obtain frame header information and important information) */
|
||||
unsigned int all_bin_parse_num; /* The number of all bin files */
|
||||
unsigned int multi_bin_parse_num; /* The number of single bin files */
|
||||
unsigned int single_bin_parse_num; /* The number of multiple bin files */
|
||||
struct bin_header_info header_info[BIN_NUM_MAX]; /* Frame header information and other important data obtained after parsing */
|
||||
struct bin_container info; /* Obtained bin file data that needs to be parsed */
|
||||
};
|
||||
|
||||
extern int aw_parsing_bin_file(struct aw_bin *bin);
|
||||
int aw_parse_bin_header_1_0_0(struct aw_bin *bin);
|
||||
#endif
|
||||
Loading…
Reference in a new issue