From 32b6752f387db7144c643020178113d20a1069df Mon Sep 17 00:00:00 2001
From: Faiyaz Mohammed <faiyazm@qti.qualcomm.com>
Date: Fri, 12 Jun 2020 12:43:10 +0530
Subject: [PATCH] ARM: dts: msm: Updates actlr settings for Shima

Update actlr settings for gfx and apps smmu for Shima, inline
with smmu hsr.

Change-Id: I4f11da907f8485998fac02a479b16340729798e3
---
 qcom/msm-arm-smmu-shima.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/qcom/msm-arm-smmu-shima.dtsi b/qcom/msm-arm-smmu-shima.dtsi
index ac4a803495ab..2b9b7cac3165 100644
--- a/qcom/msm-arm-smmu-shima.dtsi
+++ b/qcom/msm-arm-smmu-shima.dtsi
@@ -27,6 +27,11 @@
 				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
 
+		qcom,actlr =
+			/* All CBs of GFX: +15 deep PF */
+			<0x0 0x3ff 0x32B>,
+			<0x400 0x3ff 0x32B>;
+
 		gfx_0_tbu: gfx_0_tbu@3dc5000 {
 			compatible = "qcom,qsmmuv500-tbu";
 			reg = <0x3DC5000 0x1000>,
@@ -141,6 +146,16 @@
 				<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
 
+		qcom,actlr =
+			/* For Camera: +3 deep PF */
+			<0x1000 0x3ff 0x103>,
+			<0x1400 0x3ff 0x103>,
+			<0x2800 0x4ff 0x103>,
+			/* For Video: +3 deep PF*/
+			<0x2900 0x43f 0x103>,
+			/* For Compute: +15 deep PF */
+			<0x2960 0x40f 0x303>;
+
 		anoc_1_tbu: anoc_1_tbu@15185000 {
 			compatible = "qcom,qsmmuv500-tbu";
 			reg = <0x15185000 0x1000>,