From 2f8632e5758758c1051040898c328bc4e8fd7f4b Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Thu, 22 Oct 2020 14:28:25 +0800 Subject: [PATCH] ARM: dts: msm: Add cti trigger number to device tree for shima Add cti trigger number to device tree for shima. Since some platforms don't have swao cti, replace configuring cti trigger number as hard code. Change-Id: I52d53848cf23d25b8b8f5dc2ed6bb6175743d3d8 --- qcom/shima-coresight.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/shima-coresight.dtsi b/qcom/shima-coresight.dtsi index e6b90830fa55..4536aeb7d154 100644 --- a/qcom/shima-coresight.dtsi +++ b/qcom/shima-coresight.dtsi @@ -107,7 +107,9 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0_swao &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -154,7 +156,9 @@ qcom,sw-usb; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0 &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <3>; coresight-csr = <&csr>; clocks = <&aopcc QDSS_CLK>;