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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add support for CPUFREQ-HW for Shima
Add cpu frequency node to be able to scale the CPU frequency. Change-Id: I21ac437145c6481c41f00ffcab30afbb7b0a7906
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2 changed files with 28 additions and 0 deletions
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@ -107,3 +107,7 @@
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compatible = "qcom,dummycc";
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clock-output-names = "qdss_clocks";
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};
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&cpufreq_hw {
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clocks = <&bi_tcxo>, <&gcc 0>;
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};
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@ -36,6 +36,7 @@
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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@ -57,6 +58,7 @@
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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@ -73,6 +75,7 @@
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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@ -89,6 +92,7 @@
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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@ -105,6 +109,7 @@
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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capacity-dmips-mhz = <1946>;
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dynamic-power-coefficient = <520>;
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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@ -121,6 +126,7 @@
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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capacity-dmips-mhz = <1946>;
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dynamic-power-coefficient = <520>;
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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@ -137,6 +143,7 @@
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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capacity-dmips-mhz = <1946>;
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dynamic-power-coefficient = <520>;
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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@ -153,6 +160,7 @@
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 2 4>;
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capacity-dmips-mhz = <1946>;
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dynamic-power-coefficient = <552>;
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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@ -645,6 +653,22 @@
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#reset-cells = <1>;
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};
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cpufreq_hw: qcom,cpufreq-hw {
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compatible = "qcom,cpufreq-hw-epss";
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reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
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<0x18593000 0x1000>;
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reg-names = "freq-domain0", "freq-domain1",
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"freq-domain2";
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
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clock-names = "xo", "alternate";
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qcom,lut-row-size = <4>;
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qcom,skip-enable-check;
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#freq-domain-cells = <2>;
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};
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ipcc_mproc: qcom,ipcc@408000 {
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compatible = "qcom,ipcc";
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reg = <0x408000 0x1000>;
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