From 7eabddbe9cf863adbd3eb1de28191ae73e0fb5a2 Mon Sep 17 00:00:00 2001
From: David Dai <davidai@quicinc.com>
Date: Thu, 13 Jun 2019 16:07:25 -0700
Subject: [PATCH 1/2] dt-bindings: clocks: add dummycc bindings

Add dummycc device bindings. These devices are used to reference
clock controllers and emulate clock operations.

Change-Id: Icf6464f85374d7969b24e19ae458a245125b7f88
---
 bindings/clock/qcom,dummycc.txt | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 bindings/clock/qcom,dummycc.txt

diff --git a/bindings/clock/qcom,dummycc.txt b/bindings/clock/qcom,dummycc.txt
new file mode 100644
index 000000000000..9463fb6b7f57
--- /dev/null
+++ b/bindings/clock/qcom,dummycc.txt
@@ -0,0 +1,26 @@
+Qualcomm Technologies, Inc. Dummy Clock Controller Binding
+
+Qualcomm Technologies, Inc. dummy clock controller devices provide
+clock API support for driver development during pre-silicon stage.
+The clock driver always returns a dummy clock that has no effect on
+hardware.
+
+Required properties:
+- compatible:		Must be "qcom,dummycc"
+- #clock-cells:		Must be <1>. This will allow the common clock device
+			tree framework to recognize _this_ device node as a
+			clock provider.
+
+Optional properties:
+- clock-output-names:	Name of the clock or the clock type.
+- #reset-cells:		Must be <1>. This will allow the common reset device
+			tree framework to recognize _this_ device node as a
+			reset controller provider.
+
+Example:
+	clock_gcc: qcom,gcc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};

From 7536ddc0451d06c9faf607cde784239ba2c77cdd Mon Sep 17 00:00:00 2001
From: David Dai <davidai@quicinc.com>
Date: Wed, 19 Jun 2019 12:19:51 -0700
Subject: [PATCH 2/2] ARM: dts: msm: add stub clock devices for Lahaina

Add stub clock devices for rpmh, aop, gcc, videocc, camcc, dispcc
and gpucc clock controllers on the Lahaina SoC.  This allows consumers
to reference dummy clocks until full functionality is in place.

Change-Id: Idd7c45aaa301cd0688c4f7ca59ddfe3447bf996e
---
 qcom/lahaina.dtsi | 87 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 87 insertions(+)

diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index 35ec64303b18..733aae9d850e 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -1,3 +1,10 @@
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,camcc-lahaina.h>
+#include <dt-bindings/clock/qcom,dispcc-lahaina.h>
+#include <dt-bindings/clock/qcom,gcc-lahaina.h>
+#include <dt-bindings/clock/qcom,gpucc-lahaina.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,videocc-lahaina.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "lahaina-regulators.dtsi"
@@ -283,4 +290,84 @@
 			status = "disabled";
 		};
 	};
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <38400000>;
+			clock-output-names = "xo_board";
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32764>;
+		};
+	};
+
+	cxo: bi_tcxo {
+		compatible = "fixed-factor-clock";
+		clocks = <&xo_board>;
+		clock-mult = <1>;
+		clock-div = <2>;
+		#clock-cells = <0>;
+		clock-output-names = "bi_tcxo";
+	};
+
+	cxo_a: bi_tcxo_ao {
+		compatible = "fixed-factor-clock";
+		clocks = <&xo_board>;
+		clock-mult = <1>;
+		clock-div = <2>;
+		#clock-cells = <0>;
+		clock-output-names = "bi_tcxo_ao";
+	};
+
+	clock_rpmh: qcom,rpmhclk {
+		compatible = "qcom,dummycc";
+		clock-output-names = "rpmh_clocks";
+		#clock-cells = <1>;
+	};
+
+	clock_aop: qcom,aopclk {
+		compatible = "qcom,dummycc";
+		clock-output-names = "qdss_clocks";
+		#clock-cells = <1>;
+	};
+
+	clock_gcc: qcom,gcc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	clock_videocc: qcom,videocc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "videocc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	clock_camcc: qcom,camcc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "camcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	clock_dispcc: qcom,dispcc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "dispcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	clock_gpucc: qcom,gpucc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gpucc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
 };