mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (26 commits) sh: Convert sh to use read/update_persistent_clock sh: Move PMB debugfs entry initialization to later stage sh: Fix up flush_cache_vmap() on SMP. sh: fix up MMU reset with variable PMB mapping sizes. sh: establish PMB mappings for NUMA nodes. sh: check for existing mappings for bolted PMB entries. sh: fixed virt/phys mapping helpers for PMB. sh: make pmb iomapping configurable. sh: reworked dynamic PMB mapping. sh: Fix up cpumask_of_pcibus() for the NUMA build. serial: sh-sci: Tidy up build warnings. sh: Fix up ctrl_read/write stragglers in migor setup. serial: sh-sci: Add DMA support. dmaengine: shdma: extend .device_terminate_all() to record partial transfer sh: merge sh7722 and sh7724 DMA register definitions sh: activate runtime PM for dmaengine on sh7722 and sh7724 dmaengine: shdma: add runtime PM support. dmaengine: shdma: separate DMA headers. dmaengine: shdma: convert to platform device resources dmaengine: shdma: fix DMA error handling. ...
This commit is contained in:
Linus Torvalds
commit
4a31c08d2f
35 changed files with 2201 additions and 728 deletions
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@ -24,8 +24,10 @@
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <cpu/dma.h>
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#include <asm/dma-sh.h>
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#include <linux/pm_runtime.h>
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#include <asm/dmaengine.h>
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#include "shdma.h"
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/* DMA descriptor control */
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@ -38,30 +40,32 @@ enum sh_dmae_desc_status {
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};
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#define NR_DESCS_PER_CHANNEL 32
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/*
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* Define the default configuration for dual address memory-memory transfer.
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* The 0x400 value represents auto-request, external->external.
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*
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* And this driver set 4byte burst mode.
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* If you want to change mode, you need to change RS_DEFAULT of value.
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* (ex 1byte burst mode -> (RS_DUAL & ~TS_32)
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*/
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#define RS_DEFAULT (RS_DUAL)
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/* Default MEMCPY transfer size = 2^2 = 4 bytes */
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#define LOG2_DEFAULT_XFER_SIZE 2
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/* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
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static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)];
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static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
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#define SH_DMAC_CHAN_BASE(id) (dma_base_addr[id])
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static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
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{
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ctrl_outl(data, SH_DMAC_CHAN_BASE(sh_dc->id) + reg);
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__raw_writel(data, sh_dc->base + reg / sizeof(u32));
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}
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static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
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{
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return ctrl_inl(SH_DMAC_CHAN_BASE(sh_dc->id) + reg);
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return __raw_readl(sh_dc->base + reg / sizeof(u32));
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}
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static u16 dmaor_read(struct sh_dmae_device *shdev)
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{
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return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
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}
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static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
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{
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__raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
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}
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/*
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@ -69,24 +73,23 @@ static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
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*
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* SH7780 has two DMAOR register
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*/
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static void sh_dmae_ctl_stop(int id)
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static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
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{
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unsigned short dmaor = dmaor_read_reg(id);
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unsigned short dmaor = dmaor_read(shdev);
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dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
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dmaor_write_reg(id, dmaor);
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dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
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}
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static int sh_dmae_rst(int id)
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static int sh_dmae_rst(struct sh_dmae_device *shdev)
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{
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unsigned short dmaor;
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sh_dmae_ctl_stop(id);
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dmaor = dmaor_read_reg(id) | DMAOR_INIT;
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sh_dmae_ctl_stop(shdev);
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dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init;
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dmaor_write_reg(id, dmaor);
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if (dmaor_read_reg(id) & (DMAOR_AE | DMAOR_NMIF)) {
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pr_warning(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
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dmaor_write(shdev, dmaor);
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if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) {
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pr_warning("dma-sh: Can't initialize DMAOR.\n");
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return -EINVAL;
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}
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return 0;
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@ -102,13 +105,36 @@ static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
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return false; /* waiting */
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}
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static unsigned int ts_shift[] = TS_SHIFT;
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static inline unsigned int calc_xmit_shift(u32 chcr)
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static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
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{
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int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
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((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
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struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
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struct sh_dmae_device, common);
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struct sh_dmae_pdata *pdata = shdev->pdata;
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int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
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((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
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return ts_shift[cnt];
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if (cnt >= pdata->ts_shift_num)
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cnt = 0;
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return pdata->ts_shift[cnt];
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}
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static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
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{
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struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
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struct sh_dmae_device, common);
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struct sh_dmae_pdata *pdata = shdev->pdata;
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int i;
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for (i = 0; i < pdata->ts_shift_num; i++)
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if (pdata->ts_shift[i] == l2size)
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break;
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if (i == pdata->ts_shift_num)
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i = 0;
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return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
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((i << pdata->ts_high_shift) & pdata->ts_high_mask);
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}
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static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
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@ -136,8 +162,13 @@ static void dmae_halt(struct sh_dmae_chan *sh_chan)
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static void dmae_init(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = RS_DEFAULT; /* default is DUAL mode */
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sh_chan->xmit_shift = calc_xmit_shift(chcr);
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/*
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* Default configuration for dual address memory-memory transfer.
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* 0x400 represents auto-request.
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*/
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u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
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LOG2_DEFAULT_XFER_SIZE);
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sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
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sh_dmae_writel(sh_chan, chcr, CHCR);
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}
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@ -147,37 +178,26 @@ static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
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if (dmae_is_busy(sh_chan))
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return -EBUSY;
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sh_chan->xmit_shift = calc_xmit_shift(val);
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sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
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sh_dmae_writel(sh_chan, val, CHCR);
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return 0;
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}
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#define DMARS_SHIFT 8
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#define DMARS_CHAN_MSK 0x01
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static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
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{
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u32 addr;
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int shift = 0;
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struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
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struct sh_dmae_device, common);
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struct sh_dmae_pdata *pdata = shdev->pdata;
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struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
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u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16);
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int shift = chan_pdata->dmars_bit;
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if (dmae_is_busy(sh_chan))
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return -EBUSY;
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if (sh_chan->id & DMARS_CHAN_MSK)
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shift = DMARS_SHIFT;
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if (sh_chan->id < 6)
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/* DMA0RS0 - DMA0RS2 */
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addr = SH_DMARS_BASE0 + (sh_chan->id / 2) * 4;
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#ifdef SH_DMARS_BASE1
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else if (sh_chan->id < 12)
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/* DMA1RS0 - DMA1RS2 */
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addr = SH_DMARS_BASE1 + ((sh_chan->id - 6) / 2) * 4;
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#endif
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else
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return -EINVAL;
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ctrl_outw((val << shift) | (ctrl_inw(addr) & (0xFF00 >> shift)), addr);
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__raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
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addr);
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return 0;
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}
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@ -251,15 +271,15 @@ static struct sh_dmae_slave_config *sh_dmae_find_slave(
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struct dma_device *dma_dev = sh_chan->common.device;
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struct sh_dmae_device *shdev = container_of(dma_dev,
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struct sh_dmae_device, common);
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struct sh_dmae_pdata *pdata = &shdev->pdata;
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struct sh_dmae_pdata *pdata = shdev->pdata;
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int i;
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if ((unsigned)slave_id >= SHDMA_SLAVE_NUMBER)
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return NULL;
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for (i = 0; i < pdata->config_num; i++)
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if (pdata->config[i].slave_id == slave_id)
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return pdata->config + i;
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for (i = 0; i < pdata->slave_num; i++)
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if (pdata->slave[i].slave_id == slave_id)
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return pdata->slave + i;
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return NULL;
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}
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@ -270,6 +290,8 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
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struct sh_desc *desc;
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struct sh_dmae_slave *param = chan->private;
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pm_runtime_get_sync(sh_chan->dev);
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/*
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* This relies on the guarantee from dmaengine that alloc_chan_resources
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* never runs concurrently with itself or free_chan_resources.
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@ -288,9 +310,8 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
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dmae_set_dmars(sh_chan, cfg->mid_rid);
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dmae_set_chcr(sh_chan, cfg->chcr);
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} else {
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if ((sh_dmae_readl(sh_chan, CHCR) & 0x700) != 0x400)
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dmae_set_chcr(sh_chan, RS_DEFAULT);
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} else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) {
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dmae_init(sh_chan);
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}
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spin_lock_bh(&sh_chan->desc_lock);
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@ -312,6 +333,9 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
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}
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spin_unlock_bh(&sh_chan->desc_lock);
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if (!sh_chan->descs_allocated)
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pm_runtime_put(sh_chan->dev);
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return sh_chan->descs_allocated;
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}
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@ -323,6 +347,7 @@ static void sh_dmae_free_chan_resources(struct dma_chan *chan)
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struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
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struct sh_desc *desc, *_desc;
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LIST_HEAD(list);
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int descs = sh_chan->descs_allocated;
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dmae_halt(sh_chan);
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@ -343,6 +368,9 @@ static void sh_dmae_free_chan_resources(struct dma_chan *chan)
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spin_unlock_bh(&sh_chan->desc_lock);
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if (descs > 0)
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pm_runtime_put(sh_chan->dev);
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list_for_each_entry_safe(desc, _desc, &list, node)
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kfree(desc);
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}
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@ -559,6 +587,19 @@ static void sh_dmae_terminate_all(struct dma_chan *chan)
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if (!chan)
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return;
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dmae_halt(sh_chan);
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spin_lock_bh(&sh_chan->desc_lock);
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if (!list_empty(&sh_chan->ld_queue)) {
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/* Record partial transfer */
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struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
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struct sh_desc, node);
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desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
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sh_chan->xmit_shift;
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}
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spin_unlock_bh(&sh_chan->desc_lock);
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sh_dmae_chan_ld_cleanup(sh_chan, true);
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}
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|
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@ -661,7 +702,7 @@ static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
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static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
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{
|
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struct sh_desc *sd;
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struct sh_desc *desc;
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|
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spin_lock_bh(&sh_chan->desc_lock);
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/* DMA work check */
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|
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@ -671,10 +712,13 @@ static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
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}
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/* Find the first not transferred desciptor */
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list_for_each_entry(sd, &sh_chan->ld_queue, node)
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if (sd->mark == DESC_SUBMITTED) {
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list_for_each_entry(desc, &sh_chan->ld_queue, node)
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if (desc->mark == DESC_SUBMITTED) {
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dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
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desc->async_tx.cookie, sh_chan->id,
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desc->hw.tcr, desc->hw.sar, desc->hw.dar);
|
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/* Get the ld start address from ld_queue */
|
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dmae_set_reg(sh_chan, &sd->hw);
|
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dmae_set_reg(sh_chan, &desc->hw);
|
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dmae_start(sh_chan);
|
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break;
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}
|
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|
|
@ -696,6 +740,7 @@ static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
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struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
|
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dma_cookie_t last_used;
|
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dma_cookie_t last_complete;
|
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enum dma_status status;
|
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|
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sh_dmae_chan_ld_cleanup(sh_chan, false);
|
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|
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|
|
@ -709,7 +754,27 @@ static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
|
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if (used)
|
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*used = last_used;
|
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|
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return dma_async_is_complete(cookie, last_complete, last_used);
|
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spin_lock_bh(&sh_chan->desc_lock);
|
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|
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status = dma_async_is_complete(cookie, last_complete, last_used);
|
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|
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/*
|
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* If we don't find cookie on the queue, it has been aborted and we have
|
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* to report error
|
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*/
|
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if (status != DMA_SUCCESS) {
|
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struct sh_desc *desc;
|
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status = DMA_ERROR;
|
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list_for_each_entry(desc, &sh_chan->ld_queue, node)
|
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if (desc->cookie == cookie) {
|
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status = DMA_IN_PROGRESS;
|
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break;
|
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}
|
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}
|
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|
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spin_unlock_bh(&sh_chan->desc_lock);
|
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|
||||
return status;
|
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}
|
||||
|
||||
static irqreturn_t sh_dmae_interrupt(int irq, void *data)
|
||||
|
|
@ -732,40 +797,32 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data)
|
|||
#if defined(CONFIG_CPU_SH4)
|
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static irqreturn_t sh_dmae_err(int irq, void *data)
|
||||
{
|
||||
int err = 0;
|
||||
struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
|
||||
int i;
|
||||
|
||||
/* IRQ Multi */
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
int __maybe_unused cnt = 0;
|
||||
switch (irq) {
|
||||
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
|
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case DMTE6_IRQ:
|
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cnt++;
|
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#endif
|
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case DMTE0_IRQ:
|
||||
if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
|
||||
disable_irq(irq);
|
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return IRQ_HANDLED;
|
||||
/* halt the dma controller */
|
||||
sh_dmae_ctl_stop(shdev);
|
||||
|
||||
/* We cannot detect, which channel caused the error, have to reset all */
|
||||
for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
|
||||
struct sh_dmae_chan *sh_chan = shdev->chan[i];
|
||||
if (sh_chan) {
|
||||
struct sh_desc *desc;
|
||||
/* Stop the channel */
|
||||
dmae_halt(sh_chan);
|
||||
/* Complete all */
|
||||
list_for_each_entry(desc, &sh_chan->ld_queue, node) {
|
||||
struct dma_async_tx_descriptor *tx = &desc->async_tx;
|
||||
desc->mark = DESC_IDLE;
|
||||
if (tx->callback)
|
||||
tx->callback(tx->callback_param);
|
||||
}
|
||||
default:
|
||||
return IRQ_NONE;
|
||||
list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free);
|
||||
}
|
||||
} else {
|
||||
/* reset dma controller */
|
||||
err = sh_dmae_rst(0);
|
||||
if (err)
|
||||
return err;
|
||||
#ifdef SH_DMAC_BASE1
|
||||
if (shdev->pdata.mode & SHDMA_DMAOR1) {
|
||||
err = sh_dmae_rst(1);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
disable_irq(irq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
sh_dmae_rst(shdev);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -796,19 +853,12 @@ static void dmae_do_tasklet(unsigned long data)
|
|||
sh_dmae_chan_ld_cleanup(sh_chan, false);
|
||||
}
|
||||
|
||||
static unsigned int get_dmae_irq(unsigned int id)
|
||||
{
|
||||
unsigned int irq = 0;
|
||||
if (id < ARRAY_SIZE(dmte_irq_map))
|
||||
irq = dmte_irq_map[id];
|
||||
return irq;
|
||||
}
|
||||
|
||||
static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id)
|
||||
static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
|
||||
int irq, unsigned long flags)
|
||||
{
|
||||
int err;
|
||||
unsigned int irq = get_dmae_irq(id);
|
||||
unsigned long irqflags = IRQF_DISABLED;
|
||||
struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
|
||||
struct platform_device *pdev = to_platform_device(shdev->common.dev);
|
||||
struct sh_dmae_chan *new_sh_chan;
|
||||
|
||||
/* alloc channel */
|
||||
|
|
@ -819,8 +869,13 @@ static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id)
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* copy struct dma_device */
|
||||
new_sh_chan->common.device = &shdev->common;
|
||||
|
||||
new_sh_chan->dev = shdev->common.dev;
|
||||
new_sh_chan->id = id;
|
||||
new_sh_chan->irq = irq;
|
||||
new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
|
||||
|
||||
/* Init DMA tasklet */
|
||||
tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
|
||||
|
|
@ -835,29 +890,20 @@ static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id)
|
|||
INIT_LIST_HEAD(&new_sh_chan->ld_queue);
|
||||
INIT_LIST_HEAD(&new_sh_chan->ld_free);
|
||||
|
||||
/* copy struct dma_device */
|
||||
new_sh_chan->common.device = &shdev->common;
|
||||
|
||||
/* Add the channel to DMA device channel list */
|
||||
list_add_tail(&new_sh_chan->common.device_node,
|
||||
&shdev->common.channels);
|
||||
shdev->common.chancnt++;
|
||||
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
irqflags = IRQF_SHARED;
|
||||
#if defined(DMTE6_IRQ)
|
||||
if (irq >= DMTE6_IRQ)
|
||||
irq = DMTE6_IRQ;
|
||||
else
|
||||
#endif
|
||||
irq = DMTE0_IRQ;
|
||||
}
|
||||
|
||||
snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
|
||||
"sh-dmae%d", new_sh_chan->id);
|
||||
if (pdev->id >= 0)
|
||||
snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
|
||||
"sh-dmae%d.%d", pdev->id, new_sh_chan->id);
|
||||
else
|
||||
snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
|
||||
"sh-dma%d", new_sh_chan->id);
|
||||
|
||||
/* set up channel irq */
|
||||
err = request_irq(irq, &sh_dmae_interrupt, irqflags,
|
||||
err = request_irq(irq, &sh_dmae_interrupt, flags,
|
||||
new_sh_chan->dev_id, new_sh_chan);
|
||||
if (err) {
|
||||
dev_err(shdev->common.dev, "DMA channel %d request_irq error "
|
||||
|
|
@ -881,12 +927,12 @@ static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
|
|||
|
||||
for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
|
||||
if (shdev->chan[i]) {
|
||||
struct sh_dmae_chan *shchan = shdev->chan[i];
|
||||
if (!(shdev->pdata.mode & SHDMA_MIX_IRQ))
|
||||
free_irq(dmte_irq_map[i], shchan);
|
||||
struct sh_dmae_chan *sh_chan = shdev->chan[i];
|
||||
|
||||
list_del(&shchan->common.device_node);
|
||||
kfree(shchan);
|
||||
free_irq(sh_chan->irq, sh_chan);
|
||||
|
||||
list_del(&sh_chan->common.device_node);
|
||||
kfree(sh_chan);
|
||||
shdev->chan[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
|
@ -895,47 +941,84 @@ static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
|
|||
|
||||
static int __init sh_dmae_probe(struct platform_device *pdev)
|
||||
{
|
||||
int err = 0, cnt, ecnt;
|
||||
unsigned long irqflags = IRQF_DISABLED;
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
int eirq[] = { DMAE0_IRQ,
|
||||
#if defined(DMAE1_IRQ)
|
||||
DMAE1_IRQ
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
|
||||
unsigned long irqflags = IRQF_DISABLED,
|
||||
chan_flag[SH_DMAC_MAX_CHANNELS] = {};
|
||||
int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
|
||||
int err, i, irq_cnt = 0, irqres = 0;
|
||||
struct sh_dmae_device *shdev;
|
||||
struct resource *chan, *dmars, *errirq_res, *chanirq_res;
|
||||
|
||||
/* get platform data */
|
||||
if (!pdev->dev.platform_data)
|
||||
if (!pdata || !pdata->channel_num)
|
||||
return -ENODEV;
|
||||
|
||||
chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
/* DMARS area is optional, if absent, this controller cannot do slave DMA */
|
||||
dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
/*
|
||||
* IRQ resources:
|
||||
* 1. there always must be at least one IRQ IO-resource. On SH4 it is
|
||||
* the error IRQ, in which case it is the only IRQ in this resource:
|
||||
* start == end. If it is the only IRQ resource, all channels also
|
||||
* use the same IRQ.
|
||||
* 2. DMA channel IRQ resources can be specified one per resource or in
|
||||
* ranges (start != end)
|
||||
* 3. iff all events (channels and, optionally, error) on this
|
||||
* controller use the same IRQ, only one IRQ resource can be
|
||||
* specified, otherwise there must be one IRQ per channel, even if
|
||||
* some of them are equal
|
||||
* 4. if all IRQs on this controller are equal or if some specific IRQs
|
||||
* specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
|
||||
* requested with the IRQF_SHARED flag
|
||||
*/
|
||||
errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!chan || !errirq_res)
|
||||
return -ENODEV;
|
||||
|
||||
if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
|
||||
dev_err(&pdev->dev, "DMAC register region already claimed\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
|
||||
dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
|
||||
err = -EBUSY;
|
||||
goto ermrdmars;
|
||||
}
|
||||
|
||||
err = -ENOMEM;
|
||||
shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
|
||||
if (!shdev) {
|
||||
dev_err(&pdev->dev, "No enough memory\n");
|
||||
return -ENOMEM;
|
||||
dev_err(&pdev->dev, "Not enough memory\n");
|
||||
goto ealloc;
|
||||
}
|
||||
|
||||
shdev->chan_reg = ioremap(chan->start, resource_size(chan));
|
||||
if (!shdev->chan_reg)
|
||||
goto emapchan;
|
||||
if (dmars) {
|
||||
shdev->dmars = ioremap(dmars->start, resource_size(dmars));
|
||||
if (!shdev->dmars)
|
||||
goto emapdmars;
|
||||
}
|
||||
|
||||
/* platform data */
|
||||
memcpy(&shdev->pdata, pdev->dev.platform_data,
|
||||
sizeof(struct sh_dmae_pdata));
|
||||
shdev->pdata = pdata;
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
|
||||
/* reset dma controller */
|
||||
err = sh_dmae_rst(0);
|
||||
err = sh_dmae_rst(shdev);
|
||||
if (err)
|
||||
goto rst_err;
|
||||
|
||||
/* SH7780/85/23 has DMAOR1 */
|
||||
if (shdev->pdata.mode & SHDMA_DMAOR1) {
|
||||
err = sh_dmae_rst(1);
|
||||
if (err)
|
||||
goto rst_err;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&shdev->common.channels);
|
||||
|
||||
dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
|
||||
dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
|
||||
if (dmars)
|
||||
dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
|
||||
|
||||
shdev->common.device_alloc_chan_resources
|
||||
= sh_dmae_alloc_chan_resources;
|
||||
|
|
@ -950,37 +1033,72 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
|
|||
|
||||
shdev->common.dev = &pdev->dev;
|
||||
/* Default transfer size of 32 bytes requires 32-byte alignment */
|
||||
shdev->common.copy_align = 5;
|
||||
shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
|
||||
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
/* Non Mix IRQ mode SH7722/SH7730 etc... */
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
|
||||
|
||||
if (!chanirq_res)
|
||||
chanirq_res = errirq_res;
|
||||
else
|
||||
irqres++;
|
||||
|
||||
if (chanirq_res == errirq_res ||
|
||||
(errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
|
||||
irqflags = IRQF_SHARED;
|
||||
eirq[0] = DMTE0_IRQ;
|
||||
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
|
||||
eirq[1] = DMTE6_IRQ;
|
||||
#endif
|
||||
|
||||
errirq = errirq_res->start;
|
||||
|
||||
err = request_irq(errirq, sh_dmae_err, irqflags,
|
||||
"DMAC Address Error", shdev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev,
|
||||
"DMA failed requesting irq #%d, error %d\n",
|
||||
errirq, err);
|
||||
goto eirq_err;
|
||||
}
|
||||
|
||||
for (ecnt = 0 ; ecnt < ARRAY_SIZE(eirq); ecnt++) {
|
||||
err = request_irq(eirq[ecnt], sh_dmae_err, irqflags,
|
||||
"DMAC Address Error", shdev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "DMA device request_irq"
|
||||
"error (irq %d) with return %d\n",
|
||||
eirq[ecnt], err);
|
||||
goto eirq_err;
|
||||
}
|
||||
}
|
||||
#else
|
||||
chanirq_res = errirq_res;
|
||||
#endif /* CONFIG_CPU_SH4 */
|
||||
|
||||
if (chanirq_res->start == chanirq_res->end &&
|
||||
!platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
|
||||
/* Special case - all multiplexed */
|
||||
for (; irq_cnt < pdata->channel_num; irq_cnt++) {
|
||||
chan_irq[irq_cnt] = chanirq_res->start;
|
||||
chan_flag[irq_cnt] = IRQF_SHARED;
|
||||
}
|
||||
} else {
|
||||
do {
|
||||
for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
|
||||
if ((errirq_res->flags & IORESOURCE_BITS) ==
|
||||
IORESOURCE_IRQ_SHAREABLE)
|
||||
chan_flag[irq_cnt] = IRQF_SHARED;
|
||||
else
|
||||
chan_flag[irq_cnt] = IRQF_DISABLED;
|
||||
dev_dbg(&pdev->dev,
|
||||
"Found IRQ %d for channel %d\n",
|
||||
i, irq_cnt);
|
||||
chan_irq[irq_cnt++] = i;
|
||||
}
|
||||
chanirq_res = platform_get_resource(pdev,
|
||||
IORESOURCE_IRQ, ++irqres);
|
||||
} while (irq_cnt < pdata->channel_num && chanirq_res);
|
||||
}
|
||||
|
||||
if (irq_cnt < pdata->channel_num)
|
||||
goto eirqres;
|
||||
|
||||
/* Create DMA Channel */
|
||||
for (cnt = 0 ; cnt < MAX_DMA_CHANNELS ; cnt++) {
|
||||
err = sh_dmae_chan_probe(shdev, cnt);
|
||||
for (i = 0; i < pdata->channel_num; i++) {
|
||||
err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
|
||||
if (err)
|
||||
goto chan_probe_err;
|
||||
}
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
platform_set_drvdata(pdev, shdev);
|
||||
dma_async_device_register(&shdev->common);
|
||||
|
||||
|
|
@ -988,13 +1106,24 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
|
|||
|
||||
chan_probe_err:
|
||||
sh_dmae_chan_remove(shdev);
|
||||
|
||||
eirqres:
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
free_irq(errirq, shdev);
|
||||
eirq_err:
|
||||
for (ecnt-- ; ecnt >= 0; ecnt--)
|
||||
free_irq(eirq[ecnt], shdev);
|
||||
|
||||
#endif
|
||||
rst_err:
|
||||
pm_runtime_put(&pdev->dev);
|
||||
if (dmars)
|
||||
iounmap(shdev->dmars);
|
||||
emapdmars:
|
||||
iounmap(shdev->chan_reg);
|
||||
emapchan:
|
||||
kfree(shdev);
|
||||
ealloc:
|
||||
if (dmars)
|
||||
release_mem_region(dmars->start, resource_size(dmars));
|
||||
ermrdmars:
|
||||
release_mem_region(chan->start, resource_size(chan));
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
@ -1002,36 +1131,39 @@ rst_err:
|
|||
static int __exit sh_dmae_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
||||
struct resource *res;
|
||||
int errirq = platform_get_irq(pdev, 0);
|
||||
|
||||
dma_async_device_unregister(&shdev->common);
|
||||
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
free_irq(DMTE0_IRQ, shdev);
|
||||
#if defined(DMTE6_IRQ)
|
||||
free_irq(DMTE6_IRQ, shdev);
|
||||
#endif
|
||||
}
|
||||
if (errirq > 0)
|
||||
free_irq(errirq, shdev);
|
||||
|
||||
/* channel data remove */
|
||||
sh_dmae_chan_remove(shdev);
|
||||
|
||||
if (!(shdev->pdata.mode & SHDMA_MIX_IRQ)) {
|
||||
free_irq(DMAE0_IRQ, shdev);
|
||||
#if defined(DMAE1_IRQ)
|
||||
free_irq(DMAE1_IRQ, shdev);
|
||||
#endif
|
||||
}
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
if (shdev->dmars)
|
||||
iounmap(shdev->dmars);
|
||||
iounmap(shdev->chan_reg);
|
||||
|
||||
kfree(shdev);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (res)
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
if (res)
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_dmae_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
||||
sh_dmae_ctl_stop(0);
|
||||
if (shdev->pdata.mode & SHDMA_DMAOR1)
|
||||
sh_dmae_ctl_stop(1);
|
||||
sh_dmae_ctl_stop(shdev);
|
||||
}
|
||||
|
||||
static struct platform_driver sh_dmae_driver = {
|
||||
|
|
|
|||
|
|
@ -17,24 +17,10 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#include <asm/dmaengine.h>
|
||||
|
||||
#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
|
||||
|
||||
struct sh_dmae_regs {
|
||||
u32 sar; /* SAR / source address */
|
||||
u32 dar; /* DAR / destination address */
|
||||
u32 tcr; /* TCR / transfer count */
|
||||
};
|
||||
|
||||
struct sh_desc {
|
||||
struct sh_dmae_regs hw;
|
||||
struct list_head node;
|
||||
struct dma_async_tx_descriptor async_tx;
|
||||
enum dma_data_direction direction;
|
||||
dma_cookie_t cookie;
|
||||
int chunks;
|
||||
int mark;
|
||||
};
|
||||
|
||||
struct device;
|
||||
|
||||
struct sh_dmae_chan {
|
||||
|
|
@ -47,14 +33,18 @@ struct sh_dmae_chan {
|
|||
struct tasklet_struct tasklet; /* Tasklet */
|
||||
int descs_allocated; /* desc count */
|
||||
int xmit_shift; /* log_2(bytes_per_xfer) */
|
||||
int irq;
|
||||
int id; /* Raw id of this channel */
|
||||
u32 __iomem *base;
|
||||
char dev_id[16]; /* unique name per DMAC of channel */
|
||||
};
|
||||
|
||||
struct sh_dmae_device {
|
||||
struct dma_device common;
|
||||
struct sh_dmae_chan *chan[MAX_DMA_CHANNELS];
|
||||
struct sh_dmae_pdata pdata;
|
||||
struct sh_dmae_chan *chan[SH_DMAC_MAX_CHANNELS];
|
||||
struct sh_dmae_pdata *pdata;
|
||||
u32 __iomem *chan_reg;
|
||||
u16 __iomem *dmars;
|
||||
};
|
||||
|
||||
#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)
|
||||
|
|
|
|||
Loading…
Reference in a new issue