From 4a6ae6e0d86102a10ee2f10081e6fcbb05cd797a Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Mon, 25 Jul 2022 16:03:51 +0530 Subject: [PATCH] ARM: dts: qcom: Add support to disable PCIe halt Wr and Rd This will add the provision to control the PCIe halt Wr and Rd. By setting this DT flag, PCIe halt Wr and Rd can be disabled. In Olympic CPE targets observed degradation in throughput due to PCIe latencies with PCIe halt write/read feature. Hence, disabling the PCIe halt feature in Olympic CPE targets. Change-Id: Iee945984e24f2a99d9e0b1e2a0323255decc28ef --- bindings/pci/pci-msm.txt | 6 ++++++ qcom/sdxlemur-pcie.dtsi | 1 + 2 files changed, 7 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index fce9facfeada..30addf402558 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -407,12 +407,18 @@ interconnects: Usage: optional Value type: Definition: Skip enumeration for the list of 32-bit BDFs. + - qcom,config-recovery: Usage: optional Value type : Definition: Enable to notify the client driver for recovery when config space is not accessible +- qcom, pcie-halt-feature-dis: + Usage: optional + Value type : + Definition: Disable PCIe Write and Read halt feature + ============== Root port node ============== diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 05b1db8be5e1..437bac326385 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -115,6 +115,7 @@ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; + qcom,pcie-halt-feature-dis; qcom,pcie-phy-ver = <1108>; qcom,phy-status-offset = <0x1214>;