From e08d91fbba053195eebcb73447dcfe96aa9ca195 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 14:52:00 -0700 Subject: [PATCH 1/8] ARM: dts: msm: move dsi ctrl power nodes to common dt for Lahaina Move DSI ctrl power handles nodes from lahaina HLOS dt to common dt file as they are needed by all the vm's. Change-Id: Id59f51e1e9e821bb5b02dd26ec41aff71950c306 --- display/lahaina-sde-common.dtsi | 54 ++++++++++++++++++++++++++++++++ display/lahaina-sde.dtsi | 55 --------------------------------- 2 files changed, 54 insertions(+), 55 deletions(-) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index 8dd8954df0c3..bd93fb5130b3 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -280,6 +280,33 @@ reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { @@ -292,6 +319,33 @@ reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <8350>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 { diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 4aa15c2d2e45..870528fae30e 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -247,33 +247,6 @@ <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk"; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; &mdss_dsi1 { @@ -287,34 +260,6 @@ <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk"; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <8350>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; }; &mdss_dsi_phy0 { From ef6fabda4a5b30097f4103b8080d990bcbab264d Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Sat, 20 Jun 2020 00:15:04 -0700 Subject: [PATCH 2/8] ARM: dts: msm: add trusted vm dtsi files for Lahaina target Add trusted VM device tree files for Lahaina. These files inherit common Lahaina target bindings and overrides with needed bindings with VM specific values. Change-Id: Icb3090d1dfa6afe7eb993064e4493140708b658e --- display/trustedvm-lahaina-sde-display.dtsi | 33 +++++++++++ display/trustedvm-lahaina-sde.dtsi | 68 ++++++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 display/trustedvm-lahaina-sde-display.dtsi create mode 100644 display/trustedvm-lahaina-sde.dtsi diff --git a/display/trustedvm-lahaina-sde-display.dtsi b/display/trustedvm-lahaina-sde-display.dtsi new file mode 100644 index 000000000000..036205f97d18 --- /dev/null +++ b/display/trustedvm-lahaina-sde-display.dtsi @@ -0,0 +1,33 @@ +#include "lahaina-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>, + <&clock_cpucc PCLK_MUX_0_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_SRC_0_CLK>, + <&clock_cpucc PCLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_0_CLK>, + <&clock_cpucc BYTECLK_MUX_1_CLK>, + <&clock_cpucc PCLK_MUX_1_CLK>, + <&clock_cpucc CPHY_BYTECLK_SRC_1_CLK>, + <&clock_cpucc CPHY_PCLK_SRC_1_CLK>, + <&clock_cpucc BYTECLK_SRC_1_CLK>, + <&clock_cpucc PCLK_SRC_1_CLK>, + <&clock_cpucc SHADOW_BYTECLK_SRC_1_CLK>, + <&clock_cpucc SHADOW_PCLK_SRC_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1", + "src_byte_clk1", "src_pixel_clk1", + "shadow_byte_clk1", "shadow_pixel_clk1"; + qcom,panel-te-source = <0>; +}; + +&mdss_mdp { + connectors = <&sde_dsi>; +}; diff --git a/display/trustedvm-lahaina-sde.dtsi b/display/trustedvm-lahaina-sde.dtsi new file mode 100644 index 000000000000..005a82796a64 --- /dev/null +++ b/display/trustedvm-lahaina-sde.dtsi @@ -0,0 +1,68 @@ +#include "lahaina-sde-common.dtsi" +#include + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>, + <0x0ae8f000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-hw-version =<0x70000000>; + + clocks = + <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc GCC_DISP_SF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_cpucc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; From 5bd4516c99157317ccd6977440c2bcded088e0b8 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 14:59:41 -0700 Subject: [PATCH 3/8] bindings: Documentation: add property to indicate trusted VM execution Add a property in SDE device to indicate the executing environment is the trusted VM. Change-Id: Id4650d60f582b2058b166e69c2b0c66cdfce36e0 --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 93e968a01ab9..6bad2544b4c9 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -517,6 +517,8 @@ Optional properties: ordering block 0: lower priority pipe has to be on the left for a given pair of pipes. 1: priority have to be explicitly configured for a given pair of pipes. +- qcom,sde-trusted-vm-env: Boolean property to indicate if the device + driver is executing in a trusted VM Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -728,6 +730,7 @@ Example: qcom,sde-te2-off = <0x100>; qcom,sde-te-size = <0xffff>; qcom,sde-te2-size = <0xffff>; + qcom,sde-trusted-vm-env; qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x2bc 16>; From 0f35dca90be9f19a674eb344d812e8913732b024 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Mon, 1 Jun 2020 17:17:02 -0700 Subject: [PATCH 4/8] ARM: dts: msm: add property for trusted VM execution for Lahaina Add a property in the display device to indicate the executing environment being a trusted VM for Lahaina target. Change-Id: Iaeeba1b83b8167accfdcb6bbe4f3fd930b891e52 --- display/trustedvm-lahaina-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/trustedvm-lahaina-sde.dtsi b/display/trustedvm-lahaina-sde.dtsi index 005a82796a64..8ee259e82f95 100644 --- a/display/trustedvm-lahaina-sde.dtsi +++ b/display/trustedvm-lahaina-sde.dtsi @@ -35,6 +35,7 @@ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; + qcom,sde-trusted-vm-env; }; &mdss_dsi0 { From 21bb257fd5f8243ef8121e2b699139f1d6d7dfe3 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 13:07:29 -0700 Subject: [PATCH 5/8] bindings: Documentation: add property to specify max trusted vm displays Add documentation for the property to specify the maximum number of concurrent displays supported in the trusted vm environment. Change-Id: I84c0408686e816a6498931949b7391209c9f9640 --- bindings/sde.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 6bad2544b4c9..635cefcd2ad7 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -519,6 +519,9 @@ Optional properties: 1: priority have to be explicitly configured for a given pair of pipes. - qcom,sde-trusted-vm-env: Boolean property to indicate if the device driver is executing in a trusted VM +- qcom,sde-max-trusted-vm-displays: A u32 property to indicate the maximum + number of concurrent displays supported in the + trusted vm environment Bus Scaling: - interconnects An array of 4 cell properties with the format of @@ -711,6 +714,7 @@ Example: qcom,sde-has-idle-pc; qcom,fullsize-va-map; qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; qcom,sde-max-dest-scaler-input-linewidth = <2048>; qcom,sde-max-dest-scaler-output-linewidth = <2560>; qcom,sde-sspp-max-rects = <1 1 1 1 From 555466b842307c7c84ec808352a5114370f504be Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 13:05:35 -0700 Subject: [PATCH 6/8] ARM: dts: msm: specify max trusted vm displays for Lahaina Specify maximum number of concurrent displays supported in trusted vm. This value will be used by both the vm's to validate the TUI start request. For Lahaina, we support one display in trusted vm. Change-Id: I643bacea09f1eead26c0165bf00590afeda67569 --- display/lahaina-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/lahaina-sde-common.dtsi b/display/lahaina-sde-common.dtsi index bd93fb5130b3..fc2d7fa27bf7 100644 --- a/display/lahaina-sde-common.dtsi +++ b/display/lahaina-sde-common.dtsi @@ -161,6 +161,7 @@ qcom,sde-pipe-order-version = <0x1>; qcom,sde-has-dim-layer; qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; qcom,sde-max-dest-scaler-input-linewidth = <2048>; qcom,sde-max-dest-scaler-output-linewidth = <2560>; From 51ce5ca9dfdd9e64a68cc1ab877e344c1b500f84 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Tue, 7 Jul 2020 13:12:50 -0700 Subject: [PATCH 7/8] bindings: Documentation: add a property to exclude reg-names In trusted vm, register ranges that need to be mapped need to exactly be the same as that of HLOS vm. But the DT provided register ranges are used to validate the IO memory assign from HLOS vm. So this change introduces a separate property to specify the register names which need to be excluded from the IO memory validation list but still need to be mapped to the vm. Change-Id: I8c5c194254ae260f7a8878bb5492f5a039203fc9 --- bindings/sde.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 635cefcd2ad7..d6cf76c02dd7 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -522,6 +522,9 @@ Optional properties: - qcom,sde-max-trusted-vm-displays: A u32 property to indicate the maximum number of concurrent displays supported in the trusted vm environment +- qcom,sde-vm-exclude-reg-names A string array indicating the reg-names which + should be excluded from IO memory validation list + in trusted vm environment Bus Scaling: - interconnects An array of 4 cell properties with the format of From 044f1408aaa2604cb4abb22a13c18a8880968b00 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Mon, 13 Jul 2020 14:56:12 -0700 Subject: [PATCH 8/8] ARM: dts: msm: populate the property to exclude reg-names for validation Populate the property to exclude reg-names in trusted vm for Lahaina target while validating the IO memory assign from primary vm. Change-Id: I9dc92be7d11862f9af3c083939e82fa8a705b9e3 --- display/trustedvm-lahaina-sde.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/trustedvm-lahaina-sde.dtsi b/display/trustedvm-lahaina-sde.dtsi index 8ee259e82f95..dfebcb3a869f 100644 --- a/display/trustedvm-lahaina-sde.dtsi +++ b/display/trustedvm-lahaina-sde.dtsi @@ -21,6 +21,8 @@ "regdma_phys", "sid_phys"; + qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,sde-hw-version =<0x70000000>; clocks =