mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-31 04:01:48 -04:00
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (21 commits)
m68knommu: convert to using tracehook_report_syscall_*
m68knommu: some boards use fixed phy for FEC ethernet
m68knommu: support the external GPIO based interrupts of the 5272
m68knommu: mask of vector bits in exception word properly
m68knommu: change to new flag variables
m68knommu: Fix MCFUART_TXFIFOSIZE for m548x.
m68knommu: add basic mmu-less m548x support
m68knommu: .gitignore vmlinux.lds
m68knommu: stop using __do_IRQ
m68knommu: rename PT_OFF_VECTOR to PT_OFF_FORMATVEC.
m68knommu: add support for Coldfire 547x/548x interrupt controller
m68k{nommu}: Remove unused DEFINE's from asm-offsets.c
m68knommu: whitespace cleanup in 68328/entry.S
m68knommu: Document supported chips in intc-2.c and intc-simr.c.
m68knommu: fix strace support for 68328/68360
m68knommu: fix default starting date
arch/m68knommu: Removing dead 68328_SERIAL_UART2 config option
arch/m68knommu: Removing dead RAM_{16,32}_MB config option
arch/m68knommu: Removing dead M68KFPU_EMU config option
arch/m68knommu: Removing dead RELOCATE config option
...
This commit is contained in:
Linus Torvalds
commit
4b37ba90f4
47 changed files with 707 additions and 215 deletions
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@ -29,7 +29,7 @@
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static inline void __flush_cache_all(void)
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{
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#ifdef CONFIG_M5407
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#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
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/*
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* Use cpushl to push and invalidate all cache lines.
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* Gas doesn't seem to know how to generate the ColdFire
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@ -32,7 +32,9 @@
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*/
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#define MCF_MBAR 0x10000000
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#define MCF_MBAR2 0x80000000
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#if defined(CONFIG_M520x)
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#if defined(CONFIG_M548x)
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#define MCF_IPSBAR MCF_MBAR
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#elif defined(CONFIG_M520x)
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#define MCF_IPSBAR 0xFC000000
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#else
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#define MCF_IPSBAR 0x40000000
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@ -36,7 +36,8 @@
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*/
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M532x) || defined(CONFIG_M548x)
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/* These parts have GPIO organized by 8 bit ports */
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@ -136,6 +137,8 @@ static inline u32 __mcf_gpio_ppdr(unsigned gpio)
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#endif
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else
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return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
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#else
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return 0;
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#endif
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}
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@ -173,6 +176,8 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
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#endif
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else
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return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
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#else
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return 0;
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#endif
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}
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88
arch/m68k/include/asm/m548xgpt.h
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88
arch/m68k/include/asm/m548xgpt.h
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@ -0,0 +1,88 @@
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/*
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* File: m548xgpt.h
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* Purpose: Register and bit definitions for the MCF548X
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*
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* Notes:
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*
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*/
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#ifndef m548xgpt_h
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#define m548xgpt_h
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/*********************************************************************
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*
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* General Purpose Timers (GPT)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_GPT_GMS0 0x000800
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#define MCF_GPT_GCIR0 0x000804
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#define MCF_GPT_GPWM0 0x000808
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#define MCF_GPT_GSR0 0x00080C
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#define MCF_GPT_GMS1 0x000810
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#define MCF_GPT_GCIR1 0x000814
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#define MCF_GPT_GPWM1 0x000818
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#define MCF_GPT_GSR1 0x00081C
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#define MCF_GPT_GMS2 0x000820
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#define MCF_GPT_GCIR2 0x000824
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#define MCF_GPT_GPWM2 0x000828
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#define MCF_GPT_GSR2 0x00082C
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#define MCF_GPT_GMS3 0x000830
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#define MCF_GPT_GCIR3 0x000834
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#define MCF_GPT_GPWM3 0x000838
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#define MCF_GPT_GSR3 0x00083C
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#define MCF_GPT_GMS(x) (0x000800+((x)*0x010))
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#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010))
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#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010))
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#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010))
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/* Bit definitions and macros for MCF_GPT_GMS */
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#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
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#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
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#define MCF_GPT_GMS_IEN (0x00000100)
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#define MCF_GPT_GMS_OD (0x00000200)
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#define MCF_GPT_GMS_SC (0x00000400)
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#define MCF_GPT_GMS_CE (0x00001000)
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#define MCF_GPT_GMS_WDEN (0x00008000)
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#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
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#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
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#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
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#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
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#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
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#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
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#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
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#define MCF_GPT_GMS_ICT_ANY (0x00000000)
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#define MCF_GPT_GMS_ICT_RISE (0x00010000)
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#define MCF_GPT_GMS_ICT_FALL (0x00020000)
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#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
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#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
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#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
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#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
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#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
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#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
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#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
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#define MCF_GPT_GMS_TMS_PWM (0x00000003)
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#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
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/* Bit definitions and macros for MCF_GPT_GCIR */
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#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
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#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_GPT_GPWM */
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#define MCF_GPT_GPWM_LOAD (0x00000001)
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#define MCF_GPT_GPWM_PWMOP (0x00000100)
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#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_GPT_GSR */
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#define MCF_GPT_GSR_CAPT (0x00000001)
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#define MCF_GPT_GSR_COMP (0x00000002)
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#define MCF_GPT_GSR_PWMP (0x00000004)
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#define MCF_GPT_GSR_TEXP (0x00000008)
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#define MCF_GPT_GSR_PIN (0x00000100)
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#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
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#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
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/********************************************************************/
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#endif /* m548xgpt_h */
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55
arch/m68k/include/asm/m548xsim.h
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55
arch/m68k/include/asm/m548xsim.h
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@ -0,0 +1,55 @@
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/*
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* m548xsim.h -- ColdFire 547x/548x System Integration Unit support.
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*/
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#ifndef m548xsim_h
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#define m548xsim_h
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#define MCFINT_VECBASE 64
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/*
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* Interrupt Controller Registers
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*/
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#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
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#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
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#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
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#define MCFINTC_IRLR 0x18 /* */
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#define MCFINTC_IACKL 0x19 /* */
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#define MCFINTC_ICR0 0x40 /* Base ICR register */
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
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#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */
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#define MCFGPIO_IRQ_MAX -1
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#define MCFGPIO_IRQ_VECBASE -1
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/*
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* Some PSC related definitions
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*/
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#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
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#define MCF_PAR_SDA (0x0008)
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#define MCF_PAR_SCL (0x0004)
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#define MCF_PAR_PSC_TXD (0x04)
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#define MCF_PAR_PSC_RXD (0x08)
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#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
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#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
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#define MCF_PAR_PSC_CTS_GPIO (0x00)
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#define MCF_PAR_PSC_CTS_BCLK (0x80)
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#define MCF_PAR_PSC_CTS_CTS (0xC0)
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#define MCF_PAR_PSC_RTS_GPIO (0x00)
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#define MCF_PAR_PSC_RTS_FSYNC (0x20)
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#define MCF_PAR_PSC_RTS_RTS (0x30)
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#define MCF_PAR_PSC_CANRX (0x40)
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#endif /* m548xsim_h */
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@ -107,7 +107,7 @@
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.endm
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#endif /* CONFIG_M532x */
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#if defined(CONFIG_M5407)
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#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
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/*
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* Version 4 cores have a true harvard style separate instruction
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* and data cache. Invalidate and enable cache, also enable write
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@ -41,6 +41,8 @@
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#elif defined(CONFIG_M5407)
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#include <asm/m5407sim.h>
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#include <asm/mcfintc.h>
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#elif defined(CONFIG_M548x)
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#include <asm/m548xsim.h>
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#endif
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/****************************************************************************/
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44
arch/m68k/include/asm/mcfslt.h
Normal file
44
arch/m68k/include/asm/mcfslt.h
Normal file
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@ -0,0 +1,44 @@
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/****************************************************************************/
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/*
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* mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
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*
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* (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
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*/
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/****************************************************************************/
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#ifndef mcfslt_h
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#define mcfslt_h
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/****************************************************************************/
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/*
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* Get address specific defines for the 547x.
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*/
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#define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */
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#define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */
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/*
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* Define the SLT timer register set addresses.
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*/
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#define MCFSLT_STCNT 0x00 /* Terminal count */
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#define MCFSLT_SCR 0x04 /* Control */
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#define MCFSLT_SCNT 0x08 /* Current count */
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#define MCFSLT_SSR 0x0C /* Status */
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/*
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* Bit definitions for the SCR control register.
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*/
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#define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */
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#define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */
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#define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */
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/*
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* Bit definitions for the SSR status register.
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*/
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#define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */
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#define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */
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/****************************************************************************/
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#endif /* mcfslt_h */
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@ -47,6 +47,11 @@
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#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
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#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
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#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
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#elif defined(CONFIG_M548x)
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#define MCFUART_BASE1 0x8600 /* on M548x */
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#define MCFUART_BASE2 0x8700 /* on M548x */
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#define MCFUART_BASE3 0x8800 /* on M548x */
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#define MCFUART_BASE4 0x8900 /* on M548x */
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#endif
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@ -212,7 +217,9 @@ struct mcf_platform_uart {
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#define MCFUART_URF_RXS 0xc0 /* Receiver status */
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#endif
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#if defined(CONFIG_M5272)
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#if defined(CONFIG_M548x)
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#define MCFUART_TXFIFOSIZE 512
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#elif defined(CONFIG_M5272)
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#define MCFUART_TXFIFOSIZE 25
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#else
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#define MCFUART_TXFIFOSIZE 1
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@ -22,13 +22,9 @@
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int main(void)
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{
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/* offsets into the task struct */
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DEFINE(TASK_STATE, offsetof(struct task_struct, state));
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DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags));
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DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace));
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DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
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DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info));
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DEFINE(TASK_MM, offsetof(struct task_struct, mm));
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DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
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#ifdef CONFIG_MMU
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DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info));
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#endif
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@ -64,14 +60,6 @@ int main(void)
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/* bitfields are a bit difficult */
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DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
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/* offsets into the irq_handler struct */
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DEFINE(IRQ_HANDLER, offsetof(struct irq_node, handler));
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DEFINE(IRQ_DEVID, offsetof(struct irq_node, dev_id));
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DEFINE(IRQ_NEXT, offsetof(struct irq_node, next));
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/* offsets into the kernel_stat struct */
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DEFINE(STAT_IRQ, offsetof(struct kernel_stat, irqs));
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/* offsets into the irq_cpustat_t struct */
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DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
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