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clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks

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The PCIe PIPE clock in the GCC is fed by the PIPE clock coming from the
PHY, describe this relationship.

Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
This commit is contained in:
Bjorn Andersson 2019-02-25 23:02:21 -08:00 • committed by Stephen Boyd
commit 4b5a59a265
1 changed files with 5 additions and 0 deletions
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5
drivers/clk/qcom/gcc-sdm845.c
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@ -1697,6 +1697,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.parent_names = (const char *[]){ "pcie_0_pipe_clk" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@ -1796,6 +1799,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
.enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.parent_names = (const char *[]){ "pcie_1_pipe_clk" },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},