icnss2: Send SMMU IOVA range only when SMMU S1 is enabled

Send SMMU IOVA range to Firmware only when SMMU S1 stage is
enabled.

Change-Id: I3d0d0b6ad3db18aded0d921f79337cf845ceb5f4
Signed-off-by: Naman Padhiar <npadhiar@codeaurora.org>
This commit is contained in:
Naman Padhiar 2020-07-23 19:13:34 +05:30
commit 4bb5a23e62
3 changed files with 11 additions and 1 deletions

View file

@ -2923,6 +2923,7 @@ static int icnss_smmu_dt_parse(struct icnss_priv *priv)
int ret = 0;
struct platform_device *pdev = priv->pdev;
struct device *dev = &pdev->dev;
const char *iommu_dma_type;
struct resource *res;
u32 addr_win[2];
@ -2943,6 +2944,13 @@ static int icnss_smmu_dt_parse(struct icnss_priv *priv)
priv->iommu_domain =
iommu_get_domain_for_dev(&pdev->dev);
ret = of_property_read_string(dev->of_node, "qcom,iommu-dma",
&iommu_dma_type);
if (!ret && !strcmp("fastmap", iommu_dma_type)) {
icnss_pr_dbg("SMMU S1 stage enabled\n");
priv->smmu_s1_enable = true;
}
res = platform_get_resource_byname(pdev,
IORESOURCE_MEM,
"smmu_iova_ipa");

View file

@ -356,6 +356,7 @@ struct icnss_priv {
struct completion unblock_shutdown;
char function_name[WLFW_FUNCTION_NAME_LEN + 1];
bool is_ssr;
bool smmu_s1_enable;
struct kobject *icnss_kobject;
atomic_t is_shutdown;
u32 qdss_mem_seg_len;

View file

@ -2243,7 +2243,8 @@ int wlfw_host_cap_send_sync(struct icnss_priv *priv)
req->cal_done = priv->cal_done;
icnss_pr_dbg("Calibration done is %d\n", priv->cal_done);
if (!icnss_get_iova(priv, &iova_start, &iova_size) &&
if (priv->smmu_s1_enable &&
!icnss_get_iova(priv, &iova_start, &iova_size) &&
!icnss_get_iova_ipa(priv, &iova_ipa_start,
&iova_ipa_size)) {
req->ddr_range_valid = 1;