mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 21:54:34 -04:00
Merge "clk: qcom: debugcc: Add debug clock controller support for QCS404"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
4c6d782bd9
5 changed files with 1345 additions and 439 deletions
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@ -72,6 +72,15 @@ config QCOM_CLK_RPMH
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Say Y if you want to support the clocks exposed by RPMh on
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platforms such as SDM845.
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config QCS_CMN_BLK_PLL
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tristate "QCS404 CMN BLK PLL"
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select QCS_GCC_404
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help
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Support for the CMN BLK PLL on Qualcomm Technologies, Inc QCS404
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devices.
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Common block PLL is required for USB and PCIE subsystems.
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Say Y if you want to support the Common Block PLL.
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config APQ_GCC_8084
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tristate "APQ8084 Global Clock Controller"
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select QCOM_GDSC
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@ -221,6 +230,15 @@ config MSM_GCC_8998
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Say Y if you want to use peripheral devices such as UART, SPI,
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i2c, USB, UFS, SD/eMMC, PCIe, etc.
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config QCS_DEBUGCC_404
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tristate "QCS404 Debug Clock Controller"
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depends on QCS_GCC_404
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help
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Support for the debug clock controller on Qualcomm Technologies, Inc.
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QCS404 devices.
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Say Y if you want to support the debug clocks such as clock measurement
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functionality.
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config QCS_GCC_404
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tristate "QCS404 Global Clock Controller"
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help
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@ -54,6 +54,8 @@ obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
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obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
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obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
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obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
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obj-$(CONFIG_QCS_CMN_BLK_PLL) += cmn-blk-pll.o
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obj-$(CONFIG_QCS_DEBUGCC_404) += debugcc-qcs404.o
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obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
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obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
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obj-$(CONFIG_SA_DEBUGCC_DIREWOLF) += debugcc-direwolf.o
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236
drivers/clk/qcom/cmn-blk-pll.c
Normal file
236
drivers/clk/qcom/cmn-blk-pll.c
Normal file
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@ -0,0 +1,236 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/clock/qcom,cmn-blk-pll.h>
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#include "common.h"
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#define SW_RESET_LOGIC_MASK BIT(6)
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struct cmn_blk_pll {
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struct regmap *regmap;
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struct clk *misc_reset;
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struct clk *ahb_clk;
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struct clk *aon_clk;
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struct reset_control *reset;
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};
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static struct cmn_blk_pll pll;
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static unsigned long clk_cmn_blk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return to_clk_fixed_rate(hw)->fixed_rate;
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}
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static int clk_cmn_blk_pll_prepare(struct clk_hw *hw)
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{
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int ret;
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ret = clk_prepare(pll.misc_reset);
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if (ret)
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return ret;
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ret = clk_prepare(pll.aon_clk);
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if (ret)
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return ret;
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return clk_prepare(pll.ahb_clk);
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}
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static int clk_cmn_blk_pll_enable(struct clk_hw *hw)
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{
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u32 val, ret;
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ret = reset_control_reset(pll.reset);
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if (ret)
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return ret;
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ret = clk_enable(pll.misc_reset);
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if (ret)
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return ret;
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ret = clk_enable(pll.aon_clk);
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if (ret)
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return ret;
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ret = clk_enable(pll.ahb_clk);
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if (ret)
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return ret;
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ret = regmap_read(pll.regmap, 0, &val);
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if (ret)
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return ret;
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if (val & SW_RESET_LOGIC_MASK) {
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val &= ~BIT(6);
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regmap_write(pll.regmap, 0, val);
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}
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val |= BIT(6);
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regmap_write(pll.regmap, 0, val);
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return 0;
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}
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static void clk_cmn_blk_pll_unprepare(struct clk_hw *hw)
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{
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clk_unprepare(pll.misc_reset);
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clk_unprepare(pll.aon_clk);
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clk_unprepare(pll.ahb_clk);
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}
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static void clk_cmn_blk_pll_disable(struct clk_hw *hw)
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{
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u32 val;
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regmap_read(pll.regmap, 0, &val);
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val &= ~BIT(6);
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regmap_write(pll.regmap, 0, val);
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clk_disable(pll.misc_reset);
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clk_disable(pll.aon_clk);
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clk_disable(pll.ahb_clk);
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}
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const struct clk_ops clk_cmn_blk_ops = {
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.prepare = clk_cmn_blk_pll_prepare,
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.enable = clk_cmn_blk_pll_enable,
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.disable = clk_cmn_blk_pll_disable,
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.unprepare = clk_cmn_blk_pll_unprepare,
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.recalc_rate = clk_cmn_blk_recalc_rate,
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};
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static struct clk_fixed_rate cmn_blk_pll = {
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.fixed_rate = 100000000,
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.hw.init = &(struct clk_init_data){
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.name = "cmn_blk_pll",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_cmn_blk_ops,
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},
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};
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struct clk_hw *cmn_blk_pll_hws[] = {
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[CMN_BLK_PLL] = &cmn_blk_pll.hw,
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};
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static const struct regmap_config cmn_blk_pll_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x8,
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.fast_io = true,
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};
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static const struct of_device_id cmn_blk_pll_match_table[] = {
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{ .compatible = "qcom,cmn_blk_pll" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, cmn_blk_pll_match_table);
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static int cmn_blk_pll_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct clk_hw_onecell_data *clk_data;
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struct device *dev = &pdev->dev;
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void __iomem *base;
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int i, ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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pll.regmap = devm_regmap_init_mmio(&pdev->dev, base,
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&cmn_blk_pll_regmap_config);
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if (IS_ERR(pll.regmap))
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return PTR_ERR(pll.regmap);
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pll.misc_reset = devm_clk_get(&pdev->dev, "misc_reset_clk");
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if (IS_ERR(pll.misc_reset)) {
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if (PTR_ERR(pll.misc_reset) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Unable to get misc_reset clock\n");
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return PTR_ERR(pll.misc_reset);
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}
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pll.ahb_clk = devm_clk_get(&pdev->dev, "ahb_clk");
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if (IS_ERR(pll.ahb_clk)) {
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if (PTR_ERR(pll.ahb_clk) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Unable to get ahb_clk clock\n");
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return PTR_ERR(pll.ahb_clk);
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}
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pll.aon_clk = devm_clk_get(&pdev->dev, "aon_clk");
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if (IS_ERR(pll.aon_clk)) {
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if (PTR_ERR(pll.aon_clk) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Unable to get aon_clk clock\n");
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return PTR_ERR(pll.aon_clk);
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}
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pll.reset = devm_reset_control_get(&pdev->dev, "cmn_blk_pll_reset");
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if (IS_ERR(pll.reset)) {
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if (PTR_ERR(pll.reset) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Unable to get cmn_blk\n");
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return PTR_ERR(pll.reset);
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}
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clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->num = ARRAY_SIZE(cmn_blk_pll_hws);
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for (i = 0; i < clk_data->num; i++) {
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ret = devm_clk_hw_register(dev, cmn_blk_pll_hws[i]);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register cmn_blk_pll\n");
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return ret;
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}
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clk_data->hws[i] = cmn_blk_pll_hws[i];
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}
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
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if (ret) {
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dev_err(dev, "Unable to register cmn_blk_pll provider ret = %d\n"
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, ret);
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return ret;
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}
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dev_info(&pdev->dev, "Registered CMN BLK PLL\n");
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return 0;
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}
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static struct platform_driver cmn_blk_pll_driver = {
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.probe = cmn_blk_pll_probe,
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.driver = {
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.name = "cmn_blk_pll",
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.of_match_table = cmn_blk_pll_match_table,
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},
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};
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static int __init cmn_blk_pll_init(void)
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{
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return platform_driver_register(&cmn_blk_pll_driver);
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}
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subsys_initcall(cmn_blk_pll_init);
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static void __exit cmn_blk_pll_exit(void)
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{
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platform_driver_unregister(&cmn_blk_pll_driver);
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}
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module_exit(cmn_blk_pll_exit);
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367
drivers/clk/qcom/debugcc-qcs404.c
Normal file
367
drivers/clk/qcom/debugcc-qcs404.c
Normal file
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@ -0,0 +1,367 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "clk: %s: " fmt, __func__
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "clk-debug.h"
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#include "common.h"
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static struct measure_clk_data debug_mux_priv = {
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.ctl_reg = 0x74004,
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.status_reg = 0x74008,
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.xo_div4_cbcr = 0x30034,
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};
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static const char *const apcs_debug_mux_parent_names[] = {
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"measure_only_apcs_clk",
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};
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static int apcs_debug_mux_sels[] = {
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0x0, /* measure_only_apcs_clk */
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};
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static int apcs_debug_mux_pre_divs[] = {
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0x1, /* measure_only_apcs_clk */
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};
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static struct clk_debug_mux apcs_debug_mux = {
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.priv = &debug_mux_priv,
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.debug_offset = 0x0,
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.post_div_offset = 0x0,
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.cbcr_offset = U32_MAX,
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.src_sel_mask = 0x300,
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.src_sel_shift = 8,
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.post_div_mask = 0x1E0000,
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.post_div_shift = 11,
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.post_div_val = 1,
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.mux_sels = apcs_debug_mux_sels,
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.pre_div_vals = apcs_debug_mux_pre_divs,
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.hw.init = &(struct clk_init_data){
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.name = "apcs_debug_mux",
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.ops = &clk_debug_mux_ops,
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.parent_names = apcs_debug_mux_parent_names,
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.num_parents = ARRAY_SIZE(apcs_debug_mux_parent_names),
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.flags = CLK_IS_MEASURE,
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},
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};
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static const char *const gcc_debug_mux_parent_names[] = {
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"gcc_apss_ahb_clk",
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"gcc_bimc_gfx_clk",
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"gcc_bimc_gpu_clk",
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"gcc_bimc_mdss_clk",
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"gcc_blsp1_ahb_clk",
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"gcc_blsp1_qup0_i2c_apps_clk",
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"gcc_blsp1_qup0_spi_apps_clk",
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"gcc_blsp1_qup1_i2c_apps_clk",
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"gcc_blsp1_qup1_spi_apps_clk",
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"gcc_blsp1_qup2_i2c_apps_clk",
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"gcc_blsp1_qup2_spi_apps_clk",
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"gcc_blsp1_qup3_i2c_apps_clk",
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"gcc_blsp1_qup3_spi_apps_clk",
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"gcc_blsp1_qup4_i2c_apps_clk",
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"gcc_blsp1_qup4_spi_apps_clk",
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"gcc_blsp1_uart0_apps_clk",
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"gcc_blsp1_uart1_apps_clk",
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"gcc_blsp1_uart2_apps_clk",
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"gcc_blsp1_uart3_apps_clk",
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"gcc_blsp2_ahb_clk",
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"gcc_blsp2_qup0_i2c_apps_clk",
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"gcc_blsp2_qup0_spi_apps_clk",
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"gcc_blsp2_uart0_apps_clk",
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"gcc_boot_rom_ahb_clk",
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"gcc_dcc_clk",
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"gcc_eth_axi_clk",
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"gcc_eth_ptp_clk",
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"gcc_eth_rgmii_clk",
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"gcc_eth_slave_ahb_clk",
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"gcc_geni_ir_s_clk",
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"gcc_gfx_tbu_clk",
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"gcc_gfx_tcu_clk",
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"gcc_gp1_clk",
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"gcc_gp2_clk",
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"gcc_gp3_clk",
|
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"gcc_gtcu_ahb_clk",
|
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"gcc_mdss_ahb_clk",
|
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"gcc_mdss_axi_clk",
|
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"gcc_mdss_byte0_clk",
|
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"gcc_mdss_esc0_clk",
|
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"gcc_mdss_hdmi_app_clk",
|
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"gcc_mdss_hdmi_pclk_clk",
|
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"gcc_mdss_mdp_clk",
|
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"gcc_mdss_pclk0_clk",
|
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"gcc_mdss_vsync_clk",
|
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"gcc_oxili_ahb_clk",
|
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"gcc_oxili_gfx3d_clk",
|
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"gcc_pcie_0_aux_clk",
|
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"gcc_pcie_0_cfg_ahb_clk",
|
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"gcc_pcie_0_mstr_axi_clk",
|
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"gcc_pcie_0_pipe_clk",
|
||||
"gcc_pcie_0_slv_axi_clk",
|
||||
"gcc_pcnoc_usb2_clk",
|
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"gcc_pcnoc_usb3_clk",
|
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"gcc_pdm2_clk",
|
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"gcc_pdm_ahb_clk",
|
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"gcc_prng_ahb_clk",
|
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"gcc_pwm0_xo512_clk",
|
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"gcc_pwm1_xo512_clk",
|
||||
"gcc_pwm2_xo512_clk",
|
||||
"gcc_sdcc1_ahb_clk",
|
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"gcc_sdcc1_apps_clk",
|
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"gcc_sdcc1_ice_core_clk",
|
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"gcc_sdcc2_ahb_clk",
|
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"gcc_sdcc2_apps_clk",
|
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"gcc_smmu_cfg_clk",
|
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"gcc_sys_noc_usb3_clk",
|
||||
"gcc_usb20_mock_utmi_clk",
|
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"gcc_usb2a_phy_sleep_clk",
|
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"gcc_usb30_master_clk",
|
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"gcc_usb30_mock_utmi_clk",
|
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"gcc_usb30_phy_pipe_clk",
|
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"gcc_usb30_sleep_clk",
|
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"gcc_usb3_phy_aux_clk",
|
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"gcc_usb_hs_inactivity_timers_clk",
|
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"gcc_usb_hs_phy_cfg_ahb_clk",
|
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"gcc_usb_hs_system_clk",
|
||||
"gcc_apss_tcu_clk",
|
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"gcc_crypto_ahb_clk",
|
||||
"gcc_crypto_axi_clk",
|
||||
"gcc_mdp_tbu_clk",
|
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"gcc_qdss_dap_clk",
|
||||
"gcc_geni_ir_h_clk",
|
||||
"gcc_dcc_xo_clk",
|
||||
"pnoc_clk",
|
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"qpic_clk",
|
||||
"snoc_clk",
|
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"bimc_clk",
|
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"ce1_clk",
|
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"apcs_debug_mux",
|
||||
};
|
||||
|
||||
static int gcc_debug_mux_sels[] = {
|
||||
0x168, /* gcc_apss_ahb_clk */
|
||||
0x2D, /* gcc_bimc_gfx_clk */
|
||||
0x157, /* gcc_bimc_gpu_clk */
|
||||
0x15F, /* gcc_bimc_mdss_clk */
|
||||
0x88, /* gcc_blsp1_ahb_clk */
|
||||
0x99, /* gcc_blsp1_qup0_i2c_apps_clk */
|
||||
0x98, /* gcc_blsp1_qup0_spi_apps_clk */
|
||||
0x8B, /* gcc_blsp1_qup1_i2c_apps_clk */
|
||||
0x8A, /* gcc_blsp1_qup1_spi_apps_clk */
|
||||
0x8F, /* gcc_blsp1_qup2_i2c_apps_clk */
|
||||
0x8E, /* gcc_blsp1_qup2_spi_apps_clk */
|
||||
0x93, /* gcc_blsp1_qup3_i2c_apps_clk */
|
||||
0x92, /* gcc_blsp1_qup3_spi_apps_clk */
|
||||
0x95, /* gcc_blsp1_qup4_i2c_apps_clk */
|
||||
0x94, /* gcc_blsp1_qup4_spi_apps_clk */
|
||||
0x9A, /* gcc_blsp1_uart0_apps_clk */
|
||||
0x8C, /* gcc_blsp1_uart1_apps_clk */
|
||||
0x90, /* gcc_blsp1_uart2_apps_clk */
|
||||
0x96, /* gcc_blsp1_uart3_apps_clk */
|
||||
0xA0, /* gcc_blsp2_ahb_clk */
|
||||
0xA3, /* gcc_blsp2_qup0_i2c_apps_clk */
|
||||
0xA2, /* gcc_blsp2_qup0_spi_apps_clk */
|
||||
0xA4, /* gcc_blsp2_uart0_apps_clk */
|
||||
0xF8, /* gcc_boot_rom_ahb_clk */
|
||||
0x1B9, /* gcc_dcc_clk */
|
||||
0x80, /* gcc_eth_axi_clk */
|
||||
0x83, /* gcc_eth_ptp_clk */
|
||||
0x81, /* gcc_eth_rgmii_clk */
|
||||
0x82, /* gcc_eth_slave_ahb_clk */
|
||||
0xEE, /* gcc_geni_ir_s_clk */
|
||||
0x52, /* gcc_gfx_tbu_clk */
|
||||
0x53, /* gcc_gfx_tcu_clk */
|
||||
0x10, /* gcc_gp1_clk */
|
||||
0x11, /* gcc_gp2_clk */
|
||||
0x12, /* gcc_gp3_clk */
|
||||
0x58, /* gcc_gtcu_ahb_clk */
|
||||
0x1F6, /* gcc_mdss_ahb_clk */
|
||||
0x1F7, /* gcc_mdss_axi_clk */
|
||||
0x1FC, /* gcc_mdss_byte0_clk */
|
||||
0x1FD, /* gcc_mdss_esc0_clk */
|
||||
0x1F2, /* gcc_mdss_hdmi_app_clk */
|
||||
0x1F1, /* gcc_mdss_hdmi_pclk_clk */
|
||||
0x1F9, /* gcc_mdss_mdp_clk */
|
||||
0x1F8, /* gcc_mdss_pclk0_clk */
|
||||
0x1FB, /* gcc_mdss_vsync_clk */
|
||||
0x1EB, /* gcc_oxili_ahb_clk */
|
||||
0x1EA, /* gcc_oxili_gfx3d_clk */
|
||||
0xAB, /* gcc_pcie_0_aux_clk */
|
||||
0xAA, /* gcc_pcie_0_cfg_ahb_clk */
|
||||
0xA9, /* gcc_pcie_0_mstr_axi_clk */
|
||||
0xAC, /* gcc_pcie_0_pipe_clk */
|
||||
0xA8, /* gcc_pcie_0_slv_axi_clk */
|
||||
0x9, /* gcc_pcnoc_usb2_clk */
|
||||
0xA, /* gcc_pcnoc_usb3_clk */
|
||||
0xD2, /* gcc_pdm2_clk */
|
||||
0xD0, /* gcc_pdm_ahb_clk */
|
||||
0xD8, /* gcc_prng_ahb_clk */
|
||||
0xD3, /* gcc_pwm0_xo512_clk */
|
||||
0xD4, /* gcc_pwm1_xo512_clk */
|
||||
0xD5, /* gcc_pwm2_xo512_clk */
|
||||
0x69, /* gcc_sdcc1_ahb_clk */
|
||||
0x68, /* gcc_sdcc1_apps_clk */
|
||||
0x6A, /* gcc_sdcc1_ice_core_clk */
|
||||
0x71, /* gcc_sdcc2_ahb_clk */
|
||||
0x70, /* gcc_sdcc2_apps_clk */
|
||||
0x5B, /* gcc_smmu_cfg_clk */
|
||||
0x1, /* gcc_sys_noc_usb3_clk */
|
||||
0x65, /* gcc_usb20_mock_utmi_clk */
|
||||
0x63, /* gcc_usb2a_phy_sleep_clk */
|
||||
0x78, /* gcc_usb30_master_clk */
|
||||
0x7A, /* gcc_usb30_mock_utmi_clk */
|
||||
0x7B, /* gcc_usb30_phy_pipe_clk */
|
||||
0x79, /* gcc_usb30_sleep_clk */
|
||||
0x7C, /* gcc_usb3_phy_aux_clk */
|
||||
0x62, /* gcc_usb_hs_inactivity_timers_clk */
|
||||
0x64, /* gcc_usb_hs_phy_cfg_ahb_clk */
|
||||
0x60, /* gcc_usb_hs_system_clk */
|
||||
0x159, /* gcc_apss_tcu_clk */
|
||||
0x13A, /* gcc_crypto_ahb_clk */
|
||||
0x139, /* gcc_crypto_axi_clk */
|
||||
0x051, /* gcc_mdp_tbu_clk */
|
||||
0x049, /* gcc_qdss_dap_clk */
|
||||
0x0EC, /* gcc_geni_ir_h_clk */
|
||||
0x1B8, /* gcc_dcc_xo_clk */
|
||||
0x008, /* pnoc_clk */
|
||||
0xC0, /* qpic_clk */
|
||||
0x0, /* snoc_clk */
|
||||
0x15A, /* bimc_clk */
|
||||
0x138, /* ce1_clk */
|
||||
0x16A, /* apcs_debug_mux */
|
||||
};
|
||||
|
||||
static struct clk_debug_mux gcc_debug_mux = {
|
||||
.priv = &debug_mux_priv,
|
||||
.debug_offset = 0x74000,
|
||||
.post_div_offset = 0x74000,
|
||||
.cbcr_offset = 0x74000,
|
||||
.src_sel_mask = 0x1FF,
|
||||
.src_sel_shift = 0,
|
||||
.post_div_mask = 0xF000,
|
||||
.post_div_shift = 12,
|
||||
.post_div_val = 1,
|
||||
.en_mask = BIT(16),
|
||||
.mux_sels = gcc_debug_mux_sels,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_debug_mux",
|
||||
.ops = &clk_debug_mux_ops,
|
||||
.parent_names = gcc_debug_mux_parent_names,
|
||||
.num_parents = ARRAY_SIZE(gcc_debug_mux_parent_names),
|
||||
.flags = CLK_IS_MEASURE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct mux_regmap_names mux_list[] = {
|
||||
{ .mux = &gcc_debug_mux, .regmap_name = "qcom,gcc" },
|
||||
{ .mux = &apcs_debug_mux, .regmap_name = "qcom,cpucc" },
|
||||
};
|
||||
|
||||
static struct clk_dummy measure_only_apcs_clk = {
|
||||
.rrate = 1000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "measure_only_apcs_clk",
|
||||
.ops = &clk_dummy_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_hw *debugcc_qcs404_hws[] = {
|
||||
&measure_only_apcs_clk.hw,
|
||||
};
|
||||
|
||||
static const struct of_device_id clk_debug_match_table[] = {
|
||||
{ .compatible = "qcom,qcs404-debugcc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int clk_debug_qcs404_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk *clk;
|
||||
int ret, i;
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(gcc_debug_mux_parent_names) != ARRAY_SIZE(gcc_debug_mux_sels));
|
||||
BUILD_BUG_ON(ARRAY_SIZE(apcs_debug_mux_parent_names) != ARRAY_SIZE(apcs_debug_mux_sels));
|
||||
|
||||
clk = devm_clk_get(&pdev->dev, "xo_clk_src");
|
||||
if (IS_ERR(clk)) {
|
||||
if (PTR_ERR(clk) != -EPROBE_DEFER)
|
||||
dev_err(&pdev->dev, "Unable to get xo clock\n");
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
debug_mux_priv.cxo = clk;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
|
||||
if (IS_ERR_OR_NULL(mux_list[i].mux->regmap)) {
|
||||
ret = map_debug_bases(pdev,
|
||||
mux_list[i].regmap_name, mux_list[i].mux);
|
||||
if (ret == -EBADR)
|
||||
continue;
|
||||
else if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
|
||||
if (!mux_list[i].mux->regmap)
|
||||
continue;
|
||||
|
||||
clk = devm_clk_register(&pdev->dev, &mux_list[i].mux->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(&pdev->dev, "Unable to register mux clk %s, err:(%d)\n",
|
||||
clk_hw_get_name(&mux_list[i].mux->hw),
|
||||
PTR_ERR(clk));
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(debugcc_qcs404_hws); i++) {
|
||||
clk = devm_clk_register(&pdev->dev, debugcc_qcs404_hws[i]);
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n",
|
||||
clk_hw_get_name(debugcc_qcs404_hws[i]),
|
||||
PTR_ERR(clk));
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
}
|
||||
|
||||
ret = clk_debug_measure_register(&gcc_debug_mux.hw);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Could not register Measure clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "Registered debug measure clocks\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_debug_driver = {
|
||||
.probe = clk_debug_qcs404_probe,
|
||||
.driver = {
|
||||
.name = "qcs404-debugcc",
|
||||
.of_match_table = clk_debug_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init clk_debug_qcs404_init(void)
|
||||
{
|
||||
return platform_driver_register(&clk_debug_driver);
|
||||
}
|
||||
fs_initcall(clk_debug_qcs404_init);
|
||||
|
||||
MODULE_DESCRIPTION("QTI DEBUG CC QCS404 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue