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Merge "ARM: dts: msm: Remove PCIE clock from YUPIK IOT QRD"

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qctecmdr 2021-03-23 09:33:12 -07:00 • committed by Gerrit - the friendly Code Review server
commit 4c9855ef3c
1 changed files with 39 additions and 0 deletions
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39
qcom/yupik-iot-qrd.dtsi
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@ -1 +1,40 @@
#include "yupik-qrd.dtsi"
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-yupik.h>
&gcc {
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo", "sleep_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
protected-clocks = <GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <GCC_DDRSS_PCIE_SF_CLK>,
<GCC_PCIE0_PHY_RCHNG_CLK>, <GCC_PCIE1_PHY_RCHNG_CLK>,
<GCC_PCIE_0_AUX_CLK>, <GCC_PCIE_0_AUX_CLK_SRC>,
<GCC_PCIE_0_CFG_AHB_CLK>, <GCC_PCIE_0_MSTR_AXI_CLK>,
<GCC_PCIE_0_PHY_RCHNG_CLK_SRC>, <GCC_PCIE_0_PIPE_CLK>,
<GCC_PCIE_0_PIPE_CLK_SRC>, <GCC_PCIE_0_SLV_AXI_CLK>,
<GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <GCC_PCIE_1_AUX_CLK>,
<GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>,
<GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,
<GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,
<GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<GCC_PCIE_THROTTLE_CORE_CLK>, <GCC_THROTTLE_PCIE_AHB_CLK>,
<GCC_AGGRE_USB3_SEC_AXI_CLK>, <GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<GCC_USB30_SEC_MASTER_CLK>, <GCC_USB30_SEC_MASTER_CLK_SRC>,
<GCC_USB30_SEC_MOCK_UTMI_CLK>, <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>,
<GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>,
<GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>,
<GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>,
<GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
<GCC_AGGRE_NOC_PCIE_TBU_CLK>, <GCC_PCIE_CLKREF_EN>;
};
&gcc_pcie_0_gdsc {
status = "disabled";
};
&gcc_pcie_1_gdsc {
status = "disabled";
};