msm: kgsl: Disable gpu_llc flags by default

Set default value of flags gpu_llc_slice_enable and
gpuhtw_llc_slice_enable to false and disable change
via sysfs nodes.

Change-Id: I1446a04b25a793cdebf5428de2e84870a6b33b7c
Signed-off-by: Rohan Sethi <rohsethi@codeaurora.org>
This commit is contained in:
Rohan Sethi 2020-10-16 18:33:17 +05:30
commit 4cc9960429
3 changed files with 8 additions and 5 deletions

View file

@ -1239,6 +1239,8 @@ static int adreno_probe_llcc(struct adreno_device *adreno_dev,
"Unable to get the GPU LLC slice: %d\n", ret);
}
adreno_dev->gpu_llc_slice_enable = true;
/* Get the system cache slice descriptor for GPU pagetables */
adreno_dev->gpuhtw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
ret = PTR_ERR_OR_ZERO(adreno_dev->gpuhtw_llc_slice);
@ -1253,6 +1255,8 @@ static int adreno_probe_llcc(struct adreno_device *adreno_dev,
"Unable to get GPU HTW LLC slice: %d\n", ret);
}
adreno_dev->gpuhtw_llc_slice_enable = true;
return 0;
}

View file

@ -2134,9 +2134,6 @@ int a6xx_probe_common(struct platform_device *pdev,
adreno_dev->preempt.skipsaverestore = true;
adreno_dev->preempt.usesgmem = true;
adreno_dev->gpu_llc_slice_enable = true;
adreno_dev->gpuhtw_llc_slice_enable = true;
/* Set the GPU busy counter for frequency scaling */
adreno_dev->perfctr_pwr_lo = A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L;

View file

@ -49,7 +49,8 @@ static unsigned int _ft_pagefault_policy_show(struct adreno_device *adreno_dev)
static int _gpu_llc_slice_enable_store(struct adreno_device *adreno_dev,
bool val)
{
adreno_dev->gpu_llc_slice_enable = val;
if (!IS_ERR_OR_NULL(adreno_dev->gpu_llc_slice))
adreno_dev->gpu_llc_slice_enable = val;
return 0;
}
@ -61,7 +62,8 @@ static bool _gpu_llc_slice_enable_show(struct adreno_device *adreno_dev)
static int _gpuhtw_llc_slice_enable_store(struct adreno_device *adreno_dev,
bool val)
{
adreno_dev->gpuhtw_llc_slice_enable = val;
if (!IS_ERR_OR_NULL(adreno_dev->gpuhtw_llc_slice))
adreno_dev->gpuhtw_llc_slice_enable = val;
return 0;
}