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ARM: dts: msm: add entry for PCIe0 to manage PCIe PHY PLL on lahaina

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PCIe0 needs to manage PHY PLL on lahaina. Therefore add the DT
entries so that PCIe0 has to correct information to support this
request.

Change-Id: I622b4d3dc24e530554c23cbeeb0ee6dd528e5587
This commit is contained in:
Tony Truong 2020-04-28 17:05:44 -07:00 • committed by Gerrit - the friendly Code Review server
commit 4ce97d3889
1 changed files with 5 additions and 0 deletions
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5
qcom/lahaina-pcie.dtsi
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@ -109,6 +109,11 @@
qcom,slv-addr-space-size = <0x4000000>;
qcom,ep-latency = <10>;
qcom,phy-manage-pll = <1>;
qcom,phy-resetsm-cntrl2 = <0xa0>;
qcom,phy-core-pll-en-mux = <7>;
qcom,phy-c-ready-status = <0x178>;
qcom,pcie-phy-ver = <10971>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;