From 4e0ef92ec7833dcce9e460737bf78a1d61c7017b Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Mon, 27 Jan 2020 22:36:34 -0800 Subject: [PATCH] clk: qcom: clk-alpha-pll: Fix zonda set_rate failure when PLL is disabled Currently, clk_zonda_pll_set_rate polls for the PLL to lock even if the PLL is disabled. However, if the PLL is disabled then LOCK_DET will never assert and we'll return an error. There is no reason to poll LOCK_DET if the PLL is already disabled, so skip polling in this case. Change-Id: Iaea6460f3be58e1591ff49e025017b2c0b7e20ef Signed-off-by: Mike Tipton --- drivers/clk/qcom/clk-alpha-pll.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 4ee77f31051a..cdddd8159b3c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2016, 2018-2019, The Linux Foundation. + * Copyright (c) 2015-2016, 2018-2020, The Linux Foundation. * All rights reserved. */ @@ -1187,6 +1187,9 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + if (!clk_hw_is_enabled(hw)) + return 0; + /* Wait before polling for the frequency latch */ udelay(5);