From 4e5cad47bf9554ef9970208c832c8095bdfdf896 Mon Sep 17 00:00:00 2001
From: Saurabh Ambulkar <sambulka@qti.qualcomm.com>
Date: Wed, 19 Aug 2020 22:07:31 +0530
Subject: [PATCH] ARM: dts: msm: Add scm & scm-pas device on SDMSHRIKE

Add device nodes for scm & scm-pas for SDMSHRIKE SoC.
This is needed to secure memory buffers, and protect them
against unauthorized access.

Change-Id: Ia7d57cd3b2ef520839d46a77da64fd0aa2ca1d6a
---
 qcom/sdmshrike.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi
index 006a1d4bb2a2..f3ba2a28e8b3 100644
--- a/qcom/sdmshrike.dtsi
+++ b/qcom/sdmshrike.dtsi
@@ -503,6 +503,10 @@
 		compatible = "simple-bus";
 	};
 
+	qcom-secure-buffer {
+		compatible = "qcom,secure-buffer";
+	};
+
 	soc: soc { };
 };
 
@@ -665,6 +669,12 @@
 		qcom,rtb-size = <0x100000>;
 	};
 
+	pil_scm_pas {
+		compatible = "qcom,pil-tz-scm-pas";
+		interconnects = <&aggre2_noc MASTER_CRYPTO
+			&mc_virt SLAVE_EBI1>;
+	};
+
 	qcom,mpm2-sleep-counter@c221000 {
 		compatible = "qcom,mpm2-sleep-counter";
 		reg = <0xc221000 0x1000>;
@@ -1481,6 +1491,12 @@
 #include "sa8195-ssc-qupv3.dtsi"
 #include "sa8195-usb.dtsi"
 
+&firmware {
+	scm {
+		compatible = "qcom,scm";
+	};
+};
+
 &emac_gdsc {
 	status = "ok";
 };