From 4ea97bb26cf7f7567d913a66014dcebd454fa726 Mon Sep 17 00:00:00 2001
From: Nagireddy Annem <nannem@qti.qualcomm.com>
Date: Sat, 16 Jan 2021 10:54:37 +0530
Subject: [PATCH] ARM: dts: msm: Map more no of redistributors for monaco

As GIC is configured with more no of cores, So map all region
of available redistributor, change monaco soc id and also
correct syntax errors due to merge conflict.

Change-Id: I832e4e4de9e74b2cdf9a20d1224f8e9a5f3ab7eb
---
 qcom/monaco-rumi-overlay.dts | 2 +-
 qcom/monaco.dtsi             | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/qcom/monaco-rumi-overlay.dts b/qcom/monaco-rumi-overlay.dts
index 4f3bb6574696..05c56ab9fafa 100644
--- a/qcom/monaco-rumi-overlay.dts
+++ b/qcom/monaco-rumi-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Monaco RUMI";
 	compatible = "qcom,monaco-rumi", "qcom,monaco", "qcom,rumi";
-	qcom,msm-id = <459 0x10000>;
+	qcom,msm-id = <486 0x10000>;
 	qcom,board-id = <15 0>;
 };
diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi
index 61d0400287fc..4d93eb062b7c 100644
--- a/qcom/monaco.dtsi
+++ b/qcom/monaco.dtsi
@@ -252,7 +252,7 @@
 		#redistributor-regions = <1>;
 		redistributor-stride = <0x0 0x20000>;
 		reg = <0xf200000 0x10000>,     /* GICD */
-		      <0xf300000 0x80000>;    /* GICR * 4 */
+		      <0xf300000 0x100000>;    /* GICR * 8 */
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
@@ -783,7 +783,7 @@
 			interrupt-controller;
 			#interrupt-cells = <2>;
 		};
-	}
+	};
 
 	clk_virt: interconnect {
 		compatible = "qcom,monaco-clk_virt";
@@ -817,6 +817,7 @@
 };
 
 #include "monaco-pinctrl.dtsi"
+#include "msm-arm-smmu-monaco.dtsi"
 #include "monaco-ion.dtsi"
 #include "monaco-gdsc.dtsi"