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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add devicetree support for HSP (WCN6850)
Add devicetree changes for supporting HSP card (WCN6850). Change-Id: Ibeb7ccbe378338175e9f6027efc0a59b92d67c79
This commit is contained in:
Govind Singh
Gerrit - the friendly Code Review server
parent
60da1ce988
commit
4f062ac632
2 changed files with 217 additions and 0 deletions
208
qcom/qcx6490-cnss.dtsi
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208
qcom/qcx6490-cnss.dtsi
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@ -0,0 +1,208 @@
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&soc {
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wlan: qcom,cnss-qca6490@b0000000 {
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compatible = "qcom,cnss-qca6490";
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reg = <0xb0000000 0x10000>;
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reg-names = "smmu_iova_ipa";
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wlan-en-gpio = <&tlmm 84 0>;
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pinctrl-names = "wlan_en_active", "wlan_en_sleep";
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pinctrl-0 = <&cnss_wlan_en_active>;
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pinctrl-1 = <&cnss_wlan_en_sleep>;
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qcom,wlan-rc-num = <0>;
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qcom,wlan-ramdump-dynamic = <0x420000>;
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qcom,wlan-cbc-enabled;
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vdd-wlan-aon-supply = <&S7B>;
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qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>;
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vdd-wlan-dig-supply = <&S7B>;
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qcom,vdd-wlan-dig-config = <950000 952000 0 0 1>;
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vdd-wlan-io-supply = <&L19B>;
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qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
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vdd-wlan-rfa1-supply = <&S1B>;
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qcom,vdd-wlan-rfa1-config = <1880000 1880000 0 0 1>;
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vdd-wlan-rfa2-supply = <&S8B>;
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qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>;
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wlan-ant-switch-supply = <&L11C>;
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qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>;
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interconnects =
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<&aggre2_noc MASTER_PCIE_0 &aggre2_noc SLAVE_ANOC_PCIE_GEM_NOC>,
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<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
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interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
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qcom,icc-path-count = <2>;
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qcom,bus-bw-cfg-count = <7>;
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qcom,bus-bw-cfg =
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/** ICC Path 1 **/
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<0 0>, /* no vote */
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/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
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<2250 390000>,
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/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
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<7500 390000>,
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/* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
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<30000 790000>,
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/* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
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<100000 790000>,
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/* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */
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<175000 1600000>,
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/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
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* ddr: 547.2 MHz
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*/
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<7500 390000>,
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/** ICC Path 2 **/
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<0 0>,
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<2250 1804800>,
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<7500 1804800>,
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<30000 1804800>,
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<100000 1804800>,
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<175000 6220800>,
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<7500 2188800>;
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mhi,max-channels = <30>;
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mhi,timeout = <10000>;
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mhi,buffer-len = <0x8000>;
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mhi,m2-no-db-access;
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mhi_channels {
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#address-cells = <1>;
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#size-cells = <0>;
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mhi_chan@0 {
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reg = <0>;
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label = "LOOPBACK";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@1 {
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reg = <1>;
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label = "LOOPBACK";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@4 {
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reg = <4>;
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label = "DIAG";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@5 {
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reg = <5>;
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label = "DIAG";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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};
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mhi_chan@20 {
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reg = <20>;
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label = "IPCR";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <1>;
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mhi,data-type = <1>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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mhi,auto-start;
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};
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mhi_chan@21 {
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reg = <21>;
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label = "IPCR";
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mhi,num-elements = <32>;
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mhi,event-ring = <1>;
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mhi,chan-dir = <2>;
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mhi,data-type = <0>;
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mhi,doorbell-mode = <2>;
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mhi,ee = <0x14>;
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mhi,auto-queue;
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mhi,auto-start;
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};
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};
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mhi_events {
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mhi_event@0 {
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mhi,num-elements = <32>;
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mhi,intmod = <0>;
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mhi,msi = <1>;
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mhi,priority = <1>;
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mhi,brstmode = <2>;
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mhi,data-type = <1>;
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};
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mhi_event@1 {
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mhi,num-elements = <256>;
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mhi,intmod = <0>;
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mhi,msi = <2>;
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mhi,priority = <1>;
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mhi,brstmode = <2>;
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};
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mhi_event@2 {
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mhi,num-elements = <32>;
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mhi,intmod = <0>;
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mhi,msi = <0>;
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mhi,priority = <2>;
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mhi,brstmode = <2>;
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mhi,data-type = <3>;
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};
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};
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mhi_devices {
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mhi_qrtr {
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mhi,chan = "IPCR";
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qcom,net-id = <0>;
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qcom,low-latency;
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};
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};
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};
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};
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&pcie0_rp {
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#address-cells = <5>;
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#size-cells = <0>;
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cnss_pci: cnss_pci {
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reg = <0 0 0 0 0>;
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qcom,iommu-group = <&cnss_pci_iommu_group>;
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memory-region = <&cnss_wlan_mem>;
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#address-cells = <1>;
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#size-cells = <1>;
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cnss_pci_iommu_group: cnss_pci_iommu_group {
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qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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qcom,iommu-pagetable = "coherent";
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qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
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"non-fatal";
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};
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};
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};
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&pil_wpss {
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status = "disabled";
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};
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&icnss2 {
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status = "disabled";
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};
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@ -509,6 +509,15 @@
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reg = <0x0 0xe3300000 0x0 0x0100000>;
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label = "dfps_data_memory";
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};
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cnss_wlan_mem: cnss_wlan_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1400000>;
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};
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};
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&soc {
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