A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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msm: kgsl: Drive FAL QACTIVE signal high before GMU boot

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Drive FAL QACTIVE signal high before GMU boot to make sure
path to DDR accepts transactions from GMU/GPU and comes out
of low power state if it was in a low power state.

Change-Id: I238a39c5b9dbd10a8c9b2c6437aaf48df410802f
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
This commit is contained in:
Deepak Kumar 2020-08-29 00:46:40 +05:30
commit 4f125084c0
2 changed files with 5 additions and 1 deletions
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1
drivers/gpu/msm/a6xx_reg.h
View file

@ -1039,6 +1039,7 @@
/* FAL10 veto register */
#define A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x1F8F0
#define A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x1F8F1
#define A6XX_GMU_AO_INTERRUPT_EN 0x23B03
#define A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x23B04

5
drivers/gpu/msm/adreno_a6xx_gmu.c
View file

@ -1300,8 +1300,11 @@ static void a6xx_gmu_register_config(struct adreno_device *adreno_dev)
u32 gmu_log_info, chipid = 0;
/* Vote veto for FAL10 feature if supported*/
if (a6xx_core->veto_fal10)
if (a6xx_core->veto_fal10) {
gmu_core_regwrite(device, A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 0x1);
gmu_core_regwrite(device,
A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 0x1);
}
/* Turn on TCM retention */
gmu_core_regwrite(device, A6XX_GMU_GENERAL_7, 1);