From 4f9a6b9016c17d41176cd7ced4a023bdad5cbd1f Mon Sep 17 00:00:00 2001 From: Hariharan Basuthkar Date: Fri, 8 May 2020 19:04:56 +0530 Subject: [PATCH] qcacmn: Add max_bw field in struct regdomain When RD ETSI11 is configued, 5G HT40 channels are getting built for low band channel frequencies. As per regulatory update #31, this is not allowed. To fix this issue, add a new field max_bw that indicates the maximum supported bandwidth by a regdomain. Add max_bw values for all 2G and 5G regdomains definitions. Also pick bandwidth between reg-domain's max_bw and country's max_bw. Change-Id: Ie0e9f9c7d9ae21eea2bc534626ef7a13602577bb CRs-Fixed: 2682424 --- umac/regulatory/core/src/reg_db.c | 446 ++++++++++++----------- umac/regulatory/core/src/reg_db.h | 4 +- umac/regulatory/core/src/reg_db_parser.c | 28 +- 3 files changed, 258 insertions(+), 220 deletions(-) diff --git a/umac/regulatory/core/src/reg_db.c b/umac/regulatory/core/src/reg_db.c index 8b47d2f8fcf1..269f11bd0a03 100644 --- a/umac/regulatory/core/src/reg_db.c +++ b/umac/regulatory/core/src/reg_db.c @@ -1131,20 +1131,23 @@ const struct regulatory_rule reg_rules_2g[] = { const struct regdomain regdomains_2g[] = { - [FCCA] = {CTL_FCC, DFS_UNINIT_REGION, 0, 6, 1, {CHAN_1_11_1} }, - [FCCB] = {CTL_FCC, DFS_UNINIT_REGION, 0, 6, 1, {CHAN_1_11_3} }, - [WORLD] = {CTL_ETSI, DFS_UNINIT_REGION, 0, 0, 1, {CHAN_1_13_1} }, - [MKKA] = {CTL_MKK, DFS_UNINIT_REGION, 0, 0, 2, {CHAN_1_13_4, - CHAN_14_1} }, - [MKKC] = {CTL_MKK, DFS_UNINIT_REGION, 0, 0, 1, {CHAN_1_13_4} }, - [ETSIC] = {CTL_ETSI, DFS_UNINIT_REGION, 0, 0, 1, {CHAN_1_13_2} }, - [ETSID] = {CTL_ETSI, DFS_UNINIT_REGION, 0, 0, 1, {CHAN_1_13_5} }, - [KRRA] = {CTL_KOR, DFS_UNINIT_REGION, 0, 0, 1, {CHAN_1_13_4} }, - [WORLD_2G_1] = {CTL_NONE, DFS_UNINIT_REGION, 0, 0, 1, {CHAN_1_11_2} }, - [WORLD_2G_2] = {CTL_NONE, DFS_UNINIT_REGION, 0, 0, 2, - {CHAN_1_11_2, CHAN_12_13_1} }, - [WORLD_2G_3] = {CTL_NONE, DFS_UNINIT_REGION, 0, 0, 2, - {CHAN_1_11_2, CHAN_12_12_1} }, + [FCCA] = {CTL_FCC, DFS_UNINIT_REGION, 0, 40, 6, 1, {CHAN_1_11_1} }, + [FCCB] = {CTL_FCC, DFS_UNINIT_REGION, 0, 40, 6, 1, {CHAN_1_11_3} }, + [WORLD] = {CTL_ETSI, DFS_UNINIT_REGION, 0, 40, 0, 1, {CHAN_1_13_1} }, + [MKKA] = {CTL_MKK, DFS_UNINIT_REGION, 0, 40, 0, 2, {CHAN_1_13_4, + CHAN_14_1} }, + [MKKC] = {CTL_MKK, DFS_UNINIT_REGION, 0, 40, 0, 1, {CHAN_1_13_4} }, + [ETSIC] = {CTL_ETSI, DFS_UNINIT_REGION, 0, 40, 0, 1, {CHAN_1_13_2} }, + [ETSID] = {CTL_ETSI, DFS_UNINIT_REGION, 0, 20, 0, 1, {CHAN_1_13_5} }, + [KRRA] = {CTL_KOR, DFS_UNINIT_REGION, 0, 40, 0, 1, {CHAN_1_13_4} }, + [WORLD_2G_1] = {CTL_NONE, DFS_UNINIT_REGION, 0, 40, 0, 1, {CHAN_1_11_2} + }, + [WORLD_2G_2] = {CTL_NONE, DFS_UNINIT_REGION, 0, 40, 0, 2, {CHAN_1_11_2, + CHAN_12_13_1} + }, + [WORLD_2G_3] = {CTL_NONE, DFS_UNINIT_REGION, 0, 40, 0, 2, {CHAN_1_11_2, + CHAN_12_12_1} + }, }; @@ -1342,234 +1345,255 @@ const struct regulatory_rule reg_rules_5g[] = { const struct regdomain regdomains_5g[] = { - [FCC1] = {CTL_FCC, DFS_FCC_REGION, 2, 6, 3, {CHAN_5170_5250_1, - CHAN_5250_5330_1, - CHAN_5735_5835_2} }, + [FCC1] = {CTL_FCC, DFS_FCC_REGION, 2, 160, 6, 3, {CHAN_5170_5250_1, + CHAN_5250_5330_1, + CHAN_5735_5835_2} }, - [FCC2] = {CTL_FCC, DFS_FCC_REGION, 2, 6, 3, {CHAN_5170_5250_2, - CHAN_5250_5330_1, - CHAN_5735_5835_2} }, + [FCC2] = {CTL_FCC, DFS_FCC_REGION, 2, 160, 6, 3, {CHAN_5170_5250_2, + CHAN_5250_5330_1, + CHAN_5735_5835_2} }, - [FCC3] = {CTL_FCC, DFS_FCC_REGION, 2, 6, 4, {CHAN_5170_5250_5, - CHAN_5250_5330_7, - CHAN_5490_5730_1, - CHAN_5735_5835_2} }, + [FCC3] = {CTL_FCC, DFS_FCC_REGION, 2, 160, 6, 4, {CHAN_5170_5250_5, + CHAN_5250_5330_7, + CHAN_5490_5730_1, + CHAN_5735_5835_2} }, - [FCC4] = {CTL_FCC, DFS_FCC_REGION, 2, 6, 1, {CHAN_4940_4990_1} }, + [FCC4] = {CTL_FCC, DFS_FCC_REGION, 2, 20, 6, 1, {CHAN_4940_4990_1} }, - [FCC5] = {CTL_FCC, DFS_UNINIT_REGION, 2, 6, 2, {CHAN_5170_5250_4, - CHAN_5735_5835_2} }, + [FCC5] = {CTL_FCC, DFS_UNINIT_REGION, 2, 80, 6, 2, {CHAN_5170_5250_4, + CHAN_5735_5835_2} }, - [FCC6] = {CTL_FCC, DFS_FCC_REGION, 2, 6, 5, {CHAN_5170_5250_5, - CHAN_5250_5330_7, - CHAN_5490_5590_1, - CHAN_5650_5730_1, - CHAN_5735_5835_2} }, + [FCC6] = {CTL_FCC, DFS_FCC_REGION, 2, 160, 6, 5, {CHAN_5170_5250_5, + CHAN_5250_5330_7, + CHAN_5490_5590_1, + CHAN_5650_5730_1, + CHAN_5735_5835_2} }, - [FCC8] = {CTL_FCC, DFS_FCC_REGION, 2, 6, 4, {CHAN_5170_5250_4, - CHAN_5250_5330_7, - CHAN_5490_5730_1, - CHAN_5735_5835_2} }, + [FCC8] = {CTL_FCC, DFS_FCC_REGION, 2, 160, 6, 4, {CHAN_5170_5250_4, + CHAN_5250_5330_7, + CHAN_5490_5730_1, + CHAN_5735_5835_2} }, - [FCC10] = {CTL_FCC, DFS_FCC_REGION, 2, 0, 5, {CHAN_5170_5250_4, - CHAN_5250_5330_7, - CHAN_5490_5730_1, - CHAN_5735_5835_2, - CHAN_5850_5925_1} }, + [FCC10] = {CTL_FCC, DFS_FCC_REGION, 2, 160, 0, 5, {CHAN_5170_5250_4, + CHAN_5250_5330_7, + CHAN_5490_5730_1, + CHAN_5735_5835_2, + CHAN_5850_5925_1} }, - [FCC11] = {CTL_FCC, DFS_FCC_REGION, 2, 6, 4, {CHAN_5170_5250_5, - CHAN_5250_5330_7, - CHAN_5490_5650_2, - CHAN_5735_5835_6} }, + [FCC11] = {CTL_FCC, DFS_FCC_REGION, 2, 160, 6, 4, {CHAN_5170_5250_5, + CHAN_5250_5330_7, + CHAN_5490_5650_2, + CHAN_5735_5835_6} }, - [FCC13] = {CTL_FCC, DFS_UNINIT_REGION, 2, 0, 4, {CHAN_5170_5330_2, - CHAN_5250_5330_10, - CHAN_5490_5730_4, - CHAN_5735_5835_2} }, + [FCC13] = {CTL_FCC, DFS_UNINIT_REGION, 2, 160, 0, 4, {CHAN_5170_5330_2, + CHAN_5250_5330_10, + CHAN_5490_5730_4, + CHAN_5735_5835_2} + }, - [FCC14] = {CTL_FCC, DFS_UNINIT_REGION, 2, 0, 4, {CHAN_5170_5250_4, - CHAN_5250_5330_10, - CHAN_5490_5730_4, - CHAN_5735_5835_2} }, + [FCC14] = {CTL_FCC, DFS_UNINIT_REGION, 2, 160, 0, 4, {CHAN_5170_5250_4, + CHAN_5250_5330_10, + CHAN_5490_5730_4, + CHAN_5735_5835_2} + }, #ifdef CONFIG_BAND_6GHZ - [FCC15] = {CTL_FCC, DFS_FCC_REGION, 2, 0, 8, {CHAN_5170_5250_5, - CHAN_5250_5330_7, - CHAN_5490_5730_1, - CHAN_5735_5835_2, - CHAN_5935_6435_1, - CHAN_6435_6535_1, - CHAN_6535_6875_1, - CHAN_6875_7115_1} }, + [FCC15] = {CTL_FCC, DFS_FCC_REGION, 2, 160, 0, 8, {CHAN_5170_5250_5, + CHAN_5250_5330_7, + CHAN_5490_5730_1, + CHAN_5735_5835_2, + CHAN_5935_6435_1, + CHAN_6435_6535_1, + CHAN_6535_6875_1, + CHAN_6875_7115_1} }, - [FCC16] = {CTL_FCC, DFS_FCC_REGION, 2, 0, 8, {CHAN_5170_5250_4, - CHAN_5250_5330_7, - CHAN_5490_5730_1, - CHAN_5735_5835_2, - CHAN_5935_6435_2, - CHAN_6435_6535_2, - CHAN_6535_6875_2, - CHAN_6875_7115_2} }, + [FCC16] = {CTL_FCC, DFS_FCC_REGION, 2, 160, 0, 8, {CHAN_5170_5250_4, + CHAN_5250_5330_7, + CHAN_5490_5730_1, + CHAN_5735_5835_2, + CHAN_5935_6435_2, + CHAN_6435_6535_2, + CHAN_6535_6875_2, + CHAN_6875_7115_2} }, - [FCC17] = {CTL_FCC, DFS_FCC_REGION, 2, 0, 6, {CHAN_5170_5250_4, - CHAN_5250_5330_7, - CHAN_5490_5730_1, - CHAN_5735_5835_2, - CHAN_5935_6435_2, - CHAN_6535_6875_2} }, + [FCC17] = {CTL_FCC, DFS_FCC_REGION, 2, 160, 0, 6, {CHAN_5170_5250_4, + CHAN_5250_5330_7, + CHAN_5490_5730_1, + CHAN_5735_5835_2, + CHAN_5935_6435_2, + CHAN_6535_6875_2} }, #endif + [ETSI1] = {CTL_ETSI, DFS_ETSI_REGION, 2, 160, 0, 3, {CHAN_5170_5250_8, + CHAN_5250_5330_12, + CHAN_5490_5710_1} + }, - [ETSI1] = {CTL_ETSI, DFS_ETSI_REGION, 2, 0, 3, {CHAN_5170_5250_8, - CHAN_5250_5330_12, - CHAN_5490_5710_1} }, + [ETSI3] = {CTL_ETSI, DFS_ETSI_REGION, 5, 160, 0, 2, {CHAN_5170_5250_2, + CHAN_5250_5330_1} + }, - [ETSI3] = {CTL_ETSI, DFS_ETSI_REGION, 5, 0, 2, {CHAN_5170_5250_2, - CHAN_5250_5330_1} }, + [ETSI4] = {CTL_ETSI, DFS_ETSI_REGION, 2, 160, 0, 2, {CHAN_5170_5250_6, + CHAN_5250_5330_3} + }, - [ETSI4] = {CTL_ETSI, DFS_ETSI_REGION, 2, 0, 2, {CHAN_5170_5250_6, - CHAN_5250_5330_3} }, - - [ETSI8] = {CTL_ETSI, DFS_UNINIT_REGION, 20, 0, 4, {CHAN_5170_5250_2, - CHAN_5250_5330_5, - CHAN_5490_5730_3, - CHAN_5735_5835_2} }, - - [ETSI9] = {CTL_ETSI, DFS_ETSI_REGION, 20, 0, 4, {CHAN_5170_5250_2, - CHAN_5250_5330_1, - CHAN_5490_5710_5, - CHAN_5735_5835_6} }, - - [ETSI10] = {CTL_ETSI, DFS_ETSI_REGION, 10, 0, 4, {CHAN_5170_5250_7, - CHAN_5250_5330_14, - CHAN_5490_5710_3, - CHAN_5850_5925_2} }, - - [ETSI11] = {CTL_ETSI, DFS_ETSI_REGION, 10, 0, 4, {CHAN_5170_5250_10, - CHAN_5250_5330_15, - CHAN_5490_5710_8, - CHAN_5735_5875_1} }, - - [ETSI12] = {CTL_ETSI, DFS_ETSI_REGION, 2, 0, 4, {CHAN_5170_5250_7, - CHAN_5250_5330_14, - CHAN_5490_5730_6, - CHAN_5735_5835_8} }, - - [ETSI13] = {CTL_ETSI, DFS_ETSI_REGION, 2, 0, 4, {CHAN_5170_5250_8, - CHAN_5250_5330_12, - CHAN_5490_5730_5, - CHAN_5735_5875_4} }, - - [ETSI14] = {CTL_ETSI, DFS_ETSI_REGION, 2, 0, 4, {CHAN_5170_5250_2, - CHAN_5250_5330_1, - CHAN_5490_5730_7, - CHAN_5735_5875_5} }, - - [ETSI15] = {CTL_ETSI, DFS_ETSI_REGION, 2, 0, 4, {CHAN_5170_5250_2, - CHAN_5250_5330_1, - CHAN_5490_5730_5, - CHAN_5735_5815_2} }, - - [APL1] = {CTL_ETSI, DFS_UNINIT_REGION, 2, 0, 1, {CHAN_5735_5835_2} }, - - [APL2] = {CTL_ETSI, DFS_UNINIT_REGION, 2, 0, 1, {CHAN_5735_5815_4} }, - - [APL4] = {CTL_ETSI, DFS_UNINIT_REGION, 2, 0, 2, {CHAN_5170_5250_2, - CHAN_5735_5835_1} }, - - [APL6] = {CTL_ETSI, DFS_ETSI_REGION, 2, 0, 3, {CHAN_5170_5250_3, - CHAN_5250_5330_2, - CHAN_5735_5835_3} }, - - [APL8] = {CTL_FCC, DFS_ETSI_REGION, 2, 0, 2, {CHAN_5250_5330_4, - CHAN_5735_5835_2} }, - - [APL9] = {CTL_MKK, DFS_KR_REGION, 2, 6, 4, {CHAN_5170_5250_2, - CHAN_5250_5330_1, - CHAN_5490_5730_6, - CHAN_5735_5835_1} }, - - [APL10] = {CTL_ETSI, DFS_FCC_REGION, 2, 6, 4, {CHAN_5170_5250_2, - CHAN_5250_5330_4, - CHAN_5490_5710_1, - CHAN_5735_5815_1} }, - - [APL11] = { CTL_ETSI, DFS_FCC_REGION, 2, 0, 4, {CHAN_5170_5250_9, - CHAN_5250_5330_13, - CHAN_5490_5710_4, - CHAN_5735_5875_2} }, - - [APL12] = {CTL_ETSI, DFS_ETSI_REGION, 2, 0, 3, {CHAN_5170_5250_2, - CHAN_5490_5570_1, - CHAN_5735_5775_1} }, - - [APL13] = {CTL_ETSI, DFS_ETSI_REGION, 2, 0, 3, {CHAN_5170_5250_2, - CHAN_5250_5330_1, - CHAN_5490_5670_2} }, - - [APL14] = {CTL_MKK, DFS_CN_REGION, 2, 0, 3, {CHAN_5170_5250_2, - CHAN_5250_5330_1, - CHAN_5735_5835_4} }, - - [APL15] = {CTL_FCC, DFS_UNINIT_REGION, 2, 0, 3, {CHAN_5170_5250_8, - CHAN_5250_5330_16, - CHAN_5735_5835_4} }, - - [APL16] = {CTL_FCC, DFS_UNINIT_REGION, 2, 0, 5, {CHAN_5170_5250_1, - CHAN_5250_5330_6, - CHAN_5490_5590_2, - CHAN_5650_5730_2, + [ETSI8] = {CTL_ETSI, DFS_UNINIT_REGION, 20, 160, 0, 4, + {CHAN_5170_5250_2, + CHAN_5250_5330_5, + CHAN_5490_5730_3, CHAN_5735_5835_2} }, - [APL17] = {CTL_FCC, DFS_UNINIT_REGION, 2, 0, 5, {CHAN_5170_5250_2, - CHAN_5250_5330_8, - CHAN_5490_5590_3, - CHAN_5650_5730_3, - CHAN_5735_5835_7} }, + [ETSI9] = {CTL_ETSI, DFS_ETSI_REGION, 20, 160, 0, 4, {CHAN_5170_5250_2, + CHAN_5250_5330_1, + CHAN_5490_5710_5, + CHAN_5735_5835_6} + }, - [APL19] = {CTL_FCC, DFS_FCC_REGION, 2, 0, 4, {CHAN_5170_5250_4, - CHAN_5250_5330_7, - CHAN_5490_5730_1, - CHAN_5735_5875_3} }, + [ETSI10] = {CTL_ETSI, DFS_ETSI_REGION, 10, 160, 0, 4, + {CHAN_5170_5250_7, + CHAN_5250_5330_14, + CHAN_5490_5710_3, + CHAN_5850_5925_2} }, - [APL20] = {CTL_ETSI, DFS_ETSI_REGION, 2, 0, 4, {CHAN_5170_5250_8, - CHAN_5250_5330_12, - CHAN_5490_5730_5, - CHAN_5735_5835_4} }, + [ETSI11] = {CTL_ETSI, DFS_ETSI_REGION, 10, 20, 0, 4, {CHAN_5170_5250_7, + CHAN_5250_5330_14, + CHAN_5490_5710_3, + CHAN_5735_5875_1} + }, - [APL23] = {CTL_ETSI, DFS_UNINIT_REGION, 2, 0, 3, {CHAN_5170_5250_7, - CHAN_5250_5330_11, - CHAN_5735_5835_3} }, + [ETSI12] = {CTL_ETSI, DFS_ETSI_REGION, 2, 160, 0, 4, {CHAN_5170_5250_7, + CHAN_5250_5330_14, + CHAN_5490_5730_6, + CHAN_5735_5835_8} + }, - [APL24] = {CTL_ETSI, DFS_ETSI_REGION, 2, 0, 3, {CHAN_5170_5250_8, - CHAN_5250_5330_12, - CHAN_5735_5815_3} }, + [ETSI13] = {CTL_ETSI, DFS_ETSI_REGION, 2, 160, 0, 4, {CHAN_5170_5250_8, + CHAN_5250_5330_12, + CHAN_5490_5730_5, + CHAN_5735_5875_4} + }, - [MKK3] = {CTL_MKK, DFS_UNINIT_REGION, 2, 0, 1, {CHAN_5170_5250_3} }, + [ETSI14] = {CTL_ETSI, DFS_ETSI_REGION, 2, 160, 0, 4, {CHAN_5170_5250_2, + CHAN_5250_5330_1, + CHAN_5490_5730_7, + CHAN_5735_5875_5} + }, - [MKK5] = {CTL_MKK, DFS_MKK_REGION, 2, 0, 3, {CHAN_5170_5250_8, - CHAN_5250_5330_12, - CHAN_5490_5710_7} }, + [ETSI15] = {CTL_ETSI, DFS_ETSI_REGION, 2, 160, 0, 4, {CHAN_5170_5250_2, + CHAN_5250_5330_1, + CHAN_5490_5730_5, + CHAN_5735_5815_2} + }, - [MKK11] = {CTL_MKK, DFS_MKK_REGION, 2, 0, 5, {CHAN_4910_4990_1, - CHAN_5170_5250_2, - CHAN_5030_5090_1, - CHAN_5250_5330_1, - CHAN_5490_5710_7} }, + [APL1] = {CTL_ETSI, DFS_UNINIT_REGION, 2, 80, 0, 1, {CHAN_5735_5835_2} + }, - [MKK16] = {CTL_MKK, DFS_MKK_REGION, 2, 0, 1, {CHAN_5490_5710_6} }, + [APL2] = {CTL_ETSI, DFS_UNINIT_REGION, 2, 20, 0, 1, {CHAN_5735_5815_4} + }, - [MKK17] = {CTL_MKK, DFS_MKKN_REGION, 2, 0, 3, {CHAN_5170_5250_8, - CHAN_5250_5330_12, - CHAN_5490_5730_6} }, + [APL4] = {CTL_ETSI, DFS_UNINIT_REGION, 2, 80, 0, 2, {CHAN_5170_5250_2, + CHAN_5735_5835_1} + }, - [WORLD_5G_1] = {CTL_NONE, DFS_UNINIT_REGION, 2, 0, 2, - {CHAN_5170_5330_1, - CHAN_5735_5835_5} }, + [APL6] = {CTL_ETSI, DFS_ETSI_REGION, 2, 160, 0, 3, {CHAN_5170_5250_3, + CHAN_5250_5330_2, + CHAN_5735_5835_3} }, - [WORLD_5G_2] = {CTL_NONE, DFS_UNINIT_REGION, 2, 0, 3, - {CHAN_5170_5330_1, - CHAN_5490_5730_2, - CHAN_5735_5835_5} }, + [APL8] = {CTL_FCC, DFS_ETSI_REGION, 2, 80, 0, 2, {CHAN_5250_5330_4, + CHAN_5735_5835_2} }, + + [APL9] = {CTL_MKK, DFS_KR_REGION, 2, 160, 6, 4, {CHAN_5170_5250_2, + CHAN_5250_5330_1, + CHAN_5490_5730_6, + CHAN_5735_5835_1} }, + + [APL10] = {CTL_ETSI, DFS_FCC_REGION, 2, 160, 6, 4, {CHAN_5170_5250_2, + CHAN_5250_5330_4, + CHAN_5490_5710_1, + CHAN_5735_5815_1} }, + + [APL11] = { CTL_ETSI, DFS_FCC_REGION, 2, 40, 0, 4, {CHAN_5170_5250_9, + CHAN_5250_5330_13, + CHAN_5490_5710_4, + CHAN_5735_5875_2} }, + + [APL12] = {CTL_ETSI, DFS_ETSI_REGION, 2, 80, 0, 3, {CHAN_5170_5250_2, + CHAN_5490_5570_1, + CHAN_5735_5775_1} }, + + [APL13] = {CTL_ETSI, DFS_ETSI_REGION, 2, 160, 0, 3, {CHAN_5170_5250_2, + CHAN_5250_5330_1, + CHAN_5490_5670_2} + }, + + [APL14] = {CTL_MKK, DFS_CN_REGION, 2, 160, 0, 3, {CHAN_5170_5250_2, + CHAN_5250_5330_1, + CHAN_5735_5835_4} }, + + [APL15] = {CTL_FCC, DFS_UNINIT_REGION, 2, 160, 0, 3, {CHAN_5170_5250_2, + CHAN_5250_5330_5, + CHAN_5735_5835_4} + }, + + [APL16] = {CTL_FCC, DFS_UNINIT_REGION, 2, 160, 0, 5, {CHAN_5170_5250_1, + CHAN_5250_5330_6, + CHAN_5490_5590_2, + CHAN_5650_5730_2, + CHAN_5735_5835_2} + }, + + [APL17] = {CTL_FCC, DFS_UNINIT_REGION, 2, 160, 0, 5, {CHAN_5170_5250_2, + CHAN_5250_5330_8, + CHAN_5490_5590_3, + CHAN_5650_5730_3, + CHAN_5735_5835_7} + }, + + [APL19] = {CTL_FCC, DFS_FCC_REGION, 2, 160, 0, 4, {CHAN_5170_5250_4, + CHAN_5250_5330_7, + CHAN_5490_5730_1, + CHAN_5735_5875_3} }, + + [APL20] = {CTL_ETSI, DFS_ETSI_REGION, 2, 160, 0, 4, {CHAN_5170_5250_8, + CHAN_5250_5330_12, + CHAN_5490_5730_5, + CHAN_5735_5835_4} + }, + + [APL23] = {CTL_ETSI, DFS_UNINIT_REGION, 2, 160, 0, 3, + {CHAN_5170_5250_7, + CHAN_5250_5330_11, + CHAN_5735_5835_3} }, + + [APL24] = {CTL_ETSI, DFS_ETSI_REGION, 2, 80, 0, 3, {CHAN_5170_5250_8, + CHAN_5250_5330_12, + CHAN_5735_5815_3} }, + + [MKK3] = {CTL_MKK, DFS_UNINIT_REGION, 2, 80, 0, 1, {CHAN_5170_5250_3} }, + + [MKK5] = {CTL_MKK, DFS_MKK_REGION, 2, 160, 0, 3, {CHAN_5170_5250_8, + CHAN_5250_5330_12, + CHAN_5490_5710_7} }, + + [MKK11] = {CTL_MKK, DFS_MKK_REGION, 2, 160, 0, 5, {CHAN_4910_4990_1, + CHAN_5170_5250_2, + CHAN_5030_5090_1, + CHAN_5250_5330_1, + CHAN_5490_5710_7} }, + + [MKK16] = {CTL_MKK, DFS_MKK_REGION, 2, 160, 0, 1, {CHAN_5490_5710_6} }, + + [MKK17] = {CTL_MKK, DFS_MKKN_REGION, 2, 160, 0, 3, {CHAN_5170_5250_8, + CHAN_5250_5330_12, + CHAN_5490_5730_6} }, + + [WORLD_5G_1] = {CTL_NONE, DFS_UNINIT_REGION, 2, 160, 0, 2, + {CHAN_5170_5330_1, + CHAN_5735_5835_5} }, + + [WORLD_5G_2] = {CTL_NONE, DFS_UNINIT_REGION, 2, 160, 0, 3, + {CHAN_5170_5330_1, + CHAN_5490_5730_2, + CHAN_5735_5835_5} }, }; #ifdef CONFIG_REG_CLIENT diff --git a/umac/regulatory/core/src/reg_db.h b/umac/regulatory/core/src/reg_db.h index b07c14339a64..4a026c2caea5 100644 --- a/umac/regulatory/core/src/reg_db.h +++ b/umac/regulatory/core/src/reg_db.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * * Permission to use, copy, modify, and/or distribute this software for @@ -49,6 +49,7 @@ struct regulatory_rule { * @ctl_val: CTL value * @dfs_region: dfs region * @min_bw: minimum bandwidth + * @max_bw: maximum bandwidth * @num_reg_rules: number of regulatory rules * @reg_rules_id: regulatory rule index */ @@ -56,6 +57,7 @@ struct regdomain { uint8_t ctl_val; enum dfs_reg dfs_region; uint16_t min_bw; + uint16_t max_bw; uint8_t ant_gain; uint8_t num_reg_rules; uint8_t reg_rule_id[MAX_REG_RULES]; diff --git a/umac/regulatory/core/src/reg_db_parser.c b/umac/regulatory/core/src/reg_db_parser.c index 3d993a1357ed..3cff4ca52b0d 100644 --- a/umac/regulatory/core/src/reg_db_parser.c +++ b/umac/regulatory/core/src/reg_db_parser.c @@ -189,7 +189,7 @@ QDF_STATUS reg_get_rdpair_from_country_code(uint16_t cc, return QDF_STATUS_SUCCESS; } -static inline QDF_STATUS reg_get_reginfo_form_country_code_and_regdmn_pair( +static inline QDF_STATUS reg_get_reginfo_from_country_code_and_regdmn_pair( struct cur_regulatory_info *reg_info, uint16_t country_index, uint16_t regdmn_pair) @@ -220,9 +220,21 @@ static inline QDF_STATUS reg_get_reginfo_form_country_code_and_regdmn_pair( reg_info->dfs_region = regdomains_5g[dmn_id_5g].dfs_region; reg_info->phybitmap = g_all_countries[country_index].phymode_bitmap; + if (g_all_countries[country_index].max_bw_2g < + regdomains_2g[dmn_id_2g].max_bw) + reg_info->max_bw_2g = + g_all_countries[country_index].max_bw_2g; + else + reg_info->max_bw_2g = + regdomains_2g[dmn_id_2g].max_bw; - reg_info->max_bw_2g = g_all_countries[country_index].max_bw_2g; - reg_info->max_bw_5g = g_all_countries[country_index].max_bw_5g; + if (g_all_countries[country_index].max_bw_5g < + regdomains_5g[dmn_id_5g].max_bw) + reg_info->max_bw_5g = + g_all_countries[country_index].max_bw_5g; + else + reg_info->max_bw_5g = + regdomains_5g[dmn_id_5g].max_bw; reg_info->min_bw_2g = regdomains_2g[dmn_id_2g].min_bw; reg_info->min_bw_5g = regdomains_5g[dmn_id_5g].min_bw; @@ -304,7 +316,7 @@ reg_update_alpha2_from_domain(struct cur_regulatory_info *reg_info) } #endif -static inline QDF_STATUS reg_get_reginfo_form_regdmn_pair( +static inline QDF_STATUS reg_get_reginfo_from_regdmn_pair( struct cur_regulatory_info *reg_info, uint16_t regdmn_pair) { @@ -334,8 +346,8 @@ static inline QDF_STATUS reg_get_reginfo_form_regdmn_pair( reg_info->dfs_region = regdomains_5g[dmn_id_5g].dfs_region; reg_info->phybitmap = 0; - reg_info->max_bw_2g = 40; - reg_info->max_bw_5g = 160; + reg_info->max_bw_2g = regdomains_2g[dmn_id_2g].max_bw; + reg_info->max_bw_5g = regdomains_5g[dmn_id_5g].max_bw; reg_info->min_bw_2g = regdomains_2g[dmn_id_2g].min_bw; reg_info->min_bw_5g = regdomains_5g[dmn_id_5g].min_bw; @@ -377,10 +389,10 @@ QDF_STATUS reg_get_cur_reginfo(struct cur_regulatory_info *reg_info, { if ((country_index != (uint16_t)(-1)) && (regdmn_pair != (uint16_t)(-1))) - return reg_get_reginfo_form_country_code_and_regdmn_pair( + return reg_get_reginfo_from_country_code_and_regdmn_pair( reg_info, country_index, regdmn_pair); else if (regdmn_pair != (uint16_t)(-1)) - return reg_get_reginfo_form_regdmn_pair(reg_info, regdmn_pair); + return reg_get_reginfo_from_regdmn_pair(reg_info, regdmn_pair); else return QDF_STATUS_E_FAILURE;