mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 15:49:17 -04:00
ARM: dts: msm: snapshot change for lahaina target
This snapshot change brings all the device tree entries for lahaina display driver. Change-Id: I3677b0227c3330d2d4bfe09172ffae519883fac2
This commit is contained in:
Narendra Muppalla
Gerrit - the friendly Code Review server
parent
1ae72cca20
commit
50c6b08a4f
8 changed files with 2146 additions and 0 deletions
155
display/lahaina-sde-display-cdp-lcd.dtsi
Normal file
155
display/lahaina-sde-display-cdp-lcd.dtsi
Normal file
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@ -0,0 +1,155 @@
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&dsi_sharp_4k_dsc_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
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qcom,esd-check-enabled;
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qcom,mdss-dsi-panel-status-check-mode = "reg_read";
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qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
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qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
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qcom,mdss-dsi-panel-status-value = <0x77>;
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qcom,mdss-dsi-panel-on-check-value = <0x77>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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/delete-property/ qcom,platform-en-gpio;
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};
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&dsi_sharp_4k_dsc_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
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qcom,esd-check-enabled;
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qcom,mdss-dsi-panel-status-check-mode = "reg_read";
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qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
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qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
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qcom,mdss-dsi-panel-status-value = <0x77>;
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qcom,mdss-dsi-panel-on-check-value = <0x77>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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qcom,mdss-dsi-qsync-min-refresh-rate = <55>;
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/delete-property/ qcom,platform-en-gpio;
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};
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&dsi_sharp_qsync_wqhd_cmd {
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qcom,esd-check-enabled;
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qcom,mdss-dsi-panel-status-check-mode = "reg_read";
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qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
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qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
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qcom,mdss-dsi-panel-status-value = <0x9c>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
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/delete-property/ qcom,platform-en-gpio;
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};
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&dsi_sharp_qsync_wqhd_video {
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qcom,esd-check-enabled;
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qcom,mdss-dsi-panel-status-check-mode = "reg_read";
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qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
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qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
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qcom,mdss-dsi-panel-status-value = <0x9c>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
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/delete-property/ qcom,platform-en-gpio;
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};
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&dsi_sharp_1080_cmd {
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qcom,esd-check-enabled;
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qcom,mdss-dsi-panel-status-check-mode = "reg_read";
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qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
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qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
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qcom,mdss-dsi-panel-status-value = <0x9c>;
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qcom,mdss-dsi-panel-on-check-value = <0x9c>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
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};
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&dsi_dual_nt35597_truly_cmd {
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qcom,esd-check-enabled;
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qcom,mdss-dsi-panel-status-check-mode = "reg_read";
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qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
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qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
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qcom,mdss-dsi-panel-status-value = <0x9c>;
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qcom,mdss-dsi-panel-on-check-value = <0x9c>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
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};
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&dsi_dual_nt35597_truly_video {
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qcom,esd-check-enabled;
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qcom,mdss-dsi-panel-status-check-mode = "reg_read";
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qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
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qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
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qcom,mdss-dsi-panel-status-value = <0x9c>;
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qcom,mdss-dsi-panel-on-check-value = <0x9c>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
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};
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&dsi_nt35695b_truly_fhd_cmd {
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qcom,esd-check-enabled;
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qcom,mdss-dsi-panel-status-check-mode = "reg_read";
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qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
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qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
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qcom,mdss-dsi-panel-status-value = <0x9c>;
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qcom,mdss-dsi-panel-on-check-value = <0x9c>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
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};
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&dsi_nt35695b_truly_fhd_video {
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qcom,esd-check-enabled;
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qcom,mdss-dsi-panel-status-check-mode = "reg_read";
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qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
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qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
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qcom,mdss-dsi-panel-status-value = <0x9c>;
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qcom,mdss-dsi-panel-on-check-value = <0x9c>;
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qcom,mdss-dsi-panel-status-read-length = <1>;
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
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};
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&dsi_sim_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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};
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&dsi_sim_vid {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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};
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&dsi_sim_dsc_375_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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};
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&dsi_sim_dsc_10b_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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};
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&dsi_dual_sim_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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};
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&dsi_dual_sim_vid {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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};
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&dsi_dual_sim_dsc_375_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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};
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&dsi_sim_sec_hd_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
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qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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};
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&sde_dsi {
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/delete-property/ avdd-supply;
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lab-supply = <&lcdb_ldo_vreg>;
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ibb-supply = <&lcdb_ncp_vreg>;
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qcom,dsi-default-panel = <&dsi_sharp_4k_dsc_cmd>;
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};
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&sde_dsi1 {
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lab-supply = <&lcdb_ldo_vreg>;
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ibb-supply = <&lcdb_ncp_vreg>;
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};
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174
display/lahaina-sde-display-cdp.dtsi
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174
display/lahaina-sde-display-cdp.dtsi
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@ -0,0 +1,174 @@
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#include "kona-sde-display.dtsi"
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&dsi_sw43404_amoled_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <1023>;
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qcom,mdss-brightness-max-level = <255>;
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qcom,platform-te-gpio = <&tlmm 66 0>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
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};
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&dsi_sw43404_amoled_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <1023>;
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qcom,mdss-brightness-max-level = <255>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
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};
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&dsi_sw43404_amoled_fhd_plus_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <1023>;
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qcom,mdss-brightness-max-level = <255>;
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qcom,platform-te-gpio = <&tlmm 66 0>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
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};
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&dsi_sharp_4k_dsc_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-te-gpio = <&tlmm 66 0>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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qcom,platform-en-gpio = <&tlmm 60 0>;
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};
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&dsi_sharp_4k_dsc_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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qcom,platform-en-gpio = <&tlmm 60 0>;
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};
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&dsi_sharp_qsync_wqhd_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-te-gpio = <&tlmm 66 0>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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qcom,platform-en-gpio = <&tlmm 60 0>;
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};
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&dsi_sharp_qsync_wqhd_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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qcom,platform-en-gpio = <&tlmm 60 0>;
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};
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&dsi_sharp_1080_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-te-gpio = <&tlmm 66 0>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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};
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&dsi_dual_nt35597_truly_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-te-gpio = <&tlmm 66 0>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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};
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&dsi_dual_nt35597_truly_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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};
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&dsi_nt35695b_truly_fhd_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-te-gpio = <&tlmm 66 0>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
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};
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&dsi_nt35695b_truly_fhd_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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};
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&dsi_sim_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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};
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&dsi_sim_vid {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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};
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&dsi_sim_dsc_375_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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};
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&dsi_sim_dsc_10b_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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};
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&dsi_dual_sim_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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};
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&dsi_dual_sim_vid {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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};
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&dsi_dual_sim_dsc_375_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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};
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&dsi_sim_sec_hd_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <1023>;
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qcom,platform-reset-gpio = <&tlmm 75 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
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};
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|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
|
||||
};
|
||||
90
display/lahaina-sde-display-mtp.dtsi
Normal file
90
display/lahaina-sde-display-mtp.dtsi
Normal file
|
|
@ -0,0 +1,90 @@
|
|||
#include "kona-sde-display.dtsi"
|
||||
|
||||
&dsi_sw43404_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
qcom,mdss-brightness-max-level = <255>;
|
||||
qcom,platform-te-gpio = <&tlmm 66 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
|
||||
};
|
||||
|
||||
&dsi_sw43404_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
qcom,mdss-brightness-max-level = <255>;
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
|
||||
};
|
||||
|
||||
&dsi_sw43404_amoled_fhd_plus_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
qcom,mdss-brightness-max-level = <255>;
|
||||
qcom,platform-te-gpio = <&tlmm 66 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
|
||||
};
|
||||
79
display/lahaina-sde-display-qrd.dtsi
Normal file
79
display/lahaina-sde-display-qrd.dtsi
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
#include "kona-sde-display.dtsi"
|
||||
|
||||
&dsi_sw43404_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
qcom,mdss-brightness-max-level = <255>;
|
||||
qcom,platform-te-gpio = <&tlmm 66 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
|
||||
};
|
||||
|
||||
&dsi_sw43404_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
qcom,mdss-brightness-max-level = <255>;
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
|
||||
};
|
||||
|
||||
&dsi_sw43404_amoled_fhd_plus_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
qcom,mdss-brightness-max-level = <255>;
|
||||
qcom,platform-te-gpio = <&tlmm 66 0>;
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 75 0>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
|
||||
};
|
||||
1
display/lahaina-sde-display-rumi.dtsi
Normal file
1
display/lahaina-sde-display-rumi.dtsi
Normal file
|
|
@ -0,0 +1 @@
|
|||
#include "kona-sde-display.dtsi"
|
||||
852
display/lahaina-sde-display.dtsi
Normal file
852
display/lahaina-sde-display.dtsi
Normal file
|
|
@ -0,0 +1,852 @@
|
|||
#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"
|
||||
#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"
|
||||
#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi"
|
||||
#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
|
||||
#include "dsi-panel-sharp-dsc-4k-video.dtsi"
|
||||
#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi"
|
||||
#include "dsi-panel-sharp-qsync-wqhd-video.dtsi"
|
||||
#include "dsi-panel-sharp-1080p-cmd.dtsi"
|
||||
#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
|
||||
#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
|
||||
#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
|
||||
#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
|
||||
#include "dsi-panel-ext-bridge-1080p.dtsi"
|
||||
#include "dsi-panel-sim-cmd.dtsi"
|
||||
#include "dsi-panel-sim-video.dtsi"
|
||||
#include "dsi-panel-sim-dsc375-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dsc-10bit-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dualmipi-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dualmipi-video.dtsi"
|
||||
#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
|
||||
#include "dsi-panel-sim-sec-hd-cmd.dtsi"
|
||||
#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
|
||||
|
||||
&tlmm {
|
||||
display_panel_avdd_default: display_panel_avdd_default {
|
||||
mux {
|
||||
pins = "gpio61";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio61";
|
||||
drive-strength = <8>;
|
||||
bias-disable = <0>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
ext_disp: qcom,msm-ext-disp {
|
||||
compatible = "qcom,msm-ext-disp";
|
||||
|
||||
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
|
||||
compatible = "qcom,msm-ext-disp-audio-codec-rx";
|
||||
};
|
||||
};
|
||||
|
||||
dsi_panel_pwr_supply: dsi_panel_pwr_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <62000>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "vdd";
|
||||
qcom,supply-min-voltage = <3300000>;
|
||||
qcom,supply-max-voltage = <3300000>;
|
||||
qcom,supply-enable-load = <857000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@2 {
|
||||
reg = <2>;
|
||||
qcom,supply-name = "lab";
|
||||
qcom,supply-min-voltage = <4600000>;
|
||||
qcom,supply-max-voltage = <6000000>;
|
||||
qcom,supply-enable-load = <100000>;
|
||||
qcom,supply-disable-load = <100>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@3 {
|
||||
reg = <3>;
|
||||
qcom,supply-name = "ibb";
|
||||
qcom,supply-min-voltage = <4600000>;
|
||||
qcom,supply-max-voltage = <6000000>;
|
||||
qcom,supply-enable-load = <100000>;
|
||||
qcom,supply-disable-load = <100>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
dsi_panel_pwr_supply_lab_ibb: dsi_panel_pwr_supply_lab_ibb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <62000>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "lab";
|
||||
qcom,supply-min-voltage = <4600000>;
|
||||
qcom,supply-max-voltage = <6000000>;
|
||||
qcom,supply-enable-load = <100000>;
|
||||
qcom,supply-disable-load = <100>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@2 {
|
||||
reg = <2>;
|
||||
qcom,supply-name = "ibb";
|
||||
qcom,supply-min-voltage = <4600000>;
|
||||
qcom,supply-max-voltage = <6000000>;
|
||||
qcom,supply-enable-load = <100000>;
|
||||
qcom,supply-disable-load = <100>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <62000>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "avdd";
|
||||
qcom,supply-min-voltage = <4600000>;
|
||||
qcom,supply-max-voltage = <6000000>;
|
||||
qcom,supply-enable-load = <100000>;
|
||||
qcom,supply-disable-load = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
display_panel_avdd: display_gpio_regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "display_panel_avdd";
|
||||
regulator-min-microvolt = <5500000>;
|
||||
regulator-max-microvolt = <5500000>;
|
||||
regulator-enable-ramp-delay = <233>;
|
||||
gpio = <&tlmm 61 0>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&display_panel_avdd_default>;
|
||||
};
|
||||
|
||||
sde_dsi: qcom,dsi-display-primary {
|
||||
compatible = "qcom,dsi-display";
|
||||
label = "primary";
|
||||
|
||||
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
|
||||
|
||||
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
|
||||
<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
|
||||
<&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
|
||||
<&mdss_dsi0_pll PCLK_SRC_0_CLK>,
|
||||
<&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,
|
||||
<&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>,
|
||||
<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
|
||||
<&mdss_dsi1_pll PCLK_MUX_1_CLK>,
|
||||
<&mdss_dsi1_pll BYTECLK_SRC_1_CLK>,
|
||||
<&mdss_dsi1_pll PCLK_SRC_1_CLK>,
|
||||
<&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>,
|
||||
<&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>;
|
||||
|
||||
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
|
||||
"src_byte_clk0", "src_pixel_clk0",
|
||||
"shadow_byte_clk0", "shadow_pixel_clk0",
|
||||
"mux_byte_clk1", "mux_pixel_clk1",
|
||||
"src_byte_clk1", "src_pixel_clk1",
|
||||
"shadow_byte_clk1", "shadow_pixel_clk1";
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
|
||||
|
||||
qcom,platform-te-gpio = <&tlmm 66 0>;
|
||||
qcom,panel-te-source = <0>;
|
||||
|
||||
vddio-supply = <&pm8150_l14>;
|
||||
vdd-supply = <&pm8150a_l11>;
|
||||
avdd-supply = <&display_panel_avdd>;
|
||||
lab-supply = <&ab_vreg>;
|
||||
ibb-supply = <&ibb_vreg>;
|
||||
|
||||
qcom,mdp = <&mdss_mdp>;
|
||||
qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
|
||||
};
|
||||
|
||||
sde_dsi1: qcom,dsi-display-secondary {
|
||||
compatible = "qcom,dsi-display";
|
||||
label = "secondary";
|
||||
|
||||
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
|
||||
|
||||
clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
|
||||
<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
|
||||
<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
|
||||
<&mdss_dsi1_pll PCLK_MUX_1_CLK>;
|
||||
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
|
||||
"mux_byte_clk1", "mux_pixel_clk1";
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
|
||||
pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
|
||||
|
||||
qcom,platform-te-gpio = <&tlmm 67 0>;
|
||||
qcom,panel-te-source = <1>;
|
||||
|
||||
vddio-supply = <&pm8150_l14>;
|
||||
vdd-supply = <&pm8150a_l11>;
|
||||
avdd-supply = <&display_panel_avdd>;
|
||||
|
||||
qcom,mdp = <&mdss_mdp>;
|
||||
};
|
||||
|
||||
sde_wb: qcom,wb-display@0 {
|
||||
compatible = "qcom,wb-display";
|
||||
cell-index = <0>;
|
||||
label = "wb_display";
|
||||
};
|
||||
};
|
||||
|
||||
&sde_dp {
|
||||
qcom,dp-usbpd-detection = <&pm8150b_pdphy>;
|
||||
qcom,ext-disp = <&ext_disp>;
|
||||
qcom,dp-aux-switch = <&fsa4480>;
|
||||
|
||||
qcom,usbplug-cc-gpio = <&tlmm 65 0>;
|
||||
|
||||
pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
|
||||
pinctrl-0 = <&sde_dp_usbplug_cc_active>;
|
||||
pinctrl-1 = <&sde_dp_usbplug_cc_suspend>;
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>;
|
||||
};
|
||||
|
||||
/* PHY TIMINGS REVISION W */
|
||||
&dsi_ext_bridge_1080p {
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
|
||||
08 05 02 04 00 19 17];
|
||||
qcom,display-topology = <1 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sw43404_amoled_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,dsi-dyn-clk-enable;
|
||||
qcom,dsi-dyn-clk-list = <552424501 549895420 547366339>;
|
||||
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
|
||||
"src_byte_clk0", "src_pixel_clk0",
|
||||
"shadow_byte_clk0", "shadow_pixel_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
|
||||
05 03 02 04 00 12 15];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1f 1e 05
|
||||
05 03 02 04 00 12 14];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 1e 1e 04
|
||||
04 02 02 04 00 10 14];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sw43404_amoled_video {
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
qcom,dsi-supported-dfps-list = <60 57 55>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";
|
||||
qcom,mdss-dsi-min-refresh-rate = <55>;
|
||||
qcom,mdss-dsi-max-refresh-rate = <60>;
|
||||
|
||||
qcom,dsi-dyn-clk-enable;
|
||||
qcom,dsi-dyn-clk-list =
|
||||
<534712320 532484352 530256384>;
|
||||
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
|
||||
"src_byte_clk0", "src_pixel_clk0",
|
||||
"shadow_byte_clk0", "shadow_pixel_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
|
||||
05 03 02 04 00 12 15];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sw43404_amoled_fhd_plus_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04
|
||||
05 02 03 04 00 11 14];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 270 270 270 1080 270>;
|
||||
qcom,mdss-dsi-panel-clockrate = <400000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
|
||||
08 05 02 04 00 19 18];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
|
||||
08 05 02 04 00 19 18];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sharp_qsync_wqhd_cmd {
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* WQHD 60FPS CMD */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 1d 1c 03
|
||||
03 01 02 04 00 0c 12];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
|
||||
};
|
||||
|
||||
timing@1 { /* WQHD 60FPS VID */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
|
||||
06 03 02 04 00 13 15];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 { /* FHD 60FPS CMD */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02
|
||||
02 00 02 04 00 0a 12];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
|
||||
};
|
||||
|
||||
timing@3 { /* WQHD 90FPS CMD */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 1e 1e 04
|
||||
04 02 02 04 00 0f 13];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
|
||||
};
|
||||
|
||||
timing@4 { /* WQHD 120FPS CMD */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05
|
||||
05 03 02 04 00 12 14];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
|
||||
};
|
||||
|
||||
timing@5 { /* WQHD 120FPS VID */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
|
||||
06 03 02 04 00 13 15];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* FHD 120FPS CMD */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04
|
||||
04 02 02 04 00 0e 13];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
|
||||
};
|
||||
|
||||
timing@7 { /* FHD 90FPS CMD */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03
|
||||
02 01 02 04 00 0c 12];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sharp_qsync_wqhd_video {
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
|
||||
06 03 02 04 00 13 15];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sharp_1080_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08
|
||||
08 05 02 04 00 19 18];
|
||||
qcom,display-topology = <1 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,mdss-dsi-panel-clockrate = <900000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_nt35597_truly_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <2 0 2>,
|
||||
<1 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_nt35597_truly_video {
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-min-refresh-rate = <53>;
|
||||
qcom,mdss-dsi-max-refresh-rate = <60>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <2 0 2>,
|
||||
<1 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_nt35695b_truly_fhd_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
|
||||
08 08 05 02 04 00 19 17];
|
||||
qcom,display-topology = <1 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_nt35695b_truly_fhd_video {
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
|
||||
08 08 05 02 04 00 19 17];
|
||||
qcom,display-topology = <1 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,panel-roi-alignment = <540 40 540 40 540 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
|
||||
timing@4 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,panel-roi-alignment = <360 40 360 40 360 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <1 0 1>,
|
||||
<2 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 1080p */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* qhd */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
|
||||
08 05 02 04 00 19 18];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* QHD 60fps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* 1080 60fps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
|
||||
08 05 02 04 00 19 18];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 { /* QHD 90fps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
|
||||
09 06 02 04 00 18 17];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <2 0 2>,
|
||||
<1 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
|
||||
08 05 02 04 00 19 18];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
|
||||
07 05 02 04 00 18 17];
|
||||
qcom,display-topology = <2 0 2>,
|
||||
<1 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 4k 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04
|
||||
04 02 02 04 00 0e 13];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* 4k 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
|
||||
06 04 02 04 00 15 16];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 { /* 4k 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 09
|
||||
09 06 02 04 00 1c 19];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@3 { /* 4k 120 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 29 27 0c
|
||||
0c 08 02 04 00 24 1b];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@4 { /* 1080 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01
|
||||
01 01 02 04 00 0a 11];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@5 { /* 1080 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03
|
||||
02 01 02 04 00 0c 12];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* 1080 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04
|
||||
03 02 02 04 00 0e 13];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@7 { /* 1080 120 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 1e 1e 04
|
||||
04 02 02 04 00 10 14];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@8 { /* qhd 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02
|
||||
02 01 02 04 00 0b 12];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@9 { /* qhd 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 1e 1d 04
|
||||
04 02 02 04 00 0f 13];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@10 { /* qhd 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1f 05
|
||||
05 03 02 04 00 12 15];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@11 { /* qhd 120 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 07
|
||||
06 04 02 04 00 15 16];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@12 { /* 5k */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07
|
||||
07 04 02 04 00 16 16];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@13 { /* 720p 30 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1a 1a 01
|
||||
01 00 02 04 00 08 11];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@14 { /* 720p 60 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01
|
||||
01 01 02 04 00 0a 11];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@15 { /* 720p 90 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02
|
||||
02 01 02 04 00 0b 12];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@16 { /* 720 120 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03
|
||||
03 01 02 04 00 0c 12];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
|
||||
08 08 05 02 04 00 19 17];
|
||||
qcom,display-topology = <1 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
};
|
||||
};
|
||||
91
display/lahaina-sde-pll.dtsi
Normal file
91
display/lahaina-sde-pll.dtsi
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
&soc {
|
||||
mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 {
|
||||
compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
|
||||
label = "MDSS DSI 0 PLL";
|
||||
cell-index = <0>;
|
||||
#clock-cells = <1>;
|
||||
reg = <0xae94900 0x260>,
|
||||
<0xae94400 0x800>,
|
||||
<0xaf03000 0x8>,
|
||||
<0xae94200 0x100>;
|
||||
reg-names = "pll_base", "phy_base", "gdsc_base",
|
||||
"dynamic_pll_base";
|
||||
clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
|
||||
clock-names = "iface_clk";
|
||||
clock-rate = <0>;
|
||||
memory-region = <&dfps_data_memory>;
|
||||
qcom,dsi-pll-ssc-en;
|
||||
qcom,dsi-pll-ssc-mode = "down-spread";
|
||||
qcom,platform-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,platform-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "gdsc";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 {
|
||||
compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
|
||||
label = "MDSS DSI 1 PLL";
|
||||
cell-index = <1>;
|
||||
#clock-cells = <1>;
|
||||
reg = <0xae96900 0x260>,
|
||||
<0xae96400 0x800>,
|
||||
<0xaf03000 0x8>,
|
||||
<0xae96200 0x100>;
|
||||
reg-names = "pll_base", "phy_base", "gdsc_base",
|
||||
"dynamic_pll_base";
|
||||
clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
|
||||
clock-names = "iface_clk";
|
||||
clock-rate = <0>;
|
||||
qcom,dsi-pll-ssc-en;
|
||||
qcom,dsi-pll-ssc-mode = "down-spread";
|
||||
qcom,platform-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,platform-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "gdsc";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dp_pll: qcom,mdss_dp_pll@c011000 {
|
||||
compatible = "qcom,mdss_dp_pll_7nm";
|
||||
label = "MDSS DP PLL";
|
||||
cell-index = <0>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
reg = <0x088ea000 0x200>,
|
||||
<0x088eaa00 0x200>,
|
||||
<0x088ea200 0x200>,
|
||||
<0x088ea2b8 0x8>,
|
||||
<0x088ea2e8 0x4>,
|
||||
<0x088ea600 0x200>,
|
||||
<0x088ea6b8 0x8>,
|
||||
<0x088ea6e8 0x4>,
|
||||
<0xaf03000 0x8>;
|
||||
reg-names = "pll_base", "phy_base",
|
||||
"ln_tx0_base", "ln_tx0_tran_base", "ln_tx0_vmode_base",
|
||||
"ln_tx1_base", "ln_tx1_tran_base", "ln_tx1_vmode_base",
|
||||
"gdsc_base";
|
||||
|
||||
clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&clock_rpmh RPMH_CXO_CLK>,
|
||||
<&clock_gcc GCC_DISP_AHB_CLK>,
|
||||
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
||||
clock-names = "iface_clk", "ref_clk_src",
|
||||
"gcc_iface", "pipe_clk";
|
||||
clock-rate = <0>;
|
||||
};
|
||||
};
|
||||
704
display/lahaina-sde.dtsi
Normal file
704
display/lahaina-sde.dtsi
Normal file
|
|
@ -0,0 +1,704 @@
|
|||
#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
|
||||
|
||||
&soc {
|
||||
mdss_mdp: qcom,mdss_mdp@ae00000 {
|
||||
compatible = "qcom,sde-kms";
|
||||
reg = <0x0ae00000 0x84208>,
|
||||
<0x0aeb0000 0x2008>,
|
||||
<0x0aeac000 0x214>,
|
||||
<0x0ae8f000 0x02c>,
|
||||
<0x0af50000 0x038>;
|
||||
reg-names = "mdp_phys",
|
||||
"vbif_phys",
|
||||
"regdma_phys",
|
||||
"sid_phys",
|
||||
"swfuse_phys";
|
||||
|
||||
clocks =
|
||||
<&clock_gcc GCC_DISP_AHB_CLK>,
|
||||
<&clock_gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&clock_gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
|
||||
clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
|
||||
"iface_clk", "core_clk", "vsync_clk",
|
||||
"lut_clk", "rot_clk";
|
||||
clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>;
|
||||
clock-max-rate = <0 0 0 0 460000000 19200000 460000000
|
||||
460000000>;
|
||||
|
||||
mmcx-supply = <&VDD_MMCX_LEVEL>;
|
||||
|
||||
/* interrupt config */
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
/* hw blocks */
|
||||
qcom,sde-off = <0x1000>;
|
||||
qcom,sde-len = <0x494>;
|
||||
|
||||
qcom,sde-ctl-off = <0x2000 0x2200 0x2400
|
||||
0x2600 0x2800 0x2a00>;
|
||||
qcom,sde-ctl-size = <0x1dc>;
|
||||
qcom,sde-ctl-display-pref = "primary", "none", "none",
|
||||
"none", "none";
|
||||
|
||||
qcom,sde-mixer-off = <0x45000 0x46000 0x47000
|
||||
0x48000 0x49000 0x4a000>;
|
||||
qcom,sde-mixer-size = <0x320>;
|
||||
qcom,sde-mixer-display-pref = "primary", "primary", "none",
|
||||
"none", "none", "none";
|
||||
|
||||
qcom,sde-mixer-cwb-pref = "none", "none", "cwb",
|
||||
"cwb", "cwb", "cwb";
|
||||
|
||||
qcom,sde-dspp-top-off = <0x1300>;
|
||||
qcom,sde-dspp-top-size = <0x80>;
|
||||
qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
|
||||
qcom,sde-dspp-size = <0x1800>;
|
||||
|
||||
qcom,sde-dest-scaler-top-off = <0x00061000>;
|
||||
qcom,sde-dest-scaler-top-size = <0x1c>;
|
||||
qcom,sde-dest-scaler-off = <0x800 0x1000>;
|
||||
qcom,sde-dest-scaler-size = <0x800>;
|
||||
|
||||
qcom,sde-wb-off = <0x66000>;
|
||||
qcom,sde-wb-size = <0x2c8>;
|
||||
qcom,sde-wb-xin-id = <6>;
|
||||
qcom,sde-wb-id = <2>;
|
||||
qcom,sde-wb-clk-ctrl = <0x2bc 16>;
|
||||
|
||||
qcom,sde-intf-off = <0x6b000 0x6b800
|
||||
0x6c000 0x6c800>;
|
||||
qcom,sde-intf-size = <0x2b8>;
|
||||
qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
|
||||
|
||||
qcom,sde-pp-off = <0x71000 0x71800
|
||||
0x72000 0x72800 0x73000 0x73800>;
|
||||
qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
qcom,sde-pp-size = <0xd4>;
|
||||
qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>;
|
||||
|
||||
qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>;
|
||||
qcom,sde-merge-3d-size = <0x100>;
|
||||
|
||||
qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>;
|
||||
|
||||
qcom,sde-cdm-off = <0x7a200>;
|
||||
qcom,sde-cdm-size = <0x224>;
|
||||
|
||||
qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>;
|
||||
qcom,sde-dsc-size = <0x140>;
|
||||
qcom,sde-dsc-pair-mask = <2 1 4 3>;
|
||||
|
||||
qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0
|
||||
0x30e0 0x30e0 0x30e0>;
|
||||
qcom,sde-dither-version = <0x00010000>;
|
||||
qcom,sde-dither-size = <0x20>;
|
||||
|
||||
qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
|
||||
"dma", "dma", "dma", "dma";
|
||||
|
||||
qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
|
||||
0x25000 0x27000 0x29000 0x2b000>;
|
||||
qcom,sde-sspp-src-size = <0x1f8>;
|
||||
|
||||
qcom,sde-sspp-xin-id = <0 4 8 12
|
||||
1 5 9 13>;
|
||||
qcom,sde-sspp-excl-rect = <1 1 1 1
|
||||
1 1 1 1>;
|
||||
qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
|
||||
qcom,sde-smart-dma-rev = "smart_dma_v2p5";
|
||||
|
||||
qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>;
|
||||
|
||||
qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
|
||||
0xb0 0xc8 0xe0 0xf8 0x110>;
|
||||
|
||||
qcom,sde-max-per-pipe-bw-kbps = <4400000 4400000
|
||||
4400000 4400000
|
||||
4400000 4400000
|
||||
4400000 4400000>;
|
||||
|
||||
qcom,sde-max-per-pipe-bw-high-kbps = <5300000 5300000
|
||||
5300000 5300000
|
||||
5300000 5300000
|
||||
5300000 5300000>;
|
||||
|
||||
/* offsets are relative to "mdp_phys + qcom,sde-off */
|
||||
qcom,sde-sspp-clk-ctrl =
|
||||
<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
|
||||
<0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
|
||||
qcom,sde-sspp-csc-off = <0x1a00>;
|
||||
qcom,sde-csc-type = "csc-10bit";
|
||||
qcom,sde-qseed-type = "qseedv3lite";
|
||||
qcom,sde-sspp-qseed-off = <0xa00>;
|
||||
qcom,sde-mixer-linewidth = <2560>;
|
||||
qcom,sde-sspp-linewidth = <4096>;
|
||||
qcom,sde-wb-linewidth = <4096>;
|
||||
qcom,sde-mixer-blendstages = <0xb>;
|
||||
qcom,sde-highest-bank-bit = <0x3>;
|
||||
qcom,sde-ubwc-version = <0x400>;
|
||||
qcom,sde-ubwc-swizzle = <0x6>;
|
||||
qcom,sde-ubwc-bw-calc-version = <0x1>;
|
||||
qcom,sde-ubwc-static = <0x1>;
|
||||
qcom,sde-macrotile-mode = <0x1>;
|
||||
qcom,sde-smart-panel-align-mode = <0xc>;
|
||||
qcom,sde-panic-per-pipe;
|
||||
qcom,sde-has-cdp;
|
||||
qcom,sde-has-src-split;
|
||||
qcom,sde-pipe-order-version = <0x1>;
|
||||
qcom,sde-has-dim-layer;
|
||||
qcom,sde-has-dest-scaler;
|
||||
qcom,sde-has-idle-pc;
|
||||
qcom,sde-max-dest-scaler-input-linewidth = <2048>;
|
||||
qcom,sde-max-dest-scaler-output-linewidth = <2560>;
|
||||
qcom,sde-max-bw-low-kbps = <13700000>;
|
||||
qcom,sde-max-bw-high-kbps = <16600000>;
|
||||
qcom,sde-min-core-ib-kbps = <4800000>;
|
||||
qcom,sde-min-llcc-ib-kbps = <0>;
|
||||
qcom,sde-min-dram-ib-kbps = <800000>;
|
||||
qcom,sde-dram-channels = <2>;
|
||||
qcom,sde-num-nrt-paths = <0>;
|
||||
qcom,sde-dspp-ltm-version = <0x00010000>;
|
||||
/* offsets are based off dspp 0 and dspp 1 */
|
||||
qcom,sde-dspp-ltm-off = <0x2a000 0x28100>;
|
||||
|
||||
qcom,sde-uidle-off = <0x80000>;
|
||||
qcom,sde-uidle-size = <0x70>;
|
||||
|
||||
qcom,sde-vbif-off = <0>;
|
||||
qcom,sde-vbif-size = <0x1040>;
|
||||
qcom,sde-vbif-id = <0>;
|
||||
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
|
||||
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
|
||||
|
||||
qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
|
||||
qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
|
||||
qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
|
||||
qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;
|
||||
|
||||
/* macrotile & macrotile-qseed has the same configs */
|
||||
qcom,sde-danger-lut = <0x000000ff 0x0000ffff
|
||||
0x00000000 0x00000000 0x0000ffff>;
|
||||
|
||||
qcom,sde-safe-lut-linear = <0 0xfff0>;
|
||||
qcom,sde-safe-lut-macrotile = <0 0xff00>;
|
||||
/* same as safe-lut-macrotile */
|
||||
qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
|
||||
qcom,sde-safe-lut-nrt = <0 0xffff>;
|
||||
qcom,sde-safe-lut-cwb = <0 0x3ff>;
|
||||
|
||||
qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
|
||||
qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
|
||||
qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
|
||||
qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
|
||||
qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>;
|
||||
|
||||
qcom,sde-cdp-setting = <1 1>, <1 0>;
|
||||
|
||||
qcom,sde-qos-cpu-mask = <0x3>;
|
||||
qcom,sde-qos-cpu-dma-latency = <300>;
|
||||
|
||||
/* offsets are relative to "mdp_phys + qcom,sde-off */
|
||||
|
||||
qcom,sde-reg-dma-off = <0>;
|
||||
qcom,sde-reg-dma-version = <0x00010002>;
|
||||
qcom,sde-reg-dma-trigger-off = <0x119c>;
|
||||
qcom,sde-reg-dma-xin-id = <7>;
|
||||
qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
|
||||
|
||||
qcom,sde-secure-sid-mask = <0x4000821>;
|
||||
|
||||
qcom,sde-sspp-vig-blocks {
|
||||
qcom,sde-vig-csc-off = <0x1a00>;
|
||||
qcom,sde-vig-qseed-off = <0xa00>;
|
||||
qcom,sde-vig-qseed-size = <0xa0>;
|
||||
qcom,sde-vig-gamut = <0x1d00 0x00060000>;
|
||||
qcom,sde-vig-igc = <0x1d00 0x00060000>;
|
||||
qcom,sde-vig-inverse-pma;
|
||||
};
|
||||
|
||||
qcom,sde-sspp-dma-blocks {
|
||||
dgm@0 {
|
||||
qcom,sde-dma-igc = <0x400 0x00050000>;
|
||||
qcom,sde-dma-gc = <0x600 0x00050000>;
|
||||
qcom,sde-dma-inverse-pma;
|
||||
qcom,sde-dma-csc-off = <0x200>;
|
||||
};
|
||||
|
||||
dgm@1 {
|
||||
qcom,sde-dma-igc = <0x1400 0x00050000>;
|
||||
qcom,sde-dma-gc = <0x600 0x00050000>;
|
||||
qcom,sde-dma-inverse-pma;
|
||||
qcom,sde-dma-csc-off = <0x1200>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,sde-dspp-blocks {
|
||||
qcom,sde-dspp-igc = <0x0 0x00030001>;
|
||||
qcom,sde-dspp-hsic = <0x800 0x00010007>;
|
||||
qcom,sde-dspp-memcolor = <0x880 0x00010007>;
|
||||
qcom,sde-dspp-hist = <0x800 0x00010007>;
|
||||
qcom,sde-dspp-sixzone= <0x900 0x00010007>;
|
||||
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
|
||||
qcom,sde-dspp-gamut = <0x1000 0x00040002>;
|
||||
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
|
||||
qcom,sde-dspp-gc = <0x17c0 0x00010008>;
|
||||
qcom,sde-dspp-dither = <0x82c 0x00010007>;
|
||||
};
|
||||
|
||||
qcom,platform-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,platform-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "mmcx";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
|
||||
compatible = "qcom,smmu_sde_unsec";
|
||||
iommus = <&apps_smmu 0x820 0x402>;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-earlymap; /* for cont-splash */
|
||||
};
|
||||
|
||||
smmu_sde_sec: qcom,smmu_sde_sec_cb {
|
||||
compatible = "qcom,smmu_sde_sec";
|
||||
iommus = <&apps_smmu 0x821 0x400>;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-vmid = <0xa>;
|
||||
};
|
||||
|
||||
/* data and reg bus scale settings */
|
||||
qcom,sde-data-bus {
|
||||
qcom,msm-bus,name = "mdss_sde";
|
||||
qcom,msm-bus,num-cases = <3>;
|
||||
qcom,msm-bus,num-paths = <2>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<22 512 0 0>, <23 512 0 0>,
|
||||
<22 512 0 6400000>, <23 512 0 6400000>,
|
||||
<22 512 0 6400000>, <23 512 0 6400000>;
|
||||
};
|
||||
|
||||
qcom,sde-reg-bus {
|
||||
qcom,msm-bus,name = "mdss_reg";
|
||||
qcom,msm-bus,num-cases = <4>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<1 590 0 0>,
|
||||
<1 590 0 76800>,
|
||||
<1 590 0 150000>,
|
||||
<1 590 0 300000>;
|
||||
};
|
||||
};
|
||||
|
||||
sde_dp: qcom,dp_display@ae90000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,dp-display";
|
||||
|
||||
vdda-1p2-supply = <&pm8150_l9>;
|
||||
vdda-0p9-supply = <&pm8150_l18>;
|
||||
|
||||
reg = <0xae90000 0x0dc>,
|
||||
<0xae90200 0x0c0>,
|
||||
<0xae90400 0x508>,
|
||||
<0xae91000 0x094>,
|
||||
<0x88eaa00 0x200>,
|
||||
<0x88ea200 0x200>,
|
||||
<0x88ea600 0x200>,
|
||||
<0xaf02000 0x1a0>,
|
||||
<0x88ea040 0x10>,
|
||||
<0x88e8000 0x20>,
|
||||
<0x0aee1000 0x034>,
|
||||
<0xae91400 0x094>;
|
||||
/* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */
|
||||
reg-names = "dp_ahb", "dp_aux", "dp_link",
|
||||
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
|
||||
"dp_mmss_cc", "dp_pll",
|
||||
"usb3_dp_com", "hdcp_physical", "dp_p1";
|
||||
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <12 0>;
|
||||
|
||||
clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&clock_rpmh RPMH_CXO_CLK>,
|
||||
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
|
||||
<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
|
||||
<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
|
||||
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
|
||||
"core_usb_pipe_clk", "link_clk", "link_iface_clk",
|
||||
"pixel_clk_rcg", "pixel_parent",
|
||||
"pixel1_clk_rcg", "pixel1_parent",
|
||||
"strm0_pixel_clk", "strm1_pixel_clk";
|
||||
|
||||
qcom,phy-version = <0x420>;
|
||||
qcom,aux-cfg0-settings = [20 00];
|
||||
qcom,aux-cfg1-settings = [24 13];
|
||||
qcom,aux-cfg2-settings = [28 A4];
|
||||
qcom,aux-cfg3-settings = [2c 00];
|
||||
qcom,aux-cfg4-settings = [30 0a];
|
||||
qcom,aux-cfg5-settings = [34 26];
|
||||
qcom,aux-cfg6-settings = [38 0a];
|
||||
qcom,aux-cfg7-settings = [3c 03];
|
||||
qcom,aux-cfg8-settings = [40 b7];
|
||||
qcom,aux-cfg9-settings = [44 03];
|
||||
|
||||
qcom,max-pclk-frequency-khz = <675000>;
|
||||
|
||||
qcom,mst-enable;
|
||||
qcom,widebus-enable;
|
||||
qcom,dsc-feature-enable;
|
||||
qcom,fec-feature-enable;
|
||||
qcom,max-dp-dsc-blks = <2>;
|
||||
qcom,max-dp-dsc-input-width-pixs = <2048>;
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <33000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <912000>;
|
||||
qcom,supply-max-voltage = <912000>;
|
||||
qcom,supply-enable-load = <126000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,core-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,core-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "refgen";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sde_rscc: qcom,sde_rscc@af20000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,sde-rsc";
|
||||
reg = <0xaf20000 0x3c50>,
|
||||
<0xaf30000 0x3fd4>;
|
||||
reg-names = "drv", "wrapper";
|
||||
qcom,sde-rsc-version = <3>;
|
||||
|
||||
qcom,sde-dram-channels = <2>;
|
||||
|
||||
vdd-supply = <&mdss_core_gdsc>;
|
||||
clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
|
||||
clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
|
||||
|
||||
/* data and reg bus scale settings */
|
||||
qcom,sde-data-bus {
|
||||
qcom,msm-bus,name = "disp_rsc_mnoc_llcc";
|
||||
qcom,msm-bus,active-only;
|
||||
qcom,msm-bus,num-cases = <3>;
|
||||
qcom,msm-bus,num-paths = <2>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<20003 20513 0 0>, <20004 20513 0 0>,
|
||||
<20003 20513 0 6400000>, <20004 20513 0 6400000>,
|
||||
<20003 20513 0 6400000>, <20004 20513 0 6400000>;
|
||||
};
|
||||
|
||||
qcom,sde-ebi-bus {
|
||||
qcom,msm-bus,name = "disp_rsc_ebi";
|
||||
qcom,msm-bus,active-only;
|
||||
qcom,msm-bus,num-cases = <3>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<20000 20512 0 0>,
|
||||
<20000 20512 0 6400000>,
|
||||
<20000 20512 0 6400000>;
|
||||
};
|
||||
|
||||
qcom,sde-reg-bus {
|
||||
qcom,msm-bus,name = "disp_rsc_reg";
|
||||
qcom,msm-bus,num-cases = <4>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<1 590 0 0>,
|
||||
<1 590 0 76800>,
|
||||
<1 590 0 150000>,
|
||||
<1 590 0 300000>;
|
||||
};
|
||||
};
|
||||
|
||||
mdss_rotator: qcom,mdss_rotator@aea8800 {
|
||||
compatible = "qcom,sde_rotator";
|
||||
reg = <0x0ae00000 0xac000>,
|
||||
<0x0aeb8000 0x3000>;
|
||||
reg-names = "mdp_phys",
|
||||
"rot_vbif_phys";
|
||||
status = "disabled";
|
||||
|
||||
#list-cells = <1>;
|
||||
|
||||
qcom,mdss-rot-mode = <1>;
|
||||
qcom,mdss-highest-bank-bit = <0x3>;
|
||||
|
||||
/* Bus Scale Settings */
|
||||
qcom,msm-bus,name = "mdss_rotator";
|
||||
qcom,msm-bus,num-cases = <3>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<25 512 0 0>,
|
||||
<25 512 0 6400000>,
|
||||
<25 512 0 6400000>;
|
||||
|
||||
rot-vdd-supply = <&mdss_core_gdsc>;
|
||||
qcom,supply-names = "rot-vdd";
|
||||
|
||||
clocks =
|
||||
<&clock_gcc GCC_DISP_AHB_CLK>,
|
||||
<&clock_gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
|
||||
clock-names = "gcc_iface", "gcc_bus",
|
||||
"iface_clk", "rot_clk";
|
||||
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <2 0>;
|
||||
|
||||
power-domains = <&mdss_mdp>;
|
||||
|
||||
/* Offline rotator QoS setting */
|
||||
qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
|
||||
qcom,mdss-rot-vbif-memtype = <3 3>;
|
||||
qcom,mdss-rot-cdp-setting = <1 1>;
|
||||
qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
|
||||
qcom,mdss-rot-danger-lut = <0x0 0x0>;
|
||||
qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
|
||||
|
||||
qcom,mdss-default-ot-rd-limit = <32>;
|
||||
qcom,mdss-default-ot-wr-limit = <32>;
|
||||
|
||||
qcom,mdss-sbuf-headroom = <20>;
|
||||
|
||||
/* reg bus scale settings */
|
||||
rot_reg: qcom,rot-reg-bus {
|
||||
qcom,msm-bus,name = "mdss_rot_reg";
|
||||
qcom,msm-bus,num-cases = <2>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<1 590 0 0>,
|
||||
<1 590 0 76800>;
|
||||
};
|
||||
|
||||
smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
|
||||
compatible = "qcom,smmu_sde_rot_unsec";
|
||||
iommus = <&apps_smmu 0x215C 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
|
||||
compatible = "qcom,dsi-ctrl-hw-v2.4";
|
||||
label = "dsi-ctrl-0";
|
||||
cell-index = <0>;
|
||||
frame-threshold-time-us = <800>;
|
||||
reg = <0xae94000 0x400>,
|
||||
<0xaf08000 0x4>;
|
||||
reg-names = "dsi_ctrl", "disp_cc_base";
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <4 0>;
|
||||
vdda-1p2-supply = <&pm8150_l9>;
|
||||
refgen-supply = <&refgen>;
|
||||
clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
||||
<&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <26700>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,core-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,core-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "refgen";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
|
||||
compatible = "qcom,dsi-ctrl-hw-v2.4";
|
||||
label = "dsi-ctrl-1";
|
||||
cell-index = <1>;
|
||||
frame-threshold-time-us = <800>;
|
||||
reg = <0xae96000 0x400>,
|
||||
<0xaf08000 0x4>;
|
||||
reg-names = "dsi_ctrl", "disp_cc_base";
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <5 0>;
|
||||
vdda-1p2-supply = <&pm8150_l9>;
|
||||
refgen-supply = <&refgen>;
|
||||
clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
||||
<&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <26700>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,core-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,core-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "refgen";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
|
||||
compatible = "qcom,dsi-phy-v4.1";
|
||||
label = "dsi-phy-0";
|
||||
cell-index = <0>;
|
||||
reg = <0xae94400 0x7c0>,
|
||||
<0xae94200 0x100>;
|
||||
reg-names = "dsi_phy", "dyn_refresh_base";
|
||||
vdda-0p9-supply = <&pm8150_l5>;
|
||||
qcom,platform-strength-ctrl = [55 03
|
||||
55 03
|
||||
55 03
|
||||
55 03
|
||||
55 00];
|
||||
qcom,platform-lane-config = [00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 8a 8a];
|
||||
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <880000>;
|
||||
qcom,supply-max-voltage = <880000>;
|
||||
qcom,supply-enable-load = <46000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96400 {
|
||||
compatible = "qcom,dsi-phy-v4.1";
|
||||
label = "dsi-phy-1";
|
||||
cell-index = <1>;
|
||||
reg = <0xae96400 0x7c0>,
|
||||
<0xae96200 0x100>;
|
||||
reg-names = "dsi_phy", "dyn_refresh_base";
|
||||
vdda-0p9-supply = <&pm8150_l5>;
|
||||
qcom,platform-strength-ctrl = [55 03
|
||||
55 03
|
||||
55 03
|
||||
55 03
|
||||
55 00];
|
||||
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
||||
qcom,platform-lane-config = [00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 8a 8a];
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <880000>;
|
||||
qcom,supply-max-voltage = <880000>;
|
||||
qcom,supply-enable-load = <46000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
Loading…
Reference in a new issue