mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Pull networking fixes from David Miller:
1) Fix TCP checksum offload handling in iwlwifi driver, from Emmanuel
Grumbach.
2) In ksz DSA tagging code, free SKB if skb_put_padto() fails. From
Vivien Didelot.
3) Fix two regressions with bonding on wireless, from Andreas Born.
4) Fix build when busypoll is disabled, from Daniel Borkmann.
5) Fix copy_linear_skb() wrt. SO_PEEK_OFF, from Eric Dumazet.
6) Set SKB cached route properly in inet_rtm_getroute(), from Florian
Westphal.
7) Fix PCI-E relaxed ordering handling in cxgb4 driver, from Ding
Tianhong.
8) Fix module refcnt leak in ULP code, from Sabrina Dubroca.
9) Fix use of GFP_KERNEL in atomic contexts in AF_KEY code, from Eric
Dumazet.
10) Need to purge socket write queue in dccp_destroy_sock(), also from
Eric Dumazet.
11) Make bpf_trace_printk() work properly on 32-bit architectures, from
Daniel Borkmann.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (47 commits)
bpf: fix bpf_trace_printk on 32 bit archs
PCI: fix oops when try to find Root Port for a PCI device
sfc: don't try and read ef10 data on non-ef10 NIC
net_sched: remove warning from qdisc_hash_add
net_sched/sfq: update hierarchical backlog when drop packet
net_sched: reset pointers to tcf blocks in classful qdiscs' destructors
ipv4: fix NULL dereference in free_fib_info_rcu()
net: Fix a typo in comment about sock flags.
ipv6: fix NULL dereference in ip6_route_dev_notify()
tcp: fix possible deadlock in TCP stack vs BPF filter
dccp: purge write queue in dccp_destroy_sock()
udp: fix linear skb reception with PEEK_OFF
ipv6: release rt6->rt6i_idev properly during ifdown
af_key: do not use GFP_KERNEL in atomic contexts
tcp: ulp: avoid module refcnt leak in tcp_set_ulp
net/cxgb4vf: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
PCI: Disable Relaxed Ordering Attributes for AMD A1100
PCI: Disable Relaxed Ordering for some Intel processors
PCI: Disable PCIe Relaxed Ordering if unsupported
...
This commit is contained in:
Linus Torvalds
commit
510c8a899c
58 changed files with 512 additions and 159 deletions
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@ -522,10 +522,11 @@ struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
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bridge = pci_upstream_bridge(bridge);
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}
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if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
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return NULL;
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if (highest_pcie_bridge &&
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pci_pcie_type(highest_pcie_bridge) == PCI_EXP_TYPE_ROOT_PORT)
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return highest_pcie_bridge;
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return highest_pcie_bridge;
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return NULL;
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}
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EXPORT_SYMBOL(pci_find_pcie_root_port);
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@ -1762,6 +1762,48 @@ static void pci_configure_extended_tags(struct pci_dev *dev)
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PCI_EXP_DEVCTL_EXT_TAG);
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}
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/**
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* pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
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* @dev: PCI device to query
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*
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* Returns true if the device has enabled relaxed ordering attribute.
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*/
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bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
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{
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u16 v;
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pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
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return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
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}
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EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
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static void pci_configure_relaxed_ordering(struct pci_dev *dev)
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{
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struct pci_dev *root;
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/* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
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if (dev->is_virtfn)
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return;
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if (!pcie_relaxed_ordering_enabled(dev))
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return;
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/*
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* For now, we only deal with Relaxed Ordering issues with Root
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* Ports. Peer-to-Peer DMA is another can of worms.
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*/
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root = pci_find_pcie_root_port(dev);
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if (!root)
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return;
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if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
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PCI_EXP_DEVCTL_RELAX_EN);
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dev_info(&dev->dev, "Disable Relaxed Ordering because the Root Port didn't support it\n");
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}
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}
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static void pci_configure_device(struct pci_dev *dev)
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{
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struct hotplug_params hpp;
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@ -1769,6 +1811,7 @@ static void pci_configure_device(struct pci_dev *dev)
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pci_configure_mps(dev);
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pci_configure_extended_tags(dev);
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pci_configure_relaxed_ordering(dev);
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memset(&hpp, 0, sizeof(hpp));
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ret = pci_get_hp_params(dev, &hpp);
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@ -4015,6 +4015,95 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
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DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
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quirk_tw686x_class);
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/*
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* Some devices have problems with Transaction Layer Packets with the Relaxed
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* Ordering Attribute set. Such devices should mark themselves and other
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* Device Drivers should check before sending TLPs with RO set.
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*/
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static void quirk_relaxedordering_disable(struct pci_dev *dev)
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{
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dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
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dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
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}
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/*
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* Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
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* Complex has a Flow Control Credit issue which can cause performance
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* problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
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*/
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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/*
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* The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
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* where Upstream Transaction Layer Packets with the Relaxed Ordering
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* Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
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* set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
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* outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
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* November 10, 2010). As a result, on this platform we can't use Relaxed
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* Ordering for Upstream TLPs.
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*/
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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/*
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* Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
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* values for the Attribute as were supplied in the header of the
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