mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-26 06:33:19 -04:00
Merge "msm: camera: tfe: Enable only master interrupts in dual tfe usecase" into camera-kernel.lnx.4.0
This commit is contained in:
commit
517d32cb7b
3 changed files with 22 additions and 154 deletions
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@ -3439,11 +3439,6 @@ static int cam_tfe_mgr_release_hw(void *hw_mgr_priv,
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ctx->last_submit_bl_cmd.bl_count = 0;
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ctx->packet = NULL;
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for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) {
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ctx->sof_cnt[i] = 0;
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ctx->eof_cnt[i] = 0;
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ctx->epoch_cnt[i] = 0;
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}
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CAM_DBG(CAM_ISP, "Exit...ctx id:%d",
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ctx->ctx_index);
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cam_tfe_hw_mgr_put_ctx(&hw_mgr->free_ctx_list, &ctx);
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@ -4665,36 +4660,6 @@ outportlog:
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}
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static void cam_tfe_mgr_ctx_irq_dump(struct cam_tfe_hw_mgr_ctx *ctx)
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{
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struct cam_isp_hw_mgr_res *hw_mgr_res;
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struct cam_hw_intf *hw_intf;
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struct cam_isp_hw_get_cmd_update cmd_update;
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int i = 0;
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list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) {
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if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT)
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continue;
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for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) {
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if (!hw_mgr_res->hw_res[i])
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continue;
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switch (hw_mgr_res->hw_res[i]->res_id) {
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case CAM_ISP_HW_TFE_IN_CAMIF:
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hw_intf = hw_mgr_res->hw_res[i]->hw_intf;
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cmd_update.res = hw_mgr_res->hw_res[i];
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cmd_update.cmd_type =
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CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP;
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hw_intf->hw_ops.process_cmd(hw_intf->hw_priv,
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CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP,
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&cmd_update, sizeof(cmd_update));
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break;
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default:
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break;
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}
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}
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}
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}
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static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args)
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{
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int rc = 0;
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@ -5310,82 +5275,6 @@ static int cam_tfe_hw_mgr_handle_hw_rup(
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return 0;
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}
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static int cam_tfe_hw_mgr_check_irq_for_dual_tfe(
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struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx,
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uint32_t hw_event_type)
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{
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int32_t rc = -EINVAL;
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uint32_t *event_cnt = NULL;
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uint32_t master_hw_idx;
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uint32_t slave_hw_idx;
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if (!tfe_hw_mgr_ctx->is_dual)
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return 0;
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master_hw_idx = tfe_hw_mgr_ctx->master_hw_idx;
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slave_hw_idx = tfe_hw_mgr_ctx->slave_hw_idx;
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switch (hw_event_type) {
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case CAM_ISP_HW_EVENT_SOF:
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event_cnt = tfe_hw_mgr_ctx->sof_cnt;
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break;
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case CAM_ISP_HW_EVENT_EPOCH:
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event_cnt = tfe_hw_mgr_ctx->epoch_cnt;
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break;
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case CAM_ISP_HW_EVENT_EOF:
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event_cnt = tfe_hw_mgr_ctx->eof_cnt;
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break;
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default:
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return 0;
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}
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if (event_cnt[master_hw_idx] == event_cnt[slave_hw_idx]) {
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event_cnt[master_hw_idx] = 0;
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event_cnt[slave_hw_idx] = 0;
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return 0;
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}
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if ((event_cnt[master_hw_idx] &&
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(event_cnt[master_hw_idx] - event_cnt[slave_hw_idx] > 1)) ||
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(event_cnt[slave_hw_idx] &&
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(event_cnt[slave_hw_idx] - event_cnt[master_hw_idx] > 1))) {
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if (tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt > 10) {
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rc = -1;
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return rc;
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}
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CAM_ERR_RATE_LIMIT(CAM_ISP,
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"One TFE could not generate hw event %d master id :%d slave id:%d",
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hw_event_type, event_cnt[master_hw_idx],
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event_cnt[slave_hw_idx]);
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if (event_cnt[master_hw_idx] >= 2) {
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event_cnt[master_hw_idx]--;
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tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt++;
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}
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if (event_cnt[slave_hw_idx] >= 2) {
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event_cnt[slave_hw_idx]--;
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tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt++;
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}
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if (tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt == 1) {
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cam_tfe_mgr_ctx_irq_dump(tfe_hw_mgr_ctx);
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trace_cam_delay_detect("ISP", "dual tfe irq mismatch",
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CAM_DEFAULT_VALUE, tfe_hw_mgr_ctx->ctx_index,
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CAM_DEFAULT_VALUE, CAM_DEFAULT_VALUE,
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rc);
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}
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rc = 0;
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}
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CAM_DBG(CAM_ISP, "Only one core_index has given hw event %d",
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hw_event_type);
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return rc;
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}
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static int cam_tfe_hw_mgr_handle_hw_epoch(
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void *ctx,
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void *evt_info)
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@ -5394,22 +5283,16 @@ static int cam_tfe_hw_mgr_handle_hw_epoch(
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struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx;
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cam_hw_event_cb_func tfe_hw_irq_epoch_cb;
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struct cam_isp_hw_epoch_event_data epoch_done_event_data;
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int rc = 0;
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tfe_hw_irq_epoch_cb =
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tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_EPOCH];
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switch (event_info->res_id) {
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case CAM_ISP_HW_TFE_IN_CAMIF:
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tfe_hw_mgr_ctx->epoch_cnt[event_info->hw_idx]++;
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rc = cam_tfe_hw_mgr_check_irq_for_dual_tfe(tfe_hw_mgr_ctx,
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CAM_ISP_HW_EVENT_EPOCH);
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if (!rc) {
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if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending))
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break;
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tfe_hw_irq_epoch_cb(tfe_hw_mgr_ctx->common.cb_priv,
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CAM_ISP_HW_EVENT_EPOCH, &epoch_done_event_data);
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}
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if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending))
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break;
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tfe_hw_irq_epoch_cb(tfe_hw_mgr_ctx->common.cb_priv,
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CAM_ISP_HW_EVENT_EPOCH, &epoch_done_event_data);
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break;
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case CAM_ISP_HW_TFE_IN_RDI0:
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@ -5436,27 +5319,22 @@ static int cam_tfe_hw_mgr_handle_hw_sof(
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struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx;
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cam_hw_event_cb_func tfe_hw_irq_sof_cb;
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struct cam_isp_hw_sof_event_data sof_done_event_data;
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int rc = 0;
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tfe_hw_irq_sof_cb =
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tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_SOF];
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switch (event_info->res_id) {
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case CAM_ISP_HW_TFE_IN_CAMIF:
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tfe_hw_mgr_ctx->sof_cnt[event_info->hw_idx]++;
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rc = cam_tfe_hw_mgr_check_irq_for_dual_tfe(tfe_hw_mgr_ctx,
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CAM_ISP_HW_EVENT_SOF);
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if (!rc) {
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cam_tfe_mgr_cmd_get_sof_timestamp(tfe_hw_mgr_ctx,
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&sof_done_event_data.timestamp,
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&sof_done_event_data.boot_time);
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cam_tfe_mgr_cmd_get_sof_timestamp(tfe_hw_mgr_ctx,
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&sof_done_event_data.timestamp,
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&sof_done_event_data.boot_time);
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if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending))
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break;
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if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending))
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break;
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tfe_hw_irq_sof_cb(tfe_hw_mgr_ctx->common.cb_priv,
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CAM_ISP_HW_EVENT_SOF, &sof_done_event_data);
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tfe_hw_irq_sof_cb(tfe_hw_mgr_ctx->common.cb_priv,
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CAM_ISP_HW_EVENT_SOF, &sof_done_event_data);
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}
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break;
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case CAM_ISP_HW_TFE_IN_RDI0:
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@ -5492,22 +5370,17 @@ static int cam_tfe_hw_mgr_handle_hw_eof(
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struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx;
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cam_hw_event_cb_func tfe_hw_irq_eof_cb;
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struct cam_isp_hw_eof_event_data eof_done_event_data;
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int rc = 0;
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tfe_hw_irq_eof_cb =
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tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_EOF];
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switch (event_info->res_id) {
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case CAM_ISP_HW_TFE_IN_CAMIF:
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tfe_hw_mgr_ctx->eof_cnt[event_info->hw_idx]++;
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rc = cam_tfe_hw_mgr_check_irq_for_dual_tfe(tfe_hw_mgr_ctx,
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CAM_ISP_HW_EVENT_EOF);
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if (!rc) {
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if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending))
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break;
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tfe_hw_irq_eof_cb(tfe_hw_mgr_ctx->common.cb_priv,
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CAM_ISP_HW_EVENT_EOF, &eof_done_event_data);
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}
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if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending))
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break;
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tfe_hw_irq_eof_cb(tfe_hw_mgr_ctx->common.cb_priv,
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CAM_ISP_HW_EVENT_EOF, &eof_done_event_data);
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break;
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case CAM_ISP_HW_TFE_IN_RDI0:
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@ -66,9 +66,6 @@ struct cam_tfe_hw_mgr_debug {
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* @cdm_cmd cdm base and length request pointer
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* @last_submit_bl_cmd last submiited CDM BL command data
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* @config_done_complete indicator for configuration complete
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* @sof_cnt sof count value per core, used for dual TFE
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* @epoch_cnt epoch count value per core, used for dual TFE
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* @eof_cnt eof count value per core, used for dual TFE
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* @overflow_pending flat to specify the overflow is pending for the
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* context
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* @cdm_done flag to indicate cdm has finished writing shadow
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@ -113,9 +110,6 @@ struct cam_tfe_hw_mgr_ctx {
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struct cam_cdm_bl_info last_submit_bl_cmd;
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struct completion config_done_complete;
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uint32_t sof_cnt[CAM_TFE_HW_NUM_MAX];
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uint32_t epoch_cnt[CAM_TFE_HW_NUM_MAX];
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uint32_t eof_cnt[CAM_TFE_HW_NUM_MAX];
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atomic_t overflow_pending;
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atomic_t cdm_done;
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uint32_t is_rdi_only_context;
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@ -2003,7 +2003,7 @@ static int cam_tfe_camif_resource_start(
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CAM_DBG(CAM_ISP, "hw id:%d RUP val:%d", camif_res->hw_intf->hw_idx,
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rsrc_data->reg_data->reg_update_cmd_data);
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/*
Disable sof irq debug flag */
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/* Disable sof irq debug flag */
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rsrc_data->enable_sof_irq_debug = false;
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rsrc_data->irq_debug_cnt = 0;
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@ -2015,9 +2015,10 @@ static int cam_tfe_camif_resource_start(
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rsrc_data->common_reg->diag_config);
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}
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/* Enable the irq */
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cam_tfe_irq_config(core_info, rsrc_data->reg_data->subscribe_irq_mask,
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CAM_TFE_TOP_IRQ_REG_NUM, true);
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/* Enable the irq only for master or single tfe usecase */
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if (rsrc_data->sync_mode != CAM_ISP_HW_SYNC_SLAVE)
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cam_tfe_irq_config(core_info, rsrc_data->reg_data->subscribe_irq_mask,
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CAM_TFE_TOP_IRQ_REG_NUM, true);
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/* Program perf counters */
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val = (1 << rsrc_data->reg_data->perf_cnt_start_cmd_shift) |
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