mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 07:37:31 -04:00
clk: qcom: shima: Update frequency tables and VDD data
Update frequency tables, VDD data, PLL configuration and halt check settings for all clock controllers as per the latest frequency plan. Change-Id: I8f698fb7b1d10b980916d7387c3cfb800f8b2d19 Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
This commit is contained in:
Jagadeesh Kona
parent
c322899f4a
commit
51b504feaf
5 changed files with 65 additions and 32 deletions
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@ -42,13 +42,14 @@ enum {
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};
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static struct pll_vco lucid_5lpe_vco[] = {
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{ 249600000, 1750000000, 0 },
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{ 249600000, 1800000000, 0 },
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};
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static struct pll_vco zonda_5lpe_vco[] = {
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{ 595200000, 3600000000, 0 },
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};
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/* 1200MHz Configuration */
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static const struct alpha_pll_config cam_cc_pll0_config = {
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.l = 0x3E,
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.alpha = 0x8000,
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@ -84,7 +85,8 @@ static struct clk_alpha_pll cam_cc_pll0 = {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000},
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -135,6 +137,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
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},
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};
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/* 600MHz Configuration */
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static const struct alpha_pll_config cam_cc_pll1_config = {
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.l = 0x1F,
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.alpha = 0x4000,
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@ -170,7 +173,8 @@ static struct clk_alpha_pll cam_cc_pll1 = {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000},
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -198,6 +202,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
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},
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};
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/* 960MHz Configuration */
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static const struct alpha_pll_config cam_cc_pll2_config = {
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.l = 0x32,
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.alpha = 0x0,
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@ -301,6 +306,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_early = {
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},
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};
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/* 676MHz Configuration */
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static const struct alpha_pll_config cam_cc_pll3_config = {
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.l = 0x23,
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.alpha = 0x3555,
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@ -336,7 +342,8 @@ static struct clk_alpha_pll cam_cc_pll3 = {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000},
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -364,6 +371,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
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},
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};
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/* 676MHz Configuration */
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static const struct alpha_pll_config cam_cc_pll4_config = {
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.l = 0x23,
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.alpha = 0x3555,
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@ -399,7 +407,8 @@ static struct clk_alpha_pll cam_cc_pll4 = {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000},
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -427,6 +436,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
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},
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};
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/* 676MHz Configuration */
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static const struct alpha_pll_config cam_cc_pll5_config = {
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.l = 0x23,
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.alpha = 0x3555,
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@ -462,7 +472,8 @@ static struct clk_alpha_pll cam_cc_pll5 = {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000},
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -490,6 +501,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
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},
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};
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/* 960MHz Configuration */
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static const struct alpha_pll_config cam_cc_pll6_config = {
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.l = 0x32,
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.alpha = 0x0,
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@ -525,7 +537,8 @@ static struct clk_alpha_pll cam_cc_pll6 = {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000},
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -767,6 +780,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = {
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static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(320000000, P_CAM_CC_PLL6_OUT_EVEN, 1.5, 0, 0),
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F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
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{ }
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};
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@ -788,7 +802,8 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 400000000},
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[VDD_LOWER] = 320000000,
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[VDD_LOW] = 400000000},
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},
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};
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@ -1022,12 +1037,18 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = {
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},
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};
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static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
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.cmd_rcgr = 0xa040,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = cam_cc_parent_map_0,
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.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
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.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "cam_cc_ife_0_csid_clk_src",
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@ -1082,7 +1103,7 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = cam_cc_parent_map_0,
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.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
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.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "cam_cc_ife_1_csid_clk_src",
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@ -1137,7 +1158,7 @@ static struct clk_rcg2 cam_cc_ife_2_csid_clk_src = {
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = cam_cc_parent_map_0,
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.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
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.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "cam_cc_ife_2_csid_clk_src",
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@ -1187,7 +1208,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = cam_cc_parent_map_0,
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.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
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.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "cam_cc_ife_lite_csid_clk_src",
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@ -40,7 +40,7 @@ enum {
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};
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static struct pll_vco lucid_5lpe_vco[] = {
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{ 249600000, 1750000000, 0 },
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{ 249600000, 1800000000, 0 },
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};
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/* 1380MHz Configuration */
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@ -79,7 +79,8 @@ static struct clk_alpha_pll disp_cc_pll0 = {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000},
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -62,8 +62,9 @@ static struct clk_alpha_pll gcc_gpll0 = {
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -132,8 +133,9 @@ static struct clk_alpha_pll gcc_gpll10 = {
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -158,8 +160,9 @@ static struct clk_alpha_pll gcc_gpll4 = {
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -184,8 +187,9 @@ static struct clk_alpha_pll gcc_gpll9 = {
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -1229,7 +1233,8 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 100000000},
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[VDD_LOWER] = 50000000,
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[VDD_LOW_L1] = 100000000},
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},
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};
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@ -35,7 +35,7 @@ enum {
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};
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static struct pll_vco lucid_5lpe_vco[] = {
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{ 249600000, 1750000000, 0 },
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{ 249600000, 1800000000, 0 },
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};
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/* 468MHz Configuration */
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@ -74,7 +74,8 @@ static struct clk_alpha_pll gpu_cc_pll0 = {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000},
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -115,7 +116,8 @@ static struct clk_alpha_pll gpu_cc_pll1 = {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000},
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -34,11 +34,12 @@ enum {
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};
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static struct pll_vco lucid_5lpe_vco[] = {
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{ 249600000, 1750000000, 0 },
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{ 249600000, 1800000000, 0 },
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};
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/* 604.8MHz Configuration */
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static const struct alpha_pll_config video_pll0_config = {
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.l = 0x25,
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.l = 0x1F,
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.alpha = 0x8000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002261,
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@ -72,11 +73,13 @@ static struct clk_alpha_pll video_pll0 = {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000},
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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/* 840MHz Configuration */
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static const struct alpha_pll_config video_pll1_config = {
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.l = 0x2B,
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.alpha = 0xC000,
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@ -112,7 +115,8 @@ static struct clk_alpha_pll video_pll1 = {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1750000000},
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[VDD_NOMINAL] = 1750000000,
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[VDD_HIGH] = 1800000000},
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},
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},
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};
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@ -348,7 +352,7 @@ static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
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static struct clk_branch video_cc_ahb_clk = {
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.halt_reg = 0xe58,
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.halt_check = BRANCH_HALT,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0xe58,
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.hwcg_bit = 1,
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.clkr = {
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@ -446,7 +450,7 @@ static struct clk_branch video_cc_mvs1_div2_clk = {
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static struct clk_branch video_cc_mvs1c_clk = {
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.halt_reg = 0xcd4,
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.halt_check = BRANCH_HALT_VOTED,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0xcd4,
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.enable_mask = BIT(0),
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