diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index c42aaad59d8c..d1dbcc55cdea 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -136,6 +136,9 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 		[PLL_OFF_STATUS] = 0x30,
 		[PLL_OFF_OPMODE] = 0x38,
 		[PLL_OFF_ALPHA_VAL] = 0x40,
+		[PLL_OFF_SSC_DELTA_ALPHA] = 0x48,
+		[PLL_OFF_SSC_NUM_STEPS] = 0x4C,
+		[PLL_OFF_SSC_UPDATE_RATE] = 0x50,
 	},
 	[CLK_ALPHA_PLL_TYPE_ZONDA] =  {
 		[PLL_OFF_L_VAL] = 0x04,
@@ -148,6 +151,8 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 		[PLL_OFF_TEST_CTL_U] = 0x20,
 		[PLL_OFF_TEST_CTL_U1] = 0x24,
 		[PLL_OFF_OPMODE] = 0x28,
+		[PLL_OFF_SSC_DELTA_ALPHA] = 0x2C,
+		[PLL_OFF_SSC_UPDATE_RATE] =  0x30,
 		[PLL_OFF_STATUS] = 0x38,
 	},
 	[CLK_ALPHA_PLL_TYPE_LUCID_5LPE] = {
@@ -165,6 +170,9 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 		[PLL_OFF_STATUS] = 0x30,
 		[PLL_OFF_OPMODE] = 0x38,
 		[PLL_OFF_ALPHA_VAL] = 0x40,
+		[PLL_OFF_SSC_DELTA_ALPHA] = 0x48,
+		[PLL_OFF_SSC_NUM_STEPS] = 0x4C,
+		[PLL_OFF_SSC_UPDATE_RATE] = 0x50,
 	},
 	[CLK_ALPHA_PLL_TYPE_ZONDA_5LPE] = {
 		[PLL_OFF_L_VAL] = 0x04,
@@ -177,6 +185,8 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 		[PLL_OFF_TEST_CTL_U] = 0x20,
 		[PLL_OFF_TEST_CTL_U1] = 0x24,
 		[PLL_OFF_OPMODE] = 0x28,
+		[PLL_OFF_SSC_DELTA_ALPHA] = 0x2C,
+		[PLL_OFF_SSC_UPDATE_RATE] =  0x30,
 		[PLL_OFF_STATUS] = 0x38,
 	},
 	[CLK_ALPHA_PLL_TYPE_REGERA] =  {
@@ -1800,6 +1810,8 @@ static void clk_alpha_pll_zonda_list_registers(struct seq_file *f,
 		{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},
 		{"PLL_OPMODE", PLL_OFF_OPMODE},
 		{"PLL_STATUS", PLL_OFF_STATUS},
+		{"PLL_SSC_DELTA_ALPHA", PLL_OFF_SSC_DELTA_ALPHA},
+		{"PLL_SSC_UPDATE_RATE", PLL_OFF_SSC_UPDATE_RATE},
 	};
 
 	static struct clk_register_data data1[] = {
@@ -3067,6 +3079,9 @@ static void lucid_pll_list_registers(struct seq_file *f,
 		{"PLL_STATUS", PLL_OFF_STATUS},
 		{"PLL_OPMODE", PLL_OFF_OPMODE},
 		{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},
+		{"PLL_SSC_DELTA_ALPHA", PLL_OFF_SSC_DELTA_ALPHA},
+		{"PLL_SSC_NUM_STEPS", PLL_OFF_SSC_NUM_STEPS},
+		{"PLL_SSC_UPDATE_RATE", PLL_OFF_SSC_UPDATE_RATE},
 	};
 
 	static struct clk_register_data data1[] = {
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 2d097aa1f1a0..08079e44aeca 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2015-2016, 2018-2019, The Linux Foundation.
+ * Copyright (c) 2015-2016, 2018-2020 The Linux Foundation.
  * All rights reserved.
  */
 
@@ -46,6 +46,9 @@ enum {
 	PLL_OFF_OPMODE,
 	PLL_OFF_FRAC,
 	PLL_OFF_CAL_VAL,
+	PLL_OFF_SSC_DELTA_ALPHA,
+	PLL_OFF_SSC_NUM_STEPS,
+	PLL_OFF_SSC_UPDATE_RATE,
 	PLL_OFF_MAX_REGS
 };
 
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 49be829d1454..2ee866e1ea55 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2013, 2016-2020, The Linux Foundation. All rights reserved. */
 
 #ifndef __QCOM_CLK_RCG_H__
 #define __QCOM_CLK_RCG_H__
@@ -159,6 +159,7 @@ struct clk_rcg2 {
 	u8			flags;
 #define FORCE_ENABLE_RCG	BIT(0)
 #define HW_CLK_CTRL_MODE	BIT(1)
+#define DFS_SUPPORT		BIT(2)
 };
 
 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index a427c7e90fc8..30a3abecebfc 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -451,36 +451,47 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 static void clk_rcg2_list_registers(struct seq_file *f, struct clk_hw *hw)
 {
 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-	int i = 0, size = 0, val;
-
-	static struct clk_register_data data[] = {
-		{"CMD_RCGR", 0x0},
-		{"CFG_RCGR", 0x4},
-	};
+	static struct clk_register_data *data;
+	int i, val;
 
 	static struct clk_register_data data1[] = {
+		{"CMD_RCGR", 0x0},
+		{"CFG_RCGR", 0x4},
+		{ },
+	};
+
+	static struct clk_register_data data2[] = {
 		{"CMD_RCGR", 0x0},
 		{"CFG_RCGR", 0x4},
 		{"M_VAL", 0x8},
 		{"N_VAL", 0xC},
 		{"D_VAL", 0x10},
+		{ },
 	};
 
-	if (rcg->mnd_width) {
-		size = ARRAY_SIZE(data1);
-		for (i = 0; i < size; i++) {
-			regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +
-					data1[i].offset), &val);
-			seq_printf(f, "%20s: 0x%.8x\n",	data1[i].name, val);
-		}
-	} else {
-		size = ARRAY_SIZE(data);
-		for (i = 0; i < size; i++) {
-			regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +
+	static struct clk_register_data data3[] = {
+		{"CMD_RCGR", 0x0},
+		{"CFG_RCGR", 0x4},
+		{"M_VAL", 0x8},
+		{"N_VAL", 0xC},
+		{"D_VAL", 0x10},
+		{"CMD_DFSR", 0x14},
+		{ },
+	};
+
+	if (rcg->flags & DFS_SUPPORT)
+		data = data3;
+	else if (rcg->mnd_width)
+		data = data2;
+	else
+		data = data1;
+
+	for (i = 0; data[i].name != NULL; i++) {
+		regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +
 				data[i].offset), &val);
-			seq_printf(f, "%20s: 0x%.8x\n",	data[i].name, val);
-		}
+		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
 	}
+
 }
 
 /* Return the nth supported frequency for a given clock. */
@@ -1596,6 +1607,8 @@ static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
 	u32 val;
 	int ret;
 
+	rcg->flags |= DFS_SUPPORT;
+
 	ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);
 	if (ret)
 		return -EINVAL;