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clk: qcom: Add support for NPU QDSS clocks

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QDSS clocks are required for npu use cases
hence enable them.

Change-Id: I741d65677b46d2b3ca4d46ab14f4ee03ae262555
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
This commit is contained in:
Veera Vegivada 2020-11-23 21:20:09 +05:30
commit 51be9de76c
2 changed files with 58 additions and 2 deletions
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28
drivers/clk/qcom/gcc-sm8150.c
View file

@ -2202,6 +2202,19 @@ static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
},
};
static struct clk_branch gcc_npu_at_clk = {
.halt_reg = 0x4d010,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4d010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_at_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_axi_clk = {
.halt_reg = 0x4d008,
.halt_check = BRANCH_VOTED,
@ -2266,6 +2279,19 @@ static struct clk_branch gcc_npu_gpll0_div_clk_src = {
},
};
static struct clk_branch gcc_npu_trig_clk = {
.halt_reg = 0x4d00c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4d00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_trig_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_phy_refgen_clk = {
.halt_reg = 0x6f02c,
.halt_check = BRANCH_HALT,
@ -4056,10 +4082,12 @@ static struct clk_regmap *gcc_sm8150_clocks[] = {
[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
[GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
[GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
[GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,

32
drivers/clk/qcom/npucc-sm8150.c
View file

@ -137,7 +137,7 @@ static const struct parent_map npu_cc_parent_map_0[] = {
};
static const struct clk_parent_data npu_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo", },
{ .fw_name = "bi_tcxo" },
{ .hw = &npu_cc_pll1.clkr.hw },
{ .hw = &npu_cc_pll0.clkr.hw },
{ .fw_name = "gcc_npu_gpll0_clk_src", .name = "gcc_npu_gpll0_clk_src" },
@ -170,7 +170,7 @@ static const struct parent_map npu_cc_parent_map_1[] = {
};
static const struct clk_parent_data npu_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo", },
{ .fw_name = "bi_tcxo" },
{ .hw = &npu_cc_pll1.clkr.hw },
{ .hw = &npu_cc_crc_div.hw },
{ .fw_name = "gcc_npu_gpll0_clk_src", .name = "gcc_npu_gpll0_clk_src" },
@ -383,6 +383,32 @@ static struct clk_branch npu_cc_conf_noc_ahb_clk = {
},
};
static struct clk_branch npu_cc_npu_core_apb_clk = {
.halt_reg = 0x1080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "npu_cc_npu_core_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch npu_cc_npu_core_atb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "npu_cc_npu_core_atb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch npu_cc_npu_core_clk = {
.halt_reg = 0x1048,
.halt_check = BRANCH_HALT,
@ -514,6 +540,8 @@ static struct clk_regmap *npu_cc_sm8150_clocks[] = {
[NPU_CC_CAL_DP_CLK_SRC] = &npu_cc_cal_dp_clk_src.clkr,
[NPU_CC_COMP_NOC_AXI_CLK] = &npu_cc_comp_noc_axi_clk.clkr,
[NPU_CC_CONF_NOC_AHB_CLK] = &npu_cc_conf_noc_ahb_clk.clkr,
[NPU_CC_NPU_CORE_APB_CLK] = &npu_cc_npu_core_apb_clk.clkr,
[NPU_CC_NPU_CORE_ATB_CLK] = &npu_cc_npu_core_atb_clk.clkr,
[NPU_CC_NPU_CORE_CLK] = &npu_cc_npu_core_clk.clkr,
[NPU_CC_NPU_CORE_CLK_SRC] = &npu_cc_npu_core_clk_src.clkr,
[NPU_CC_NPU_CORE_CTI_CLK] = &npu_cc_npu_core_cti_clk.clkr,