From 51d46d049b239f4de8d6ea1e336cbeabc8df7a5a Mon Sep 17 00:00:00 2001
From: Mayank Grover <groverm@codeaurora.org>
Date: Thu, 11 Mar 2021 16:37:45 +0530
Subject: [PATCH] drivers: pinctrl: Add support to access tlmm spare registers

Add support to read and write SPARE registers in TLMM block.

Change-Id: I6426b86510256983b509c5f48c2ab02f80b48ef8
Signed-off-by: Mayank Grover <groverm@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c   | 40 ++++++++++++++++++++++++++++
 drivers/pinctrl/qcom/pinctrl-msm.h   | 12 +++++++++
 include/linux/pinctrl/qcom-pinctrl.h |  6 ++++-
 3 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 85f8548d04ee..4f5442c37985 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -37,6 +37,7 @@
 #define MAX_NR_TILES 4
 #define PS_HOLD_OFFSET 0x820
 #define QUP_MASK       GENMASK(5, 0)
+#define SPARE_MASK     GENMASK(15, 8)
 
 /**
  * struct msm_pinctrl - state for a pinctrl-msm device
@@ -1505,6 +1506,45 @@ int msm_qup_read(unsigned int mode)
 	return -ENOENT;
 }
 
+int msm_spare_write(int spare_reg, u32 val)
+{
+	u32 offset;
+	const struct msm_spare_tlmm *regs = msm_pinctrl_data->soc->spare_regs;
+	int num_regs =  msm_pinctrl_data->soc->nspare_regs;
+
+	if (!regs || spare_reg >= num_regs)
+		return -ENOENT;
+
+	offset = regs[spare_reg].offset;
+	if (offset != 0) {
+		writel_relaxed(val & SPARE_MASK,
+				msm_pinctrl_data->regs[0] + offset);
+		return 0;
+	}
+
+	return -ENOENT;
+}
+EXPORT_SYMBOL(msm_spare_write);
+
+int msm_spare_read(int spare_reg)
+{
+	u32 offset, val;
+	const struct msm_spare_tlmm *regs = msm_pinctrl_data->soc->spare_regs;
+	int num_regs =  msm_pinctrl_data->soc->nspare_regs;
+
+	if (!regs || spare_reg >= num_regs)
+		return -ENOENT;
+
+	offset = regs[spare_reg].offset;
+	if (offset != 0) {
+		val = readl_relaxed(msm_pinctrl_data->regs[0] + offset);
+		return val & SPARE_MASK;
+	}
+
+	return -ENOENT;
+}
+EXPORT_SYMBOL(msm_spare_read);
+
 /*
  * msm_gpio_mpm_wake_set - API to make interrupt wakeup capable
  * @dev:        Device corrsponding to pinctrl
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 5bcac8855500..687b4a2f3435 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -125,6 +125,16 @@ struct pinctrl_qup {
 	u32 offset;
 };
 
+/*
+ * struct msm_spare_tlmm - TLMM spare registers config
+ * @spare_reg:	spare register number
+ * @offset:	Offset of spare register
+ */
+struct msm_spare_tlmm {
+	int spare_reg;
+	u32 offset;
+};
+
 /**
  * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
  * @gpio:          The GPIOs that are wakeup capable
@@ -169,6 +179,8 @@ struct msm_pinctrl_soc_data {
 	unsigned int n_no_wake_gpios;
 	struct pinctrl_qup *qup_regs;
 	unsigned int nqup_regs;
+	const struct msm_spare_tlmm *spare_regs;
+	unsigned int nspare_regs;
 	struct msm_dir_conn *dir_conn;
 };
 
diff --git a/include/linux/pinctrl/qcom-pinctrl.h b/include/linux/pinctrl/qcom-pinctrl.h
index a3629fb09802..14b20ed634da 100644
--- a/include/linux/pinctrl/qcom-pinctrl.h
+++ b/include/linux/pinctrl/qcom-pinctrl.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019,2021 The Linux Foundation. All rights reserved.
  */
 
 #ifndef __LINUX_PINCTRL_MSM_H__
@@ -15,4 +15,8 @@ int msm_qup_read(u32 mode);
 /* API to write to mpm_wakeup registers */
 int msm_gpio_mpm_wake_set(unsigned int gpio, bool enable);
 
+/* APIS to TLMM Spare registers */
+int msm_spare_write(int spare_reg, u32 val);
+int msm_spare_read(int spare_reg);
+
 #endif /* __LINUX_PINCTRL_MSM_H__ */