Merge "ARM: dts: msm: Add dummy clock nodes for clock controllers for YUPIK"

qcom/shima-gdsc.dtsi

@@ -32,6 +32,13 @@
 		status = "disabled";
 	};
 
+	gcc_usb30_sec_gdsc: qcom,gdsc@19e004 {
+		compatible = "qcom,gdsc";
+		reg = <0x19e004 0x4>;
+		regulator-name = "gcc_usb30_sec_gdsc";
+		status = "disabled";
+	};
+
 	hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c {
 		compatible = "qcom,gdsc";
 		reg = <0x17d05c 0x4>;
@@ -220,4 +227,11 @@
 		regulator-name = "video_cc_mvs1c_gdsc";
 		status = "disabled";
 	};
+
+	video_cc_mvsc_gdsc: qcom,gdsc@aaf2004 {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf2004 0x4>;
+		regulator-name = "video_cc_mvsc_gdsc";
+		status = "disabled";
+	};
 };

qcom/yupik.dtsi

@@ -1,3 +1,10 @@
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,camcc-yupik.h>
+#include <dt-bindings/clock/qcom,dispcc-yupik.h>
+#include <dt-bindings/clock/qcom,gcc-yupik.h>
+#include <dt-bindings/clock/qcom,gpucc-yupik.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,videocc-yupik.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -263,7 +270,227 @@
 			status = "disabled";
 		};
 	};
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <76800000>;
+			clock-output-names = "xo_board";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "sleep_clk";
+			#clock-cells = <0>;
+		};
+
+		pcie_0_pipe_clk: pcie-0-pipe-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "pcie_0_pipe_clk";
+			#clock-cells = <0>;
+		};
+
+		pcie_1_pipe_clk: pcie-1-pipe-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "pcie_1_pipe_clk";
+			#clock-cells = <0>;
+		};
+
+		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+			#clock-cells = <0>;
+		};
+	};
+
+	bi_tcxo: bi_tcxo {
+		compatible = "fixed-factor-clock";
+		clock-mult = <1>;
+		clock-div = <4>;
+		clocks = <&xo_board>;
+		#clock-cells = <0>;
+	};
+
+	bi_tcxo_ao: bi_tcxo_ao {
+		compatible = "fixed-factor-clock";
+		clock-mult = <1>;
+		clock-div = <4>;
+		clocks = <&xo_board>;
+		#clock-cells = <0>;
+	};
+
+	aopcc: qcom,aopcc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "aopcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	rpmhcc: qcom,rpmhcc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "rpmhcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gcc: clock-controller@100000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	camcc: clock-controller@ad00000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "camcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	dispcc: clock-controller@af00000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "dispcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gpucc: clock-controller@3d90000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gpucc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	videocc: clock-controller@aaf0000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "videocc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
 };
 
+#include "shima-gdsc.dtsi"
 #include "yupik-pinctrl.dtsi"
 #include "yupik-stub-regulator.dtsi"
+
+&gcc_pcie_0_gdsc {
+	compatible = "regulator-fixed";
+	qcom,support-hw-trigger;
+	status = "ok"
+};
+
+&gcc_pcie_1_gdsc {
+	compatible = "regulator-fixed";
+	qcom,support-hw-trigger;
+	status = "ok"
+};
+
+&gcc_ufs_phy_gdsc {
+	compatible = "regulator-fixed";
+	qcom,support-hw-trigger;
+	status = "ok"
+};
+
+&gcc_usb30_prim_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};
+
+&gcc_usb30_sec_gdsc {
+	compatible = "regulator-fixed";
+	qcom,support-hw-trigger;
+	status = "ok"
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};
+
+&hlos1_vote_turing_mmu_tbu0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};
+
+&hlos1_vote_turing_mmu_tbu1_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};
+
+&cam_cc_titan_top_gdsc {
+	compatible = "regulator-fixed";
+	reg = <0xad0c194 0x4>;
+	status = "ok"
+};
+
+&cam_cc_bps_gdsc {
+	compatible = "regulator-fixed";
+	qcom,support-hw-trigger;
+	status = "ok"
+};
+
+&cam_cc_ife_0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};
+
+&cam_cc_ife_1_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};
+
+&cam_cc_ife_2_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};
+
+&cam_cc_ipe_0_gdsc {
+	compatible = "regulator-fixed";
+	qcom,support-hw-trigger;
+	status = "ok"
+};
+
+&disp_cc_mdss_core_gdsc {
+	compatible = "regulator-fixed";
+	reg = <0xaf01004 0x4>;
+	qcom,support-hw-trigger;
+	status = "ok"
+};
+
+&gpu_cx_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};
+
+&gpu_gx_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};
+
+&video_cc_mvs0_gdsc {
+	compatible = "regulator-fixed";
+	reg = <0xaaf3004 0x4>;
+	qcom,support-hw-trigger;
+	status = "ok"
+};
+
+&video_cc_mvsc_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok"
+};