mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 13:49:24 -04:00
Merge "msm: kgsl: Use bulk clock functions for GMU"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
5202070c22
14 changed files with 170 additions and 251 deletions
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@ -885,6 +885,40 @@ static void adreno_of_get_ca_aware_properties(struct adreno_device *adreno_dev,
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}
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}
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/* Dynamically build the OPP table for the GPU device */
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static void adreno_build_opp_table(struct device *dev, struct kgsl_pwrctrl *pwr)
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{
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unsigned long freq = 0;
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int i;
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/*
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* First an annoying step: Some targets have clock drivers that
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* "helpfully" builds a OPP table for us but usually it is wrong.
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* Go through and filter out unsupported frequencies
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*/
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for (;;) {
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struct dev_pm_opp *opp = dev_pm_opp_find_freq_ceil(dev, &freq);
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if (IS_ERR(opp))
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break;
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for (i = 0; i < pwr->num_pwrlevels; i++) {
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if (freq == pwr->pwrlevels[i].gpu_freq)
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break;
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}
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if (i == pwr->num_pwrlevels)
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dev_pm_opp_remove(dev, freq);
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freq++;
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}
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/* Now add all of our supported frequencies into the tree */
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for (i = 0; i < pwr->num_pwrlevels; i++)
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dev_pm_opp_add(dev, pwr->pwrlevels[i].gpu_freq, 0);
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}
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static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev,
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struct device_node *node)
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{
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@ -893,45 +927,49 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev,
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struct device_node *child;
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int ret;
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/* ADD the GPU OPP table if we define it */
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if (of_find_property(device->pdev->dev.of_node,
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"operating-points-v2", NULL)) {
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ret = dev_pm_opp_of_add_table(&device->pdev->dev);
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if (ret) {
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dev_err(device->dev,
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"Unable to set the GPU OPP table: %d\n", ret);
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return ret;
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}
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}
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pwr->num_pwrlevels = 0;
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for_each_child_of_node(node, child) {
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unsigned int index, freq = 0;
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u32 index, freq = 0, voltage, bus;
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struct kgsl_pwrlevel *level;
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if (of_property_read_u32(child, "reg", &index)) {
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dev_err(device->dev,
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"%pOF: powerlevel index not found\n", child);
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of_node_put(child);
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return -EINVAL;
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ret = of_property_read_u32(child, "reg", &index);
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if (ret) {
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dev_err(device->dev, "%pOF: powerlevel index not found\n",
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child);
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goto out;
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}
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if (of_property_read_u32(child, "qcom,gpu-freq", &freq)) {
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dev_err(device->dev,
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"%pOF: Unable to read qcom,gpu-freq\n", child);
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of_node_put(child);
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return -EINVAL;
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ret = of_property_read_u32(child, "qcom,gpu-freq", &freq);
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if (ret) {
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dev_err(device->dev, "%pOF: Unable to read qcom,gpu-freq\n",
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child);
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goto out;
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}
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/* Ignore "zero" powerlevels */
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if (!freq)
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continue;
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ret = of_property_read_u32(child, "qcom,level", &voltage);
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if (ret) {
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dev_err(device->dev, "%pOF: Unable to read qcom,level\n",
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child);
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goto out;
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}
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ret = kgsl_of_property_read_ddrtype(child, "qcom,bus-freq",
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&bus);
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if (ret) {
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dev_err(device->dev, "%pOF:Unable to read qcom,bus-freq\n",
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child);
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goto out;
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}
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if (index >= KGSL_MAX_PWRLEVELS) {
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dev_err(device->dev,
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"%pOF: Pwrlevel index %d is out of range\n",
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child, index);
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dev_err(device->dev, "%pOF: Pwrlevel index %d is out of range\n",
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child, index);
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continue;
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}
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@ -941,20 +979,12 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev,
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level = &pwr->pwrlevels[index];
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level->gpu_freq = freq;
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level->bus_freq = bus;
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level->voltage_level = voltage;
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of_property_read_u32(child, "qcom,acd-level",
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&level->acd_level);
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ret = kgsl_of_property_read_ddrtype(child,
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"qcom,bus-freq", &level->bus_freq);
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if (ret) {
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dev_err(device->dev,
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"%pOF: Couldn't read the bus frequency for power level %d\n",
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child, index);
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of_node_put(child);
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return ret;
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}
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level->bus_min = level->bus_freq;
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kgsl_of_property_read_ddrtype(child,
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"qcom,bus-min", &level->bus_min);
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@ -964,7 +994,11 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev,
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"qcom,bus-max", &level->bus_max);
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}
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adreno_build_opp_table(&device->pdev->dev, pwr);
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return 0;
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out:
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of_node_put(child);
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return ret;
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}
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static void adreno_of_get_initial_pwrlevel(struct adreno_device *adreno_dev,
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@ -2858,8 +2858,8 @@ int adreno_dispatcher_idle(struct adreno_device *adreno_dev)
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* Ensure that this function is not called when dispatcher
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* mutex is held and device is started
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*/
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if (mutex_is_locked(&dispatcher->mutex) &&
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(__mutex_owner(&dispatcher->mutex) == current))
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if (WARN_ON(mutex_is_locked(&dispatcher->mutex)))
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return -EDEADLK;
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adreno_get_gpu_halt(adreno_dev);
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@ -4346,7 +4346,7 @@ static vm_fault_t
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kgsl_gpumem_vm_fault(struct vm_fault *vmf)
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{
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struct kgsl_mem_entry *entry = vmf->vma->vm_private_data;
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int ret;
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vm_fault_t ret;
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if (!entry)
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return VM_FAULT_SIGBUS;
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@ -4354,7 +4354,7 @@ kgsl_gpumem_vm_fault(struct vm_fault *vmf)
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return VM_FAULT_SIGBUS;
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ret = entry->memdesc.ops->vmfault(&entry->memdesc, vmf->vma, vmf);
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if ((ret == 0) || (ret == VM_FAULT_NOPAGE))
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if (!ret || ret == VM_FAULT_NOPAGE)
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entry->priv->gpumem_mapped += PAGE_SIZE;
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return ret;
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@ -4776,7 +4776,7 @@ static int _register_device(struct kgsl_device *device)
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}
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device->dev->dma_mask = &dma_mask;
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arch_setup_dma_ops(device->dev, 0, 0, NULL, false);
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set_dma_ops(device->dev, NULL);
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dev_set_drvdata(&device->pdev->dev, device);
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return 0;
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@ -163,8 +163,8 @@ struct kgsl_memdesc;
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struct kgsl_memdesc_ops {
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unsigned int vmflags;
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int (*vmfault)(struct kgsl_memdesc *memdesc, struct vm_area_struct *vma,
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struct vm_fault *vmf);
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vm_fault_t (*vmfault)(struct kgsl_memdesc *memdesc,
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struct vm_area_struct *vma, struct vm_fault *vmf);
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void (*free)(struct kgsl_memdesc *memdesc);
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int (*map_kernel)(struct kgsl_memdesc *memdesc);
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void (*unmap_kernel)(struct kgsl_memdesc *memdesc);
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@ -4,6 +4,7 @@
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*/
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/io.h>
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@ -559,7 +560,7 @@ static int gmu_dcvs_set(struct kgsl_device *device,
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struct rpmh_arc_vals {
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unsigned int num;
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uint16_t val[MAX_GX_LEVELS];
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const u16 *val;
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};
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static const char gfx_res_id[] = "gfx.lvl";
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@ -584,22 +585,9 @@ enum rpmh_vote_type {
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static int rpmh_arc_cmds(struct gmu_device *gmu,
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struct rpmh_arc_vals *arc, const char *res_id)
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{
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unsigned int len;
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size_t len = 0;
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memset(arc, 0, sizeof(*arc));
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len = cmd_db_read_aux_data_len(res_id);
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if (len == 0)
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return -EINVAL;
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if (len > (MAX_GX_LEVELS << 1)) {
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dev_err(&gmu->pdev->dev,
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"gfx cmddb size %d larger than alloc buf %d of %s\n",
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len, (MAX_GX_LEVELS << 1), res_id);
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return -EINVAL;
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}
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cmd_db_read_aux_data(res_id, (uint8_t *)arc->val, len);
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arc->val = cmd_db_read_aux_data(res_id, &len);
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/*
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* cmd_db_read_aux_data() gives us a zero-padded table of
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@ -703,45 +691,22 @@ static int rpmh_arc_votes_init(struct kgsl_device *device,
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{
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unsigned int num_freqs;
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u16 vlvl_tbl[MAX_GX_LEVELS];
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unsigned int *freq_tbl;
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int i;
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struct dev_pm_opp *opp;
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if (type == GMU_ARC_VOTE)
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return rpmh_gmu_arc_votes_init(gmu, pri_rail, sec_rail);
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num_freqs = gmu->num_gpupwrlevels;
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freq_tbl = gmu->gpu_freqs;
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if (num_freqs > pri_rail->num || num_freqs > MAX_GX_LEVELS) {
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if (num_freqs > pri_rail->num) {
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dev_err(&gmu->pdev->dev,
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"Defined more GPU DCVS levels than RPMh can support\n");
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return -EINVAL;
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}
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memset(vlvl_tbl, 0, sizeof(vlvl_tbl));
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/* Get the values from OPP API */
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for (i = 0; i < num_freqs; i++) {
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/* Hardcode VLVL 0 because it is not present in OPP */
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if (freq_tbl[i] == 0) {
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vlvl_tbl[i] = 0;
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continue;
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}
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opp = dev_pm_opp_find_freq_exact(&device->pdev->dev,
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freq_tbl[i], true);
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if (IS_ERR(opp)) {
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dev_err(&gmu->pdev->dev,
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"Failed to find opp freq %d for GPU\n",
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freq_tbl[i]);
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return PTR_ERR(opp);
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}
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vlvl_tbl[i] = dev_pm_opp_get_voltage(opp);
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dev_pm_opp_put(opp);
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}
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for (i = 0; i < num_freqs; i++)
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vlvl_tbl[i] = gmu->pwrlevels[i].level;
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return setup_volt_dependency_tbl(gmu->rpmh_votes.gx_votes, pri_rail,
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sec_rail, vlvl_tbl, num_freqs);
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@ -978,34 +943,6 @@ static int gmu_reg_probe(struct kgsl_device *device)
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return 0;
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}
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static int gmu_clocks_probe(struct gmu_device *gmu, struct device_node *node)
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{
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const char *cname;
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struct property *prop;
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struct clk *c;
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int i = 0;
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of_property_for_each_string(node, "clock-names", prop, cname) {
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c = devm_clk_get(&gmu->pdev->dev, cname);
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if (IS_ERR(c)) {
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dev_err(&gmu->pdev->dev,
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"dt: Couldn't get GMU clock: %s\n", cname);
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return PTR_ERR(c);
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}
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if (i >= MAX_GMU_CLKS) {
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dev_err(&gmu->pdev->dev,
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"dt: too many GMU clocks defined\n");
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return -EINVAL;
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}
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gmu->clks[i++] = c;
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}
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return 0;
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}
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static int gmu_regulators_probe(struct gmu_device *gmu,
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struct device_node *node)
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{
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@ -1218,7 +1155,7 @@ static int gmu_probe(struct kgsl_device *device, struct device_node *node)
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struct kgsl_hfi *hfi;
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struct kgsl_pwrctrl *pwr = &device->pwrctrl;
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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int i = 0, ret = -ENXIO, index = 0;
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int i = 0, ret = -ENXIO, index;
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gmu = kzalloc(sizeof(struct gmu_device), GFP_KERNEL);
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|
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@ -1242,11 +1179,20 @@ static int gmu_probe(struct kgsl_device *device, struct device_node *node)
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if (ret)
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goto error;
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|
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/* Set up GMU clocks */
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ret = gmu_clocks_probe(gmu, node);
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if (ret)
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ret = devm_clk_bulk_get_all(&gmu->pdev->dev, &gmu->clks);
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if (ret < 0)
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goto error;
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|
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gmu->num_clks = ret;
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|
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/* Get a pointer to the GMU clock */
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gmu->gmu_clk = kgsl_of_clk_by_name(gmu->clks, gmu->num_clks, "gmu_clk");
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if (!gmu->gmu_clk) {
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dev_err(&gmu->pdev->dev, "Couldn't get gmu_clk\n");
|
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ret = -ENODEV;
|
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goto error;
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}
|
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|
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/* Set up GMU IOMMU and shared memory with GMU */
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ret = gmu_iommu_init(gmu, node);
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if (ret)
|
||||
|
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@ -1288,12 +1234,21 @@ static int gmu_probe(struct kgsl_device *device, struct device_node *node)
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tasklet_init(&hfi->tasklet, hfi_receiver, (unsigned long) gmu);
|
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hfi->kgsldev = device;
|
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|
||||
/* Add a dummy level for "off" that the GMU expects */
|
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gmu->gpu_freqs[index++] = 0;
|
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if (WARN(pwr->num_pwrlevels + 1 > ARRAY_SIZE(gmu->pwrlevels),
|
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"Too many GPU powerlevels for the GMU HFI\n")) {
|
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ret = -EINVAL;
|
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goto error;
|
||||
}
|
||||
|
||||
/* Add a dummy level for "off" because the GMU expects it */
|
||||
gmu->pwrlevels[0].freq = 0;
|
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gmu->pwrlevels[0].level = 0;
|
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|
||||
/* GMU power levels are in ascending order */
|
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for (i = pwr->num_pwrlevels - 1; i >= 0; i--)
|
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gmu->gpu_freqs[index++] = pwr->pwrlevels[i].gpu_freq;
|
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for (index = 1, i = pwr->num_pwrlevels - 1; i >= 0; i--, index++) {
|
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gmu->pwrlevels[index].freq = pwr->pwrlevels[i].gpu_freq;
|
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gmu->pwrlevels[index].level = pwr->pwrlevels[i].voltage_level;
|
||||
}
|
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|
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gmu->num_gpupwrlevels = pwr->num_pwrlevels + 1;
|
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|
||||
|
|
@ -1331,48 +1286,30 @@ error:
|
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static int gmu_enable_clks(struct kgsl_device *device)
|
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{
|
||||
struct gmu_device *gmu = KGSL_GMU_DEVICE(device);
|
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int ret, j = 0;
|
||||
int ret;
|
||||
|
||||
if (IS_ERR_OR_NULL(gmu->clks[0]))
|
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return -EINVAL;
|
||||
|
||||
ret = clk_set_rate(gmu->clks[0], GMU_FREQUENCY);
|
||||
ret = clk_set_rate(gmu->gmu_clk, GMU_FREQUENCY);
|
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if (ret) {
|
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dev_err(&gmu->pdev->dev, "fail to set default GMU clk freq %d\n",
|
||||
GMU_FREQUENCY);
|
||||
dev_err(&gmu->pdev->dev, "Unable to set GMU clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
while ((j < MAX_GMU_CLKS) && gmu->clks[j]) {
|
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ret = clk_prepare_enable(gmu->clks[j]);
|
||||
if (ret) {
|
||||
dev_err(&gmu->pdev->dev,
|
||||
"fail to enable gpucc clk idx %d\n",
|
||||
j);
|
||||
return ret;
|
||||
}
|
||||
j++;
|
||||
ret = clk_bulk_prepare_enable(gmu->num_clks, gmu->clks);
|
||||
if (ret) {
|
||||
dev_err(&gmu->pdev->dev, "Cannot enable GMU clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
set_bit(GMU_CLK_ON, &device->gmu_core.flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gmu_disable_clks(struct kgsl_device *device)
|
||||
static void gmu_disable_clks(struct kgsl_device *device)
|
||||
{
|
||||
struct gmu_device *gmu = KGSL_GMU_DEVICE(device);
|
||||
int j = 0;
|
||||
|
||||
if (IS_ERR_OR_NULL(gmu->clks[0]))
|
||||
return 0;
|
||||
|
||||
while ((j < MAX_GMU_CLKS) && gmu->clks[j]) {
|
||||
clk_disable_unprepare(gmu->clks[j]);
|
||||
j++;
|
||||
}
|
||||
|
||||
clk_bulk_disable_unprepare(gmu->num_clks, gmu->clks);
|
||||
clear_bit(GMU_CLK_ON, &device->gmu_core.flags);
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -1619,7 +1556,6 @@ static void gmu_remove(struct kgsl_device *device)
|
|||
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
|
||||
struct gmu_device *gmu = KGSL_GMU_DEVICE(device);
|
||||
struct kgsl_hfi *hfi;
|
||||
int i = 0;
|
||||
|
||||
if (gmu == NULL || gmu->pdev == NULL)
|
||||
return;
|
||||
|
|
@ -1635,11 +1571,6 @@ static void gmu_remove(struct kgsl_device *device)
|
|||
|
||||
clear_bit(ADRENO_ACD_CTRL, &adreno_dev->pwrctrl_flag);
|
||||
|
||||
while ((i < MAX_GMU_CLKS) && gmu->clks[i]) {
|
||||
gmu->clks[i] = NULL;
|
||||
i++;
|
||||
}
|
||||
|
||||
icc_put(gmu->icc_path);
|
||||
|
||||
if (gmu->fw_image) {
|
||||
|
|
@ -1649,13 +1580,6 @@ static void gmu_remove(struct kgsl_device *device)
|
|||
|
||||
gmu_memory_close(gmu);
|
||||
|
||||
for (i = 0; i < MAX_GMU_CLKS; i++) {
|
||||
if (gmu->clks[i]) {
|
||||
devm_clk_put(&gmu->pdev->dev, gmu->clks[i]);
|
||||
gmu->clks[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
if (gmu->gx_gdsc) {
|
||||
devm_regulator_put(gmu->gx_gdsc);
|
||||
gmu->gx_gdsc = NULL;
|
||||
|
|
|
|||
|
|
@ -158,7 +158,6 @@ struct icc_path;
|
|||
* @dump_mem: pointer to GMU debug dump memory
|
||||
* @gmu_log: gmu event log memory
|
||||
* @hfi: HFI controller
|
||||
* @gpu_freqs: GPU frequency table with lowest freq at index 0
|
||||
* @num_gpupwrlevels: number GPU frequencies in GPU freq table
|
||||
* @num_bwlevel: number of GPU BW levels
|
||||
* @num_cnocbwlevel: number CNOC BW levels
|
||||
|
|
@ -194,14 +193,24 @@ struct gmu_device {
|
|||
struct gmu_memdesc *dump_mem;
|
||||
struct gmu_memdesc *gmu_log;
|
||||
struct kgsl_hfi hfi;
|
||||
unsigned int gpu_freqs[MAX_GX_LEVELS];
|
||||
/** @pwrlevels: Array of GMU power levels */
|
||||
struct {
|
||||
/** @freq: GPU frequency */
|
||||
unsigned long freq;
|
||||
/** @level: Voltage level */
|
||||
u32 level;
|
||||
} pwrlevels[MAX_GX_LEVELS];
|
||||
unsigned int num_gpupwrlevels;
|
||||
unsigned int num_bwlevels;
|
||||
unsigned int num_cnocbwlevels;
|
||||
struct rpmh_votes_t rpmh_votes;
|
||||
struct regulator *cx_gdsc;
|
||||
struct regulator *gx_gdsc;
|
||||
struct clk *clks[MAX_GMU_CLKS];
|
||||
struct clk_bulk_data *clks;
|
||||
/** @num_clks: Number of entries in the @clks array */
|
||||
int num_clks;
|
||||
/** @gmu_clk: Pointer to the core GMU clock */
|
||||
struct clk *gmu_clk;
|
||||
enum gmu_load_mode load_mode;
|
||||
unsigned int wakeup_pwrlevel;
|
||||
unsigned int pcl;
|
||||
|
|
|
|||
|
|
@ -21,8 +21,6 @@
|
|||
#error "CNOC levels cannot exceed GX levels"
|
||||
#endif
|
||||
|
||||
#define MAX_GMU_CLKS 6
|
||||
|
||||
/*
|
||||
* These are the different ways the GMU can boot. GMU_WARM_BOOT is waking up
|
||||
* from slumber. GMU_COLD_BOOT is booting for the first time. GMU_RESET
|
||||
|
|
|
|||
|
|
@ -437,7 +437,7 @@ static int hfi_send_dcvstbl_v1(struct gmu_device *gmu)
|
|||
for (i = 0; i < gmu->num_gpupwrlevels; i++) {
|
||||
cmd.gx_votes[i].vote = gmu->rpmh_votes.gx_votes[i];
|
||||
/* Divide by 1000 to convert to kHz */
|
||||
cmd.gx_votes[i].freq = gmu->gpu_freqs[i] / 1000;
|
||||
cmd.gx_votes[i].freq = gmu->pwrlevels[i].freq / 1000;
|
||||
}
|
||||
|
||||
cmd.cx_votes[0].vote = gmu->rpmh_votes.cx_votes[0];
|
||||
|
|
@ -483,7 +483,7 @@ static int hfi_send_dcvstbl(struct gmu_device *gmu)
|
|||
/* Hardcode this to the max threshold since it is not used */
|
||||
cmd.gx_votes[i].acd = 0xFFFFFFFF;
|
||||
/* Divide by 1000 to convert to kHz */
|
||||
cmd.gx_votes[i].freq = gmu->gpu_freqs[i] / 1000;
|
||||
cmd.gx_votes[i].freq = gmu->pwrlevels[i].freq / 1000;
|
||||
}
|
||||
|
||||
cmd.cx_votes[0].vote = gmu->rpmh_votes.cx_votes[0];
|
||||
|
|
|
|||
|
|
@ -100,7 +100,7 @@ _kgsl_pool_add_page(struct kgsl_page_pool *pool, struct page *p)
|
|||
list_add_tail(&p->lru, &pool->page_list);
|
||||
pool->page_count++;
|
||||
spin_unlock(&pool->list_lock);
|
||||
mod_node_page_state(page_pgdat(p), NR_INDIRECTLY_RECLAIMABLE_BYTES,
|
||||
mod_node_page_state(page_pgdat(p), NR_KERNEL_MISC_RECLAIMABLE,
|
||||
(PAGE_SIZE << pool->pool_order));
|
||||
}
|
||||
|
||||
|
|
@ -117,7 +117,7 @@ _kgsl_pool_get_page(struct kgsl_page_pool *pool)
|
|||
list_del(&p->lru);
|
||||
}
|
||||
spin_unlock(&pool->list_lock);
|
||||
mod_node_page_state(page_pgdat(p), NR_INDIRECTLY_RECLAIMABLE_BYTES,
|
||||
mod_node_page_state(page_pgdat(p), NR_KERNEL_MISC_RECLAIMABLE,
|
||||
-(PAGE_SIZE << pool->pool_order));
|
||||
return p;
|
||||
}
|
||||
|
|
@ -256,20 +256,12 @@ void kgsl_pool_free_pages(struct page **pages, unsigned int pcount)
|
|||
if (!pages)
|
||||
return;
|
||||
|
||||
if (WARN(!kern_addr_valid((unsigned long)pages),
|
||||
"Address of pages=%pK is not valid\n", pages))
|
||||
return;
|
||||
|
||||
for (i = 0; i < pcount;) {
|
||||
/*
|
||||
* Free each page or compound page group individually.
|
||||
*/
|
||||
struct page *p = pages[i];
|
||||
|
||||
if (WARN(!kern_addr_valid((unsigned long)p),
|
||||
"Address of page=%pK is not valid\n", p))
|
||||
return;
|
||||
|
||||
i += 1 << compound_order(p);
|
||||
kgsl_pool_free_page(p);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1584,43 +1584,6 @@ static int kgsl_pwrctrl_clk_set_rate(struct clk *grp_clk, unsigned int freq,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static bool _gpu_freq_supported(struct kgsl_pwrctrl *pwr, unsigned int freq)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = pwr->num_pwrlevels - 1; i >= 0; i--) {
|
||||
if (pwr->pwrlevels[i].gpu_freq == freq)
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void kgsl_pwrctrl_disable_unused_opp(struct kgsl_device *device,
|
||||
struct device *dev)
|
||||
{
|
||||
struct dev_pm_opp *opp;
|
||||
unsigned long freq = 0;
|
||||
int ret;
|
||||
|
||||
ret = dev_pm_opp_get_opp_count(dev);
|
||||
/* Return early, If no OPP table or OPP count is zero */
|
||||
if (ret <= 0)
|
||||
return;
|
||||
|
||||
while (1) {
|
||||
opp = dev_pm_opp_find_freq_ceil(dev, &freq);
|
||||
if (IS_ERR(opp))
|
||||
break;
|
||||
|
||||
if (!_gpu_freq_supported(&device->pwrctrl, freq))
|
||||
dev_pm_opp_disable(dev, freq);
|
||||
|
||||
dev_pm_opp_put(opp);
|
||||
freq++;
|
||||
}
|
||||
}
|
||||
|
||||
static u32 *kgsl_bus_get_table(struct platform_device *pdev, int *count)
|
||||
{
|
||||
u32 *levels;
|
||||
|
|
@ -1702,8 +1665,6 @@ int kgsl_pwrctrl_init(struct kgsl_device *device)
|
|||
pwr->pwrlevels[i].gpu_freq = freq;
|
||||
}
|
||||
|
||||
kgsl_pwrctrl_disable_unused_opp(device, &pdev->dev);
|
||||
|
||||
kgsl_clk_set_rate(device, pwr->num_pwrlevels - 1);
|
||||
|
||||
freq = clk_round_rate(pwr->grp_clks[6], KGSL_RBBMTIMER_CLK_FREQ);
|
||||
|
|
|
|||
|
|
@ -69,6 +69,8 @@ struct kgsl_pwrlevel {
|
|||
unsigned int bus_min;
|
||||
unsigned int bus_max;
|
||||
unsigned int acd_level;
|
||||
/** @voltage_level: Voltage level used by the GMU to vote RPMh */
|
||||
u32 voltage_level;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -196,7 +198,5 @@ void kgsl_pwrctrl_busy_time(struct kgsl_device *device, u64 time, u64 busy);
|
|||
void kgsl_pwrctrl_set_constraint(struct kgsl_device *device,
|
||||
struct kgsl_pwr_constraint *pwrc, uint32_t id);
|
||||
int kgsl_pwrctrl_set_default_gpu_pwrlevel(struct kgsl_device *device);
|
||||
void kgsl_pwrctrl_disable_unused_opp(struct kgsl_device *device,
|
||||
struct device *dev);
|
||||
|
||||
#endif /* __KGSL_PWRCTRL_H */
|
||||
|
|
|
|||
|
|
@ -357,32 +357,15 @@ kgsl_sharedmem_init_sysfs(void)
|
|||
return sysfs_create_files(&kgsl_driver.virtdev.kobj, drv_attr_list);
|
||||
}
|
||||
|
||||
static int kgsl_paged_vmfault(struct kgsl_memdesc *memdesc,
|
||||
static vm_fault_t kgsl_paged_vmfault(struct kgsl_memdesc *memdesc,
|
||||
struct vm_area_struct *vma,
|
||||
struct vm_fault *vmf)
|
||||
{
|
||||
int pgoff;
|
||||
unsigned int offset;
|
||||
|
||||
offset = vmf->address - vma->vm_start;
|
||||
pgoff = (vmf->address - vma->vm_start) >> PAGE_SHIFT;
|
||||
|
||||
if (offset >= memdesc->size)
|
||||
return VM_FAULT_SIGBUS;
|
||||
|
||||
pgoff = offset >> PAGE_SHIFT;
|
||||
|
||||
if (pgoff < memdesc->page_count) {
|
||||
struct page *page = memdesc->pages[pgoff];
|
||||
|
||||
get_page(page);
|
||||
vmf->page = page;
|
||||
|
||||
memdesc->mapsize += PAGE_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
return VM_FAULT_SIGBUS;
|
||||
return vmf_insert_page(vma, vmf->address, memdesc->pages[pgoff]);
|
||||
}
|
||||
|
||||
static void kgsl_paged_unmap_kernel(struct kgsl_memdesc *memdesc)
|
||||
|
|
@ -495,27 +478,17 @@ static int kgsl_paged_map_kernel(struct kgsl_memdesc *memdesc)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int kgsl_contiguous_vmfault(struct kgsl_memdesc *memdesc,
|
||||
static vm_fault_t kgsl_contiguous_vmfault(struct kgsl_memdesc *memdesc,
|
||||
struct vm_area_struct *vma,
|
||||
struct vm_fault *vmf)
|
||||
{
|
||||
unsigned long offset, pfn;
|
||||
int ret;
|
||||
|
||||
offset = ((unsigned long) vmf->address - vma->vm_start) >>
|
||||
PAGE_SHIFT;
|
||||
|
||||
pfn = (memdesc->physaddr >> PAGE_SHIFT) + offset;
|
||||
ret = vm_insert_pfn(vma, (unsigned long) vmf->address, pfn);
|
||||
|
||||
if (ret == -ENOMEM || ret == -EAGAIN)
|
||||
return VM_FAULT_OOM;
|
||||
else if (ret == -EFAULT)
|
||||
return VM_FAULT_SIGBUS;
|
||||
|
||||
memdesc->mapsize += PAGE_SIZE;
|
||||
|
||||
return VM_FAULT_NOPAGE;
|
||||
return vmf_insert_pfn(vma, vmf->address, pfn);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
|
|
@ -1054,7 +1027,7 @@ static struct kgsl_memdesc_ops kgsl_secure_pool_ops = {
|
|||
|
||||
static struct kgsl_memdesc_ops kgsl_pool_ops = {
|
||||
.free = kgsl_free_pool_pages,
|
||||
.vmflags = VM_DONTDUMP | VM_DONTEXPAND | VM_DONTCOPY,
|
||||
.vmflags = VM_DONTDUMP | VM_DONTEXPAND | VM_DONTCOPY | VM_MIXEDMAP,
|
||||
.vmfault = kgsl_paged_vmfault,
|
||||
.map_kernel = kgsl_paged_map_kernel,
|
||||
.unmap_kernel = kgsl_paged_unmap_kernel,
|
||||
|
|
|
|||
|
|
@ -3,9 +3,13 @@
|
|||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/ktime.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include "kgsl_util.h"
|
||||
|
||||
|
|
@ -25,3 +29,15 @@ bool kgsl_regulator_disable_wait(struct regulator *reg, u32 timeout)
|
|||
usleep_range((100 >> 2) + 1, 100);
|
||||
}
|
||||
}
|
||||
|
||||
struct clk *kgsl_of_clk_by_name(struct clk_bulk_data *clks, int count,
|
||||
const char *id)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; clks && i < count; i++)
|
||||
if (!strcmp(clks[i].id, id))
|
||||
return clks[i].clk;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#define _KGSL_UTIL_H_
|
||||
|
||||
struct regulator;
|
||||
struct clk_bulk_data;
|
||||
|
||||
/**
|
||||
* kgsl_regulator_disable_wait - Disable a regulator and wait for it
|
||||
|
|
@ -20,4 +21,15 @@ struct regulator;
|
|||
*/
|
||||
bool kgsl_regulator_disable_wait(struct regulator *reg, u32 timeout);
|
||||
|
||||
/**
|
||||
* kgsl_of_clk_by_name - Return a clock device for a given name
|
||||
* @clks: Pointer to an array of bulk clk data
|
||||
* @count: Number of entries in the array
|
||||
* @id: Name of the clock to search for
|
||||
*
|
||||
* Returns: A pointer to the clock device for the given name or NULL if not
|
||||
* found
|
||||
*/
|
||||
struct clk *kgsl_of_clk_by_name(struct clk_bulk_data *clks, int count,
|
||||
const char *id);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue