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ARM: Device-tree updates for 4.15

Browse source 
We add device tree files for a couple of additional SoCs in various areas:
 
 Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for networking,
 Amlogic A113D for audio, and Renesas R-Car V3M for automotive.
 
 As usual, lots of new boards get added based on those and other SoCs:
 
  - Actions S500 based CubieBoard6 single-board computer
 
  - Amlogic Meson-AXG A113D based development board
  - Amlogic S912 based Khadas VIM2 single-board computer
  - Amlogic S912 based Tronsmart Vega S96 set-top-box
 
  - Allwinner H5 based NanoPi NEO Plus2 single-board computer
  - Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers
  - Allwinner A83T based TBS A711 Tablet
 
  - Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8
  - Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500
      wireless access points and routers
 
  - NXP i.MX51 based Zodiac Inflight Innovations RDU1 board
  - NXP i.MX53 based GE Healthcare PPD biometric monitor
  - NXP i.MX6 based Pistachio single-board computer
  - NXP i.MX6 based Vining-2000 automotive diagnostic interface
  - NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants
 
  - Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone
  - Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet
 
  - Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA
 
  - Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board
  - Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards
  - Renasas r8a7745 based iWave G22D-SODIMM SoM
 
  - Rockchip rk3288 based Amarula Vyasa single-board computer
 
  - Samsung Exynos5800 based Odroid HC1 single-board computer
 
 For existing SoC support, there was a lot of ongoing work, as usual
 most of that concentrated on the Renesas, Rockchip, OMAP, i.MX, Amlogic
 and Allwinner platforms, but others were also active.
 
 Rob Herring and many others worked on reducing the number of issues that
 the latest version of 'dtc' now warns about. Unfortunately there is still
 a lot left to do.
 
 A rework of the ARM foundation model introduced several new files
 for common variations of the model.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM device-tree updates from Arnd Bergmann:
 "We add device tree files for a couple of additional SoCs in various
  areas:

  Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for
  networking, Amlogic A113D for audio, and Renesas R-Car V3M for
  automotive.

  As usual, lots of new boards get added based on those and other SoCs:

   - Actions S500 based CubieBoard6 single-board computer

   - Amlogic Meson-AXG A113D based development board
   - Amlogic S912 based Khadas VIM2 single-board computer
   - Amlogic S912 based Tronsmart Vega S96 set-top-box

   - Allwinner H5 based NanoPi NEO Plus2 single-board computer
   - Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers
   - Allwinner A83T based TBS A711 Tablet

   - Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8
   - Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500
     wireless access points and routers

   - NXP i.MX51 based Zodiac Inflight Innovations RDU1 board
   - NXP i.MX53 based GE Healthcare PPD biometric monitor
   - NXP i.MX6 based Pistachio single-board computer
   - NXP i.MX6 based Vining-2000 automotive diagnostic interface
   - NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants

   - Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone
   - Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet

   - Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA

   - Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board
   - Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards
   - Renasas r8a7745 based iWave G22D-SODIMM SoM

   - Rockchip rk3288 based Amarula Vyasa single-board computer

   - Samsung Exynos5800 based Odroid HC1 single-board computer

  For existing SoC support, there was a lot of ongoing work, as usual
  most of that concentrated on the Renesas, Rockchip, OMAP, i.MX,
  Amlogic and Allwinner platforms, but others were also active.

  Rob Herring and many others worked on reducing the number of issues
  that the latest version of 'dtc' now warns about. Unfortunately there
  is still a lot left to do.

  A rework of the ARM foundation model introduced several new files for
  common variations of the model"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (599 commits)
  arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3
  dt-bindings: bus: Add documentation for the Technologic Systems NBUS
  arm64: dts: actions: s900-bubblegum-96: Add fake uart5 clock
  ARM: dts: owl-s500: Add CubieBoard6
  dt-bindings: arm: actions: Add CubieBoard6
  ARM: dts: owl-s500-guitar-bb-rev-b: Add fake uart3 clock
  ARM: dts: owl-s500: Set power domains for CPU2 and CPU3
  arm: dts: mt7623: remove unused compatible string for pio node
  arm: dts: mt7623: update usb related nodes
  arm: dts: mt7623: update crypto node
  ARM: dts: sun8i: a711: Enable USB OTG
  ARM: dts: sun8i: a711: Add regulator support
  ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1
  ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1
  ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file
  ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes
  ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes
  ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes
  ARM: dts: sunxi: Add dtsi for AXP81x PMIC
  arm64: dts: allwinner: H5: Restore EMAC changes
  ...
This commit is contained in:
Linus Torvalds 2017-11-16 15:48:26 -08:00
commit 527d147074
608 changed files with 28063 additions and 15882 deletions
Download patch file Download diff file Expand all files Collapse all files

7
arch/arm64/Kconfig.platforms
View file

@ -104,6 +104,7 @@ config ARCH_MESON
select PINCTRL_MESON
select COMMON_CLK_AMLOGIC
select COMMON_CLK_GXBB
select MESON_IRQ_GPIO
help
This enables support for the Amlogic S905 SoCs.
@ -187,6 +188,12 @@ config ARCH_R8A7796
help
This enables support for the Renesas R-Car M3-W SoC.
config ARCH_R8A77970
bool "Renesas R-Car V3M SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car V3M SoC.
config ARCH_R8A77995
bool "Renesas R-Car D3 SoC Platform"
depends on ARCH_RENESAS

7
arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
View file

@ -24,6 +24,12 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
uart5_clk: uart5-clk {
compatible = "fixed-clock";
clock-frequency = <921600>;
#clock-cells = <0>;
};
};
&timer {
@ -32,4 +38,5 @@
&uart5 {
status = "okay";
clocks = <&uart5_clk>;
};

1
arch/arm64/boot/dts/allwinner/Makefile
View file

@ -9,3 +9,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb

16
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
View file

@ -51,6 +51,7 @@
compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@ -69,6 +70,14 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@ -79,6 +88,13 @@
bias-pull-up;
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;

15
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
View file

@ -48,3 +48,18 @@
/* TODO: Camera, touchscreen, etc. */
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
status = "okay";
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};

17
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
View file

@ -51,6 +51,7 @@
compatible = "pine64,pine64", "allwinner,sun50i-a64";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@ -71,6 +72,15 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rmii_pins>;
phy-mode = "rmii";
phy-handle = <&ext_rmii_phy1>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@ -81,6 +91,13 @@
bias-pull-up;
};
&mdio {
ext_rmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;

16
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
View file

@ -53,6 +53,7 @@
"allwinner,sun50i-a64";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -76,6 +77,21 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
status = "okay";
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;

97
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View file

@ -136,6 +136,17 @@
reg = <0x01c00000 0x1000>;
};
dma: dma-controller@1c02000 {
compatible = "allwinner,sun50i-a64-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DMA>;
dma-channels = <8>;
dma-requests = <27>;
resets = <&ccu RST_BUS_DMA>;
#dma-cells = <1>;
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
@ -178,7 +189,7 @@
#size-cells = <0>;
};
usb_otg: usb@01c19000 {
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
@ -191,7 +202,7 @@
status = "disabled";
};
usbphy: phy@01c19400 {
usbphy: phy@1c19400 {
compatible = "allwinner,sun50i-a64-usb-phy";
reg = <0x01c19400 0x14>,
<0x01c1a800 0x4>,
@ -211,7 +222,7 @@
#phy-cells = <1>;
};
ehci0: usb@01c1a000 {
ehci0: usb@1c1a000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
@ -223,7 +234,7 @@
status = "disabled";
};
ohci0: usb@01c1a400 {
ohci0: usb@1c1a400 {
compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
@ -233,7 +244,7 @@
status = "disabled";
};
ehci1: usb@01c1b000 {
ehci1: usb@1c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
@ -247,7 +258,7 @@
status = "disabled";
};
ohci1: usb@01c1b400 {
ohci1: usb@1c1b400 {
compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
reg = <0x01c1b400 0x100>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@ -259,7 +270,7 @@
status = "disabled";
};
ccu: clock@01c20000 {
ccu: clock@1c20000 {
compatible = "allwinner,sun50i-a64-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
@ -325,7 +336,17 @@
drive-strength = <40>;
};
uart0_pins_a: uart0@0 {
spi0_pins: spi0 {
pins = "PC0", "PC1", "PC2", "PC3";
function = "spi0";
};
spi1_pins: spi1 {
pins = "PD0", "PD1", "PD2", "PD3";
function = "spi1";
};
uart0_pins_a: uart0 {
pins = "PB8", "PB9";
function = "uart0";
};
@ -449,6 +470,62 @@
#size-cells = <0>;
};
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
dmas = <&dma 23>, <&dma 23>;
dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
resets = <&ccu RST_BUS_SPI0>;
status = "disabled";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@1c69000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c69000 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
clock-names = "ahb", "mod";
dmas = <&dma 24>, <&dma 24>;
dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
resets = <&ccu RST_BUS_SPI1>;
status = "disabled";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
emac: ethernet@1c30000 {
compatible = "allwinner,sun50i-a64-emac";
syscon = <&syscon>;
reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
@ -486,7 +563,7 @@
#reset-cells = <1>;
};
r_pio: pinctrl@01f02c00 {
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun50i-a64-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@ -497,7 +574,7 @@
interrupt-controller;
#interrupt-cells = <3>;
r_rsb_pins: rsb@0 {
r_rsb_pins: rsb {
pins = "PL0", "PL1";
function = "s_rsb";
};

193
arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts Normal file
View file

@ -0,0 +1,193 @@
/*
* Copyright (C) 2017 Antony Antony <antony@phenome.org>
* Copyright (C) 2016 ARM Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-h5.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "FriendlyARM NanoPi NEO Plus2";
compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
pwr {
label = "nanopi:green:pwr";
gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
status {
label = "nanopi:red:status";
gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
};
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <100000>;
enable-active-high;
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_cpux: gpio-regulator {
compatible = "regulator-gpio";
pinctrl-names = "default";
regulator-name = "vdd-cpux";
regulator-type = "voltage";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <50>; /* 4ms */
gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
gpios-states = <0x1>;
states = <1100000 0x0
1300000 0x1>;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
post-power-on-delay-ms = <200>;
};
};
&codec {
allwinner,audio-routing =
"Line Out", "LINEOUT",
"MIC1", "Mic",
"Mic", "MBIAS";
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci3 {
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_pins>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci3 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usb_otg {
dr_mode = "host";
status = "okay";
};
&usbphy {
/* USB Type-A ports' VBUS is always on */
status = "okay";
};

17
arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
View file

@ -50,6 +50,7 @@
compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -108,6 +109,22 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;

17
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
View file

@ -59,6 +59,7 @@
};
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -136,6 +137,22 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;

17
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
View file

@ -54,6 +54,7 @@
compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -143,6 +144,22 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;

38
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View file

@ -15,6 +15,8 @@
*/
/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "altr,socfpga-stratix10";
@ -75,10 +77,10 @@
compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0xfffc1000 0x1000>,
<0x0 0xfffc2000 0x2000>,
<0x0 0xfffc4000 0x2000>,
<0x0 0xfffc6000 0x2000>;
reg = <0x0 0xfffc1000 0x0 0x1000>,
<0x0 0xfffc2000 0x0 0x2000>,
<0x0 0xfffc4000 0x0 0x2000>,
<0x0 0xfffc6000 0x0 0x2000>;
};
soc {
@ -100,6 +102,8 @@
interrupts = <0 90 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
@ -109,6 +113,8 @@
interrupts = <0 91 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
@ -118,6 +124,8 @@
interrupts = <0 92 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC2_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
@ -126,6 +134,7 @@
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc03200 0x100>;
resets = <&rst GPIO0_RESET>;
status = "disabled";
porta: gpio-controller@0 {
@ -145,6 +154,7 @@
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc03300 0x100>;
resets = <&rst GPIO1_RESET>;
status = "disabled";
portb: gpio-controller@0 {
@ -155,7 +165,7 @@
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 110 4>;
interrupts = <0 111 4>;
};
};
@ -165,6 +175,7 @@
compatible = "snps,designware-i2c";
reg = <0xffc02800 0x100>;
interrupts = <0 103 4>;
resets = <&rst I2C0_RESET>;
status = "disabled";
};
@ -174,6 +185,7 @@
compatible = "snps,designware-i2c";
reg = <0xffc02900 0x100>;
interrupts = <0 104 4>;
resets = <&rst I2C1_RESET>;
status = "disabled";
};
@ -183,6 +195,7 @@
compatible = "snps,designware-i2c";
reg = <0xffc02a00 0x100>;
interrupts = <0 105 4>;
resets = <&rst I2C2_RESET>;
status = "disabled";
};
@ -192,6 +205,7 @@
compatible = "snps,designware-i2c";
reg = <0xffc02b00 0x100>;
interrupts = <0 106 4>;
resets = <&rst I2C3_RESET>;
status = "disabled";
};
@ -201,6 +215,7 @@
compatible = "snps,designware-i2c";
reg = <0xffc02c00 0x100>;
interrupts = <0 107 4>;
resets = <&rst I2C4_RESET>;
status = "disabled";
};
@ -211,6 +226,8 @@
reg = <0xff808000 0x1000>;
interrupts = <0 96 4>;
fifo-depth = <0x400>;
resets = <&rst SDMMC_RESET>;
reset-names = "reset";
status = "disabled";
};
@ -223,6 +240,7 @@
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd11000 0x1000>;
altr,modrst-offset = <0x20>;
};
spi0: spi@ffda4000 {
@ -291,6 +309,7 @@
interrupts = <0 108 4>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART0_RESET>;
status = "disabled";
};
@ -300,6 +319,7 @@
interrupts = <0 109 4>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART1_RESET>;
status = "disabled";
};
@ -315,6 +335,8 @@
interrupts = <0 93 4>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
resets = <&rst USB0_RESET>;
reset-names = "dwc2";
status = "disabled";
};
@ -324,6 +346,8 @@
interrupts = <0 94 4>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
resets = <&rst USB1_RESET>;
reset-names = "dwc2";
status = "disabled";
};
@ -331,6 +355,7 @@
compatible = "snps,dw-wdt";
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = <&rst WATCHDOG0_RESET>;
status = "disabled";
};
@ -338,6 +363,7 @@
compatible = "snps,dw-wdt";
reg = <0xffd00300 0x100>;
interrupts = <0 118 4>;
resets = <&rst WATCHDOG1_RESET>;
status = "disabled";
};
@ -345,6 +371,7 @@
compatible = "snps,dw-wdt";
reg = <0xffd00400 0x100>;
interrupts = <0 125 4>;
resets = <&rst WATCHDOG2_RESET>;
status = "disabled";
};
@ -352,6 +379,7 @@
compatible = "snps,dw-wdt";
reg = <0xffd00500 0x100>;
interrupts = <0 126 4>;
resets = <&rst WATCHDOG3_RESET>;
status = "disabled";
};
};

62
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
View file

@ -14,7 +14,7 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
/include/ "socfpga_stratix10.dtsi"
#include "socfpga_stratix10.dtsi"
/ {
model = "SoCFPGA Stratix 10 SoCDK";
@ -27,6 +27,24 @@
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
hps0 {
label = "hps_led0";
gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
};
hps1 {
label = "hps_led1";
gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
};
hps2 {
label = "hps_led2";
gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
};
};
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
@ -34,6 +52,48 @@
};
};
&gpio1 {
status = "okay";
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&phy0>;
max-frame-size = <3800>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <4>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <1860>; /* 960ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
&mmc {
status = "okay";
num-slots = <1>;
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
};
&uart0 {
status = "okay";
};

3
arch/arm64/boot/dts/amlogic/Makefile
View file

@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
@ -16,7 +17,9 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb

22
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts Normal file
View file

@ -0,0 +1,22 @@
/*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "meson-axg.dtsi"
/ {
compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
model = "Amlogic Meson AXG S400 Development Board";
aliases {
serial0 = &uart_AO;
};
};
&uart_AO {
status = "okay";
};

204
arch/arm64/boot/dts/amlogic/meson-axg.dtsi Normal file
View file

@ -0,0 +1,204 @@
/*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "amlogic,meson-axg";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 16 MiB reserved for Hardware ROM Firmware */
hwrom_reserved: hwrom@0 {
reg = <0x0 0x0 0x0 0x1000000>;
no-map;
};
/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@5000000 {
reg = <0x0 0x05000000 0x0 0x300000>;
no-map;
};
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
cbus: cbus@ffd00000 {
compatible = "simple-bus";
reg = <0x0 0xffd00000 0x0 0x25000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
reg = <0x0 0x24000 0x0 0x14>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
uart_B: serial@23000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
reg = <0x0 0x23000 0x0 0x14>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
};
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
<0x0 0xffc02000 0 0x2000>,
<0x0 0xffc04000 0 0x2000>,
<0x0 0xffc06000 0 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
#address-cells = <0>;
};
mailbox: mailbox@ff63dc00 {
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
reg = <0 0xff63dc00 0 0x400>;
interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
#mbox-cells = <1>;
};
sram: sram@fffc0000 {
compatible = "amlogic,meson-axg-sram", "mmio-sram";
reg = <0x0 0xfffc0000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0xfffc0000 0x20000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "amlogic,meson-axg-scp-shmem";
reg = <0x13000 0x400>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "amlogic,meson-axg-scp-shmem";
reg = <0x13400 0x400>;
};
};
aobus: aobus@ff800000 {
compatible = "simple-bus";
reg = <0x0 0xff800000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
reg = <0x0 0x3000 0x0 0x18>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&xtal>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
uart_AO_B: serial@4000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
reg = <0x0 0x4000 0x0 0x18>;
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&xtal>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
};
};
};

2
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
View file

@ -213,7 +213,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";

22
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View file

@ -218,6 +218,15 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
gpio_intc: interrupt-controller@9880 {
compatible = "amlogic,meson-gpio-intc";
reg = <0x0 0x9880 0x0 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
status = "disabled";
};
reset: reset-controller@4404 {
compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
reg = <0x0 0x04404 0x0 0x20>;
@ -225,18 +234,16 @@
};
uart_A: serial@84c0 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x84c0 0x0 0x14>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
uart_B: serial@84dc {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x84dc 0x0 0x14>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
@ -279,10 +286,9 @@
};
uart_C: serial@8700 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x8700 0x0 0x14>;
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
@ -391,14 +397,14 @@
};
uart_AO: serial@4c0 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
reg = <0x0 0x004c0 0x0 0x14>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
uart_AO_B: serial@4e0 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
reg = <0x0 0x004e0 0x0 0x14>;
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
status = "disabled";

14
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
View file

@ -168,6 +168,8 @@
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
interrupt-parent = <&gpio_intc>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};
};
@ -183,7 +185,9 @@
"VCCK En", "CON1 Header Pin31",
"I2S Header Pin6", "IR In", "I2S Header Pin7",
"I2S Header Pin3", "I2S Header Pin4",
"I2S Header Pin5", "HDMI CEC", "SYS LED";
"I2S Header Pin5", "HDMI CEC", "SYS LED",
/* GPIO_TEST_N */
"";
};
&pinctrl_periphs {
@ -229,11 +233,9 @@
"Bluetooth UART TX", "Bluetooth UART RX",
"Bluetooth UART CTS", "Bluetooth UART RTS",
"", "", "", "WIFI 32K", "Bluetooth Enable",
"Bluetooth WAKE HOST",
"Bluetooth WAKE HOST", "",
/* Bank GPIOCLK */
"", "CON1 Header Pin35", "", "",
/* GPIO_TEST_N */
"";
"", "CON1 Header Pin35", "", "";
};
&pwm_ef {
@ -302,7 +304,7 @@
/* eMMC */
&sd_emmc_c {
status = "disabled";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";

31
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
View file

@ -88,6 +88,18 @@
};
};
usb_pwr: regulator-usb-pwrs {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vddio_card: gpio-regulator {
compatible = "regulator-gpio";
@ -272,7 +284,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
@ -294,3 +306,20 @@
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_pwr>;
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

15
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
View file

@ -157,6 +157,8 @@
eth_phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio_intc>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
eee-broken-1000t;
};
};
@ -194,7 +196,9 @@
"USB HUB nRESET", "USB OTG Power En",
"J7 Header Pin2", "IR In", "J7 Header Pin4",
"J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7",
"HDMI CEC", "SYS LED";
"HDMI CEC", "SYS LED",
/* GPIO_TEST_N */
"";
};
&pinctrl_periphs {
@ -233,11 +237,9 @@
"J2 Header Pin12", "J2 Header Pin13",
"J2 Header Pin8", "J2 Header Pin10",
"", "", "", "", "",
"J2 Header Pin11", "", "J2 Header Pin7",
"J2 Header Pin11", "", "J2 Header Pin7", "",
/* Bank GPIOCLK */
"", "", "", "",
/* GPIO_TEST_N */
"";
"", "", "", "";
};
&saradc {
@ -271,7 +273,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
@ -301,6 +303,7 @@
&usb1_phy {
status = "okay";
phy-supply = <&usb_otg_pwr>;
};
&usb0 {

2
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
View file

@ -117,6 +117,8 @@
eth_phy0: ethernet-phy@3 {
/* Micrel KSZ9031 (0x00221620) */
reg = <3>;
interrupt-parent = <&gpio_intc>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};
};

2
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
View file

@ -242,7 +242,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";

2
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
View file

@ -199,7 +199,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";

18
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View file

@ -323,6 +323,12 @@
clock-names = "stmmaceth", "clkin0", "clkin1";
};
&gpio_intc {
compatible = "amlogic,meson-gpio-intc",
"amlogic,meson-gxbb-gpio-intc";
status = "okay";
};
&hdmi_tx {
compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
@ -379,15 +385,21 @@
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 14 120>;
gpio-ranges = <&pinctrl_periphs 0 0 119>;
};
emmc_pins: emmc {
mux {
groups = "emmc_nand_d07",
"emmc_cmd",
"emmc_clk",
"emmc_ds";
"emmc_clk";
function = "emmc";
};
};
emmc_ds_pins: emmc-ds {
mux {
groups = "emmc_ds";
function = "emmc";
};
};

2
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
View file

@ -128,6 +128,8 @@
compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <1000>;
interrupt-parent = <&gpio_intc>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};

2
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
View file

@ -141,7 +141,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";

8
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
View file

@ -122,7 +122,9 @@
"J9 Header Pin33",
"IR In",
"HDMI CEC",
"SYS LED";
"SYS LED",
/* GPIO_TEST_N */
"";
};
&pinctrl_periphs {
@ -163,9 +165,7 @@
"WIFI 32K", "Bluetooth Enable",
"Bluetooth WAKE HOST",
/* Bank GPIOCLK */
"", "J9 Header Pin39",
/* GPIO_TEST_N */
"";
"", "J9 Header Pin39";
};
&pwm_AO_ab {

27
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
View file

@ -96,6 +96,13 @@
regulator-settling-time-down-us = <50000>;
};
vddio_ao18: regulator-vddio_ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
@ -121,6 +128,11 @@
status = "okay";
};
&internal_phy {
pinctrl-0 = <&eth_link_led_pins>, <&eth_act_led_pins>;
pinctrl-names = "default";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
@ -149,7 +161,9 @@
"7J1 Header Pin12",
"IR In",
"9J3 Switch HDMI CEC/7J1 Header Pin11",
"7J1 Header Pin13";
"7J1 Header Pin13",
/* GPIO_TEST_N */
"7J1 Header Pin15";
};
&pinctrl_periphs {
@ -191,9 +205,12 @@
"7J1 Header Pin32", "7J1 Header Pin29",
"7J1 Header Pin31",
/* Bank GPIOCLK */
"7J1 Header Pin7", "",
/* GPIO_TEST_N */
"7J1 Header Pin15";
"7J1 Header Pin7", "";
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
};
/* SD card */
@ -221,7 +238,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";

2
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
View file

@ -229,7 +229,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";

2
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
View file

@ -135,7 +135,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";

26
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View file

@ -49,6 +49,14 @@
/ {
compatible = "amlogic,meson-gxl";
reserved-memory {
/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved_alt: secmon@5000000 {
reg = <0x0 0x05000000 0x0 0x300000>;
no-map;
};
};
};
&ethmac {
@ -217,6 +225,12 @@
compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
};
&gpio_intc {
compatible = "amlogic,meson-gpio-intc",
"amlogic,meson-gxl-gpio-intc";
status = "okay";
};
&hdmi_tx {
compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
@ -268,15 +282,21 @@
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 10 101>;
gpio-ranges = <&pinctrl_periphs 0 0 100>;
};
emmc_pins: emmc {
mux {
groups = "emmc_nand_d07",
"emmc_cmd",
"emmc_clk",
"emmc_ds";
"emmc_clk";
function = "emmc";
};
};
emmc_ds_pins: emmc-ds {
mux {
groups = "emmc_ds";
function = "emmc";
};
};

400
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts Normal file
View file

@ -0,0 +1,400 @@
/*
* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
* Copyright (c) 2017 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
#include "meson-gxm.dtsi"
/ {
compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
model = "Khadas VIM2";
aliases {
serial0 = &uart_AO;
serial1 = &uart_A;
serial2 = &uart_AO_B;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1710000>;
button-function {
label = "Function";
linux,code = <KEY_FN>;
press-threshold-microvolt = <10000>;
};
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
gpio_fan: gpio-fan {
compatible = "gpio-fan";
gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH
&gpio GPIODV_15 GPIO_ACTIVE_HIGH>;
/* Dummy RPM values since fan is optional */
gpio-fan,speed-map = <0 0
1 1
2 2
3 3>;
cooling-min-level = <0>;
cooling-max-level = <3>;
#cooling-cells = <2>;
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
pwmleds {
compatible = "pwm-leds";
power {
label = "vim:red:power";
pwms = <&pwm_AO_ab 1 7812500 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&scpi_sensors 0>;
trips {
cpu_alert0: cpu-alert0 {
temperature = <70000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "active";
};
cpu_alert1: cpu-alert1 {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>;
};
map2 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map3 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vddio_ao18: regulator-vddio_ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
};
&cec_AO {
status = "okay";
pinctrl-0 = <&ao_cec_pins>;
pinctrl-names = "default";
hdmi-phandle = <&hdmi_tx>;
};
&cpu0 {
cooling-min-level = <0>;
cooling-max-level = <6>;
#cooling-cells = <2>;
};
&cpu4 {
cooling-min-level = <0>;
cooling-max-level = <4>;
#cooling-cells = <2>;
};
&ethmac {
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
/* Select external PHY by default */
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
/* External PHY reset is shared with internal PHY Led signals */
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
/* External PHY is in RGMII */
phy-mode = "rgmii";
status = "okay";
};
&external_mdio {
external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&i2c_A {
status = "okay";
pinctrl-0 = <&i2c_a_pins>;
pinctrl-names = "default";
};
&i2c_B {
status = "okay";
pinctrl-0 = <&i2c_b_pins>;
pinctrl-names = "default";
rtc: rtc@51 {
/* has to be enabled manually when a battery is connected: */
status = "disabled";
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
linux,rc-map-name = "rc-geekbox";
};
&pwm_AO_ab {
status = "okay";
pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/*
* EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe
* Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled
*/
&spifc {
status = "disabled";
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
w25q32: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q16", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <3000000>;
};
};
/* This one is connected to the Bluetooth module */
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>;
pinctrl-names = "default";
};
/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */
&uart_AO_B {
status = "okay";
pinctrl-0 = <&uart_ao_b_pins>;
pinctrl-names = "default";
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
};

2
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
View file

@ -193,7 +193,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";

2
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
View file

@ -110,6 +110,8 @@
compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <1000>;
interrupt-parent = <&gpio_intc>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};

2
arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
View file

@ -216,7 +216,7 @@
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-names = "default";
bus-width = <8>;

38
arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts Normal file
View file

@ -0,0 +1,38 @@
/*
* Copyright (c) 2017 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
* Copyright (c) 2017 Oleg <balbes-150@yandex.ru>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "meson-gxm.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
/ {
compatible = "tronsmart,vega-s96", "amlogic,s912", "amlogic,meson-gxm";
model = "Tronsmart Vega S96";
};
&ethmac {
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
/* Select external PHY by default */
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
/* External PHY is in RGMII */
phy-mode = "rgmii";
};
&external_mdio {
external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
};
};

6
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
View file

@ -19,7 +19,7 @@
#address-cells = <2>;
#size-cells = <0>;
cpu@000 {
cpu@0 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
reg = <0x0 0x000>;
@ -29,7 +29,7 @@
#clock-cells = <1>;
clocks = <&pmd0clk 0>;
};
cpu@001 {
cpu@1 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
reg = <0x0 0x001>;
@ -125,7 +125,7 @@
<0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
<0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
<0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
v2m0: v2m@00000 {
v2m0: v2m@0 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x0 0x0 0x1000>;

4
arch/arm64/boot/dts/apm/apm-storm.dtsi
View file

@ -19,7 +19,7 @@
#address-cells = <2>;
#size-cells = <0>;
cpu@000 {
cpu@0 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
reg = <0x0 0x000>;
@ -27,7 +27,7 @@
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_0>;
};
cpu@001 {
cpu@1 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
reg = <0x0 0x001>;

4
arch/arm64/boot/dts/arm/Makefile
View file

@ -1,5 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += \
foundation-v8.dtb foundation-v8-psci.dtb \
foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb

19
arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi Normal file
View file

@ -0,0 +1,19 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (GICv2 configuration)
*/
/ {
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <2>;
interrupt-controller;
reg = <0x0 0x2c001000 0 0x1000>,
<0x0 0x2c002000 0 0x2000>,
<0x0 0x2c004000 0 0x2000>,
<0x0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
};

9
arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts Normal file
View file

@ -0,0 +1,9 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (GICv3+PSCI configuration)
*/
#include "foundation-v8.dtsi"
#include "foundation-v8-gicv3.dtsi"
#include "foundation-v8-psci.dtsi"

25
arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts
View file

@ -6,26 +6,5 @@
*/
#include "foundation-v8.dtsi"
/ {
gic: interrupt-controller@2f000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x2f000000 0x0 0x10000>,
<0x0 0x2f100000 0x0 0x200000>,
<0x0 0x2c000000 0x0 0x2000>,
<0x0 0x2c010000 0x0 0x2000>,
<0x0 0x2c02f000 0x0 0x2000>;
interrupts = <1 9 4>;
its: its@2f020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x2f020000 0x0 0x20000>;
};
};
};
#include "foundation-v8-gicv3.dtsi"
#include "foundation-v8-spin-table.dtsi"

28
arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi Normal file
View file

@ -0,0 +1,28 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (GICv3 configuration)
*/
/ {
gic: interrupt-controller@2f000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x2f000000 0x0 0x10000>,
<0x0 0x2f100000 0x0 0x200000>,
<0x0 0x2c000000 0x0 0x2000>,
<0x0 0x2c010000 0x0 0x2000>,
<0x0 0x2c02f000 0x0 0x2000>;
interrupts = <1 9 4>;
its: its@2f020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x2f020000 0x0 0x20000>;
};
};
};

9
arch/arm64/boot/dts/arm/foundation-v8-psci.dts Normal file
View file

@ -0,0 +1,9 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (GICv2+PSCI configuration)
*/
#include "foundation-v8.dtsi"
#include "foundation-v8-gicv2.dtsi"
#include "foundation-v8-psci.dtsi"

28
arch/arm64/boot/dts/arm/foundation-v8-psci.dtsi Normal file
View file

@ -0,0 +1,28 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (PSCI configuration)
*/
/ {
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
&cpu0 {
enable-method = "psci";
};
&cpu1 {
enable-method = "psci";
};
&cpu2 {
enable-method = "psci";
};
&cpu3 {
enable-method = "psci";
};

25
arch/arm64/boot/dts/arm/foundation-v8-spin-table.dtsi Normal file
View file

@ -0,0 +1,25 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (spin table configuration)
*/
&cpu0 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
&cpu1 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
&cpu2 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
&cpu3 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};

16
arch/arm64/boot/dts/arm/foundation-v8.dts
View file

@ -6,17 +6,5 @@
*/
#include "foundation-v8.dtsi"
/ {
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <2>;
interrupt-controller;
reg = <0x0 0x2c001000 0 0x1000>,
<0x0 0x2c002000 0 0x2000>,
<0x0 0x2c004000 0 0x2000>,
<0x0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
};
#include "foundation-v8-gicv2.dtsi"
#include "foundation-v8-spin-table.dtsi"

30
arch/arm64/boot/dts/arm/foundation-v8.dtsi
View file

@ -29,36 +29,28 @@
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
@ -98,7 +90,7 @@
timeout-sec = <30>;
};
smb@08000000 {
smb@8000000 {
compatible = "arm,vexpress,v2m-p1", "simple-bus";
arm,v2m-memory-map = "rs1";
#address-cells = <2>; /* SMB chipselect number and offset */
@ -190,12 +182,12 @@
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysreg: sysreg@010000 {
v2m_sysreg: sysreg@10000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
};
v2m_serial0: uart@090000 {
v2m_serial0: uart@90000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
@ -203,7 +195,7 @@
clock-names = "uartclk", "apb_pclk";
};
v2m_serial1: uart@0a0000 {
v2m_serial1: uart@a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
@ -211,7 +203,7 @@
clock-names = "uartclk", "apb_pclk";
};
v2m_serial2: uart@0b0000 {
v2m_serial2: uart@b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
@ -219,7 +211,7 @@
clock-names = "uartclk", "apb_pclk";
};
v2m_serial3: uart@0c0000 {
v2m_serial3: uart@c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
@ -227,7 +219,7 @@
clock-names = "uartclk", "apb_pclk";
};
virtio-block@0130000 {
virtio-block@130000 {
compatible = "virtio,mmio";
reg = <0x130000 0x200>;
interrupts = <42>;

2
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
View file

@ -105,7 +105,7 @@
<0 63 4>;
};
smb@08000000 {
smb@8000000 {
compatible = "simple-bus";
#address-cells = <2>;

24
arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
View file

@ -61,14 +61,14 @@
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysreg: sysreg@010000 {
v2m_sysreg: sysreg@10000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};
v2m_sysctl: sysctl@020000 {
v2m_sysctl: sysctl@20000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
@ -79,7 +79,7 @@
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
};
aaci@040000 {
aaci@40000 {
compatible = "arm,pl041", "arm,primecell";
reg = <0x040000 0x1000>;
interrupts = <11>;
@ -87,7 +87,7 @@
clock-names = "apb_pclk";
};
mmci@050000 {
mmci@50000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
interrupts = <9 10>;
@ -99,7 +99,7 @@
clock-names = "mclk", "apb_pclk";
};
kmi@060000 {
kmi@60000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x060000 0x1000>;
interrupts = <12>;
@ -107,7 +107,7 @@
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@070000 {
kmi@70000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x070000 0x1000>;
interrupts = <13>;
@ -115,7 +115,7 @@
clock-names = "KMIREFCLK", "apb_pclk";
};
v2m_serial0: uart@090000 {
v2m_serial0: uart@90000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
@ -123,7 +123,7 @@
clock-names = "uartclk", "apb_pclk";
};
v2m_serial1: uart@0a0000 {
v2m_serial1: uart@a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
@ -131,7 +131,7 @@
clock-names = "uartclk", "apb_pclk";
};
v2m_serial2: uart@0b0000 {
v2m_serial2: uart@b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
@ -139,7 +139,7 @@
clock-names = "uartclk", "apb_pclk";
};
v2m_serial3: uart@0c0000 {
v2m_serial3: uart@c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
@ -147,7 +147,7 @@
clock-names = "uartclk", "apb_pclk";
};
wdt@0f0000 {
wdt@f0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0f0000 0x1000>;
interrupts = <0>;
@ -220,7 +220,7 @@
};
};
virtio-block@0130000 {
virtio-block@130000 {
compatible = "virtio,mmio";
reg = <0x130000 0x200>;
interrupts = <42>;

2
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
View file

@ -129,7 +129,7 @@
};
};
smb@08000000 {
smb@8000000 {
compatible = "simple-bus";
#address-cells = <2>;

2
arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts
View file

@ -114,7 +114,7 @@
reg = <0x04000000 0x06400000>; /* 100MB */
};
partition@0a400000{
partition@a400000{
label = "ncustfs";
reg = <0x0a400000 0x35c00000>; /* 860MB */
};

4
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
View file

@ -77,7 +77,7 @@
next-level-cache = <&CLUSTER0_L2>;
};
CLUSTER0_L2: l2-cache@000 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
};
};
@ -367,7 +367,7 @@
#size-cells = <1>;
ranges = <0 0x652e0000 0x80000>;
v2m0: v2m@00000 {
v2m0: v2m@0 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;

12
arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi
View file

@ -46,7 +46,7 @@
clock-mult = <1>;
};
genpll0: genpll0@0001d104 {
genpll0: genpll0@1d104 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll0";
reg = <0x0001d104 0x32>,
@ -58,7 +58,7 @@
"clk_paxc_axi";
};
genpll3: genpll3@0001d1e0 {
genpll3: genpll3@1d1e0 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll3";
reg = <0x0001d1e0 0x32>,
@ -68,7 +68,7 @@
"clk_sdio";
};
genpll4: genpll4@0001d214 {
genpll4: genpll4@1d214 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll4";
reg = <0x0001d214 0x32>,
@ -80,7 +80,7 @@
"clk_bridge_fscpu";
};
genpll5: genpll5@0001d248 {
genpll5: genpll5@1d248 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll5";
reg = <0x0001d248 0x32>,
@ -90,7 +90,7 @@
"crypto_ae_clk", "raid_ae_clk";
};
lcpll0: lcpll0@0001d0c4 {
lcpll0: lcpll0@1d0c4 {
#clock-cells = <1>;
compatible = "brcm,sr-lcpll0";
reg = <0x0001d0c4 0x3c>,
@ -101,7 +101,7 @@
"clk_sata_500";
};
lcpll1: lcpll1@0001d138 {
lcpll1: lcpll1@1d138 {
#clock-cells = <1>;
compatible = "brcm,sr-lcpll1";
reg = <0x0001d138 0x3c>,

4
arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi
View file

@ -36,7 +36,7 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x67000000 0x00800000>;
crypto_mbox: crypto_mbox@00000000 {
crypto_mbox: crypto_mbox@0 {
compatible = "brcm,iproc-flexrm-mbox";
reg = <0x00000000 0x200000>;
msi-parent = <&gic_its 0x4100>;
@ -44,7 +44,7 @@
dma-coherent;
};
raid_mbox: raid_mbox@00400000 {
raid_mbox: raid_mbox@400000 {
compatible = "brcm,iproc-flexrm-mbox";
reg = <0x00400000 0x200000>;
dma-coherent;

4
arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
View file

@ -32,7 +32,7 @@
#include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
pinconf: pinconf@00140000 {
pinconf: pinconf@140000 {
compatible = "pinconf-single";
reg = <0x00140000 0x250>;
pinctrl-single,register-width = <32>;
@ -40,7 +40,7 @@
/* pinconf functions */
};
pinmux: pinmux@0014029c {
pinmux: pinmux@14029c {
compatible = "pinctrl-single";
reg = <0x0014029c 0x250>;
#address-cells = <1>;

32
arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi
View file

@ -36,7 +36,7 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x67d00000 0x00800000>;
sata0: ahci@00210000 {
sata0: ahci@210000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00210000 0x1000>;
reg-names = "ahci";
@ -52,7 +52,7 @@
};
};
sata_phy0: sata_phy@00212100 {
sata_phy0: sata_phy@212100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00212100 0x1000>;
reg-names = "phy";
@ -66,7 +66,7 @@
};
};
sata1: ahci@00310000 {
sata1: ahci@310000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00310000 0x1000>;
reg-names = "ahci";
@ -82,7 +82,7 @@
};
};
sata_phy1: sata_phy@00312100 {
sata_phy1: sata_phy@312100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00312100 0x1000>;
reg-names = "phy";
@ -96,7 +96,7 @@
};
};
sata2: ahci@00120000 {
sata2: ahci@120000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00120000 0x1000>;
reg-names = "ahci";
@ -112,7 +112,7 @@
};
};
sata_phy2: sata_phy@00122100 {
sata_phy2: sata_phy@122100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00122100 0x1000>;
reg-names = "phy";
@ -126,7 +126,7 @@
};
};
sata3: ahci@00130000 {
sata3: ahci@130000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00130000 0x1000>;
reg-names = "ahci";
@ -142,7 +142,7 @@
};
};
sata_phy3: sata_phy@00132100 {
sata_phy3: sata_phy@132100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00132100 0x1000>;
reg-names = "phy";
@ -156,7 +156,7 @@
};
};
sata4: ahci@00330000 {
sata4: ahci@330000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00330000 0x1000>;
reg-names = "ahci";
@ -172,7 +172,7 @@
};
};
sata_phy4: sata_phy@00332100 {
sata_phy4: sata_phy@332100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00332100 0x1000>;
reg-names = "phy";
@ -186,7 +186,7 @@
};
};
sata5: ahci@00400000 {
sata5: ahci@400000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00400000 0x1000>;
reg-names = "ahci";
@ -202,7 +202,7 @@
};
};
sata_phy5: sata_phy@00402100 {
sata_phy5: sata_phy@402100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00402100 0x1000>;
reg-names = "phy";
@ -216,7 +216,7 @@
};
};
sata6: ahci@00410000 {
sata6: ahci@410000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00410000 0x1000>;
reg-names = "ahci";
@ -232,7 +232,7 @@
};
};
sata_phy6: sata_phy@00412100 {
sata_phy6: sata_phy@412100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00412100 0x1000>;
reg-names = "phy";
@ -246,7 +246,7 @@
};
};
sata7: ahci@00420000 {
sata7: ahci@420000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00420000 0x1000>;
reg-names = "ahci";
@ -262,7 +262,7 @@
};
};
sata_phy7: sata_phy@00422100 {
sata_phy7: sata_phy@422100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00422100 0x1000>;
reg-names = "phy";

66
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
View file

@ -42,7 +42,7 @@
#address-cells = <2>;
#size-cells = <0>;
cpu@000 {
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x0>;
@ -50,7 +50,7 @@
next-level-cache = <&CLUSTER0_L2>;
};
cpu@001 {
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x1>;
@ -106,7 +106,7 @@
next-level-cache = <&CLUSTER3_L2>;
};
CLUSTER0_L2: l2-cache@000 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
};
@ -152,13 +152,13 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x61000000 0x05000000>;
ccn: ccn@00000000 {
ccn: ccn@0 {
compatible = "arm,ccn-502";
reg = <0x00000000 0x900000>;
interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@02c00000 {
gic: interrupt-controller@2c00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <1>;
@ -177,7 +177,7 @@
};
};
smmu: mmu@03000000 {
smmu: mmu@3000000 {
compatible = "arm,mmu-500";
reg = <0x03000000 0x80000>;
#global-interrupts = <1>;
@ -258,7 +258,7 @@
#include "stingray-clock.dtsi"
gpio_crmu: gpio@00024800 {
gpio_crmu: gpio@24800 {
compatible = "brcm,iproc-gpio";
reg = <0x00024800 0x4c>;
ngpios = <6>;
@ -278,7 +278,7 @@
#include "stingray-pinctrl.dtsi"
mdio_mux_iproc: mdio-mux@0002023c {
mdio_mux_iproc: mdio-mux@2023c {
compatible = "brcm,mdio-mux-iproc";
reg = <0x0002023c 0x14>;
#address-cells = <1>;
@ -309,7 +309,7 @@
};
};
pwm: pwm@00010000 {
pwm: pwm@10000 {
compatible = "brcm,iproc-pwm";
reg = <0x00010000 0x1000>;
clocks = <&crmu_ref25m>;
@ -317,7 +317,7 @@
status = "disabled";
};
timer0: timer@00030000 {
timer0: timer@30000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00030000 0x1000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
@ -328,7 +328,7 @@
status = "disabled";
};
timer1: timer@00040000 {
timer1: timer@40000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00040000 0x1000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
@ -338,7 +338,7 @@
clock-names = "timer1", "timer2", "apb_pclk";
};
timer2: timer@00050000 {
timer2: timer@50000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00050000 0x1000>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
@ -349,7 +349,7 @@
status = "disabled";
};
timer3: timer@00060000 {
timer3: timer@60000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00060000 0x1000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
@ -360,7 +360,7 @@
status = "disabled";
};
timer4: timer@00070000 {
timer4: timer@70000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00070000 0x1000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
@ -371,7 +371,7 @@
status = "disabled";
};
timer5: timer@00080000 {
timer5: timer@80000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00080000 0x1000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@ -382,7 +382,7 @@
status = "disabled";
};
timer6: timer@00090000 {
timer6: timer@90000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00090000 0x1000>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
@ -393,7 +393,7 @@
status = "disabled";
};
timer7: timer@000a0000 {
timer7: timer@a0000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x000a0000 0x1000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
@ -404,7 +404,7 @@
status = "disabled";
};
i2c0: i2c@000b0000 {
i2c0: i2c@b0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000b0000 0x100>;
#address-cells = <1>;
@ -414,7 +414,7 @@
status = "disabled";
};
wdt0: watchdog@000c0000 {
wdt0: watchdog@c0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x000c0000 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
@ -422,7 +422,7 @@
clock-names = "wdogclk", "apb_pclk";
};
gpio_hsls: gpio@000d0000 {
gpio_hsls: gpio@d0000 {
compatible = "brcm,iproc-gpio";
reg = <0x000d0000 0x864>;
ngpios = <151>;
@ -448,7 +448,7 @@
<&pinmux 151 91 4>;
};
i2c1: i2c@000e0000 {
i2c1: i2c@e0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000e0000 0x100>;
#address-cells = <1>;
@ -458,7 +458,7 @@
status = "disabled";
};
uart0: uart@00100000 {
uart0: uart@100000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00100000 0x1000>;
@ -469,7 +469,7 @@
status = "disabled";
};
uart1: uart@00110000 {
uart1: uart@110000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00110000 0x1000>;
@ -480,7 +480,7 @@
status = "disabled";
};
uart2: uart@00120000 {
uart2: uart@120000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00120000 0x1000>;
@ -491,7 +491,7 @@
status = "disabled";
};
uart3: uart@00130000 {
uart3: uart@130000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00130000 0x1000>;
@ -502,7 +502,7 @@
status = "disabled";
};
ssp0: ssp@00180000 {
ssp0: ssp@180000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x00180000 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
@ -514,7 +514,7 @@
status = "disabled";
};
ssp1: ssp@00190000 {
ssp1: ssp@190000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x00190000 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
@ -526,12 +526,12 @@
status = "disabled";
};
hwrng: hwrng@00220000 {
hwrng: hwrng@220000 {
compatible = "brcm,iproc-rng200";
reg = <0x00220000 0x28>;
};
dma0: dma@00310000 {
dma0: dma@310000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x00310000 0x1000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
@ -551,7 +551,7 @@
iommus = <&smmu 0x6000 0x0000>;
};
enet: ethernet@00340000{
enet: ethernet@340000{
compatible = "brcm,amac";
reg = <0x00340000 0x1000>;
reg-names = "amac_base";
@ -560,7 +560,7 @@
status= "disabled";
};
nand: nand@00360000 {
nand: nand@360000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x00360000 0x600>,
<0x0050a408 0x600>,
@ -573,7 +573,7 @@
status = "disabled";
};
sdio0: sdhci@003f1000 {
sdio0: sdhci@3f1000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f1000 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
@ -583,7 +583,7 @@
status = "disabled";
};
sdio1: sdhci@003f2000 {
sdio1: sdhci@3f2000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f2000 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm64/boot/dts/cavium/thunder-88xx.dts
View file

@ -60,7 +60,7 @@
serial1 = &uaa1;
};
memory@00000000 {
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
};

32
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
View file

@ -62,97 +62,97 @@
#address-cells = <2>;
#size-cells = <0>;
cpu@000 {
cpu@0 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x000>;
enable-method = "psci";
};
cpu@001 {
cpu@1 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x001>;
enable-method = "psci";
};
cpu@002 {
cpu@2 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x002>;
enable-method = "psci";
};
cpu@003 {
cpu@3 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x003>;
enable-method = "psci";
};
cpu@004 {
cpu@4 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x004>;
enable-method = "psci";
};
cpu@005 {
cpu@5 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x005>;
enable-method = "psci";
};
cpu@006 {
cpu@6 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x006>;
enable-method = "psci";
};
cpu@007 {
cpu@7 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x007>;
enable-method = "psci";
};
cpu@008 {
cpu@8 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x008>;
enable-method = "psci";
};
cpu@009 {
cpu@9 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x009>;
enable-method = "psci";
};
cpu@00a {
cpu@a {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00a>;
enable-method = "psci";
};
cpu@00b {
cpu@b {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00b>;
enable-method = "psci";
};
cpu@00c {
cpu@c {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00c>;
enable-method = "psci";
};
cpu@00d {
cpu@d {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00d>;
enable-method = "psci";
};
cpu@00e {
cpu@e {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00e>;
enable-method = "psci";
};
cpu@00f {
cpu@f {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00f>;

33
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
View file

@ -93,6 +93,39 @@
};
};
&dspi {
bus-num = <0>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a11", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
};
flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst25wf040b", "jedec,spi-nor";
spi-cpol;
spi-cpha;
reg = <1>;
spi-max-frequency = <10000000>;
};
flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "en25s64", "jedec,spi-nor";
spi-cpol;
spi-cpha;
reg = <2>;
spi-max-frequency = <10000000>;
};
};
&duart0 {
status = "okay";
};

20
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View file

@ -355,6 +355,19 @@
status = "disabled";
};
dspi: dspi@2100000 {
compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
spi-num-chipselects = <5>;
big-endian;
status = "disabled";
};
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
@ -503,4 +516,11 @@
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
};
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};

11
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View file

@ -376,14 +376,14 @@
qman: qman@1880000 {
compatible = "fsl,qman";
reg = <0x0 0x1880000 0x0 0x10000>;
interrupts = <0 45 0x4>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&qman_fqd &qman_pfdr>;
};
bman: bman@1890000 {
compatible = "fsl,bman";
reg = <0x0 0x1890000 0x0 0x10000>;
interrupts = <0 45 0x4>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&bman_fbpr>;
};
@ -749,6 +749,13 @@
};
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
#include "qoriq-qman-portals.dtsi"

11
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View file

@ -281,7 +281,7 @@
qman: qman@1880000 {
compatible = "fsl,qman";
reg = <0x0 0x1880000 0x0 0x10000>;
interrupts = <0 45 0x4>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&qman_fqd &qman_pfdr>;
};
@ -289,7 +289,7 @@
bman: bman@1890000 {
compatible = "fsl,bman";
reg = <0x0 0x1890000 0x0 0x10000>;
interrupts = <0 45 0x4>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&bman_fbpr>;
};
@ -764,6 +764,13 @@
no-map;
};
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
#include "qoriq-qman-portals.dtsi"

88
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View file

@ -147,6 +147,15 @@
<0x0 0x0c0d0000 0 0x1000>, /* GICH */
<0x0 0x0c0e0000 0 0x20000>; /* GICV */
interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
its: gic-its@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x6020000 0 0x20000>;
};
};
timer {
@ -434,6 +443,85 @@
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
};
};
pcie@3400000 {
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x20 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
};
pcie@3500000 {
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x28 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
};
pcie@3600000 {
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x30 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
};
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};

4
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
View file

@ -151,6 +151,7 @@
};
&pcie1 {
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x20 0x00000000 0x0 0x00002000>; /* configuration space */
@ -159,6 +160,7 @@
};
&pcie2 {
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x28 0x00000000 0x0 0x00002000>; /* configuration space */
@ -167,6 +169,7 @@
};
&pcie3 {
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x30 0x00000000 0x0 0x00002000>; /* configuration space */
@ -175,6 +178,7 @@
};
&pcie4 {
compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x38 0x00000000 0x0 0x00002000>; /* configuration space */

7
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View file

@ -786,4 +786,11 @@
interrupts = <0 18 0x4>;
little-endian;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};

319
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
View file

@ -197,6 +197,325 @@
};
};
/*
* Legend: proper name = the GPIO line is used as GPIO
* NC = not connected (pin out but not routed from the chip to
* anything the board)
* "[PER]" = pin is muxed for [peripheral] (not GPIO)
* "" = no idea, schematic doesn't say, could be
* unrouted (not connected to any external pin)
* LSEC = Low Speed External Connector
* HSEC = High Speed External Connector
*
* Line names are taken from "HiKey 960 Board ver A" schematics
* from Huawei. The 40 pin low speed expansion connector is named
* J2002 63453-140LF.
*
* For the lines routed to the external connectors the
* lines are named after the 96Boards CE Specification 1.0,
* Appendix "Expansion Connector Signal Description".
*
* When the 96Board naming of a line and the schematic name of
* the same line are in conflict, the 96Board specification
* takes precedence, which means that the external UART on the
* LSEC is named UART0 while the schematic and SoC names this
* UART3. This is only for the informational lines i.e. "[FOO]",
* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
* ones actually used for GPIO.
*/
&gpio0 {
/* GPIO_000-GPIO_007 */
gpio-line-names =
"",
"TP901", /* TEST_MODE connected to TP901 */
"[PMU0_SSI]",
"[PMU1_SSI]",
"[PMU2_SSI]",
"[PMU0_CLKOUT]",
"[JTAG_TCK]",
"[JTAG_TMS]";
};
&gpio1 {
/* GPIO_008-GPIO_015 */
gpio-line-names =
"[JTAG_TRST_N]",
"[JTAG_TDI]",
"[JTAG_TDO]",
"NC", "NC",
"[I2C3_SCL]",
"[I2C3_SDA]",
"NC";
};
&gpio2 {
/* GPIO_016-GPIO_023 */
gpio-line-names =
"NC", "NC", "NC",
"GPIO-J", /* LSEC pin 32: GPIO_019 */
"GPIO_020_HDMI_SEL",
"GPIO-L", /* LSEC pin 34: GPIO_021 */
"GPIO_022_UFSBUCK_INT_N",
"GPIO-G"; /* LSEC pin 29: LCD_TE0 */
};
&gpio3 {
/* GPIO_024-GPIO_031 */
/* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */
gpio-line-names =
"[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */
"[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */
"NC",
"[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */
"[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */
"[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */
"[I2C3_SDA]", /* HSEC pin 38: ISP_SDA1 */
"NC";
};
&gpio4 {
/* GPIO_032-GPIO_039 */
gpio-line-names =
"NC", "NC",
"PWR_BTN_N", /* LSEC pin 4: GPIO_034_PWRON_DET */
"GPIO_035_PMU2_EN",
"GPIO_036_USB_HUB_RESET",
"NC", "NC", "NC";
};
&gpio5 {
/* GPIO_040-GPIO_047 */
gpio-line-names =
"GPIO-H", /* LSEC pin 30: GPIO_040_LCD_RST_N */
"GPIO_041_HDMI_PD",
"TP904", /* Test point */
"TP905", /* Test point */
"NC", "NC",
"GPIO_046_HUB_VDD33_EN",
"GPIO_047_PMU1_EN";
};
&gpio6 {
/* GPIO_048-GPIO_055 */
gpio-line-names =
"NC", "NC", "NC",
"GPIO_051_WIFI_EN",
"GPIO-I", /* LSEC pin 31: GPIO_052_CAM0_RST_N */
/*
* These two pins should be used for SD(IO) data according to the
* 96boards specification but seems to be repurposed for a IRDA UART.
* They are however named according to the spec.
*/
"[SD_DAT1]", /* HSEC pin 3: UART0_IRDA_RXD */
"[SD_DAT2]", /* HSEC pin 5: UART0_IRDA_TXD */
"[UART1_RXD]"; /* LSEC pin 13: DEBUG_UART6_RXD */
};
&gpio7 {
/* GPIO_056-GPIO_063 */
gpio-line-names =
"[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */
"[UART0_CTS]", /* LSEC pin 3: UART3_CTS_N */
"[UART0_RTS]", /* LSEC pin 9: UART3_RTS_N */
"[UART0_RXD]", /* LSEC pin 7: UART3_RXD */
"[UART0_TXD]", /* LSEC pin 5: UART3_TXD */
"[SOC_BT_UART4_CTS_N]",
"[SOC_BT_UART4_RTS_N]",
"[SOC_BT_UART4_RXD]";
};
&gpio8 {
/* GPIO_064-GPIO_071 */
gpio-line-names =
"[SOC_BT_UART4_TXD]",
"NC",
"[PMU_HKADC_SSI]",
"NC",
"GPIO_068_SEL",
"NC", "NC", "NC";
};
&gpio9 {
/* GPIO_072-GPIO_079 */
gpio-line-names =
"NC", "NC", "NC",
"GPIO-K", /* LSEC pin 33: GPIO_075_CAM1_RST_N */
"NC", "NC", "NC", "NC";
};
&gpio10 {
/* GPIO_080-GPIO_087 */
gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio11 {
/* GPIO_088-GPIO_095 */
gpio-line-names =
"NC",
"[PCIE_PERST_N]",
"NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio12 {
/* GPIO_096-GPIO_103 */
gpio-line-names = "NC", "NC", "NC", "", "", "", "", "NC";
};
&gpio13 {
/* GPIO_104-GPIO_111 */
gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio14 {
/* GPIO_112-GPIO_119 */
gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio15 {
/* GPIO_120-GPIO_127 */
gpio-line-names =
"NC", "NC", "NC", "NC", "NC", "NC",
"GPIO_126_BT_EN",
"TP902"; /* GPIO_127_JTAG_SEL0 */
};
&gpio16 {
/* GPIO_128-GPIO_135 */
gpio-line-names = "", "", "", "", "", "", "", "";
};
&gpio17 {
/* GPIO_136-GPIO_143 */
gpio-line-names = "", "", "", "", "", "", "", "";
};
&gpio18 {
/* GPIO_144-GPIO_151 */
gpio-line-names =
"[UFS_REF_CLK]",
"[UFS_RST_N]",
"[SPI1_SCLK]", /* HSEC pin 9: GPIO_146_SPI3_CLK */
"[SPI1_DIN]", /* HSEC pin 11: GPIO_147_SPI3_DI */
"[SPI1_DOUT]", /* HSEC pin 1: GPIO_148_SPI3_DO */
"[SPI1_CS]", /* HSEC pin 7: GPIO_149_SPI3_CS0_N */
"GPIO_150_USER_LED1",
"GPIO_151_USER_LED2";
};
&gpio19 {
/* GPIO_152-GPIO_159 */
gpio-line-names = "NC", "NC", "NC", "NC", "", "", "", "";
};
&gpio20 {
/* GPIO_160-GPIO_167 */
gpio-line-names =
"[SD_CLK]",
"[SD_CMD]",
"[SD_DATA0]",
"[SD_DATA1]",
"[SD_DATA2]",
"[SD_DATA3]",
"", "";
};
&gpio21 {
/* GPIO_168-GPIO_175 */
gpio-line-names =
"[WL_SDIO_CLK]",
"[WL_SDIO_CMD]",
"[WL_SDIO_DATA0]",
"[WL_SDIO_DATA1]",
"[WL_SDIO_DATA2]",
"[WL_SDIO_DATA3]",
"", "";
};
&gpio22 {
/* GPIO_176-GPIO_183 */
gpio-line-names =
"[GPIO_176_PMU_PWR_HOLD]",
"NA",
"[SYSCLK_EN]",
"GPIO_179_WL_WAKEUP_AP",
"GPIO_180_HDMI_INT",
"NA",
"GPIO-F", /* LSEC pin 28: LCD_BL_PWM */
"[I2C0_SCL]"; /* LSEC pin 15 */
};
&gpio23 {
/* GPIO_184-GPIO_191 */
gpio-line-names =
"[I2C0_SDA]", /* LSEC pin 17 */
"[I2C1_SCL]", /* Actual SoC I2C1 */
"[I2C1_SDA]", /* Actual SoC I2C1 */
"[I2C1_SCL]", /* LSEC pin 19: I2C7_SCL */
"[I2C1_SDA]", /* LSEC pin 21: I2C7_SDA */
"GPIO_189_USER_LED3",
"GPIO_190_USER_LED4",
"";
};
&gpio24 {
/* GPIO_192-GPIO_199 */
gpio-line-names =
"[PCM_DI]", /* LSEC pin 22: GPIO_192_I2S0_DI */
"[PCM_DO]", /* LSEC pin 20: GPIO_193_I2S0_DO */
"[PCM_CLK]", /* LSEC pin 18: GPIO_194_I2S0_XCLK */
"[PCM_FS]", /* LSEC pin 16: GPIO_195_I2S0_XFS */
"[GPIO_196_I2S2_DI]",
"[GPIO_197_I2S2_DO]",
"[GPIO_198_I2S2_XCLK]",
"[GPIO_199_I2S2_XFS]";
};
&gpio25 {
/* GPIO_200-GPIO_207 */
gpio-line-names =
"NC",
"NC",
"GPIO_202_VBUS_TYPEC",
"GPIO_203_SD_DET",
"GPIO_204_PMU12_IRQ_N",
"GPIO_205_WIFI_ACTIVE",
"GPIO_206_USBSW_SEL",
"GPIO_207_BT_ACTIVE";
};
&gpio26 {
/* GPIO_208-GPIO_215 */
gpio-line-names =
"GPIO-A", /* LSEC pin 23: GPIO_208 */
"GPIO-B", /* LSEC pin 24: GPIO_209 */
"GPIO-C", /* LSEC pin 25: GPIO_210 */
"GPIO-D", /* LSEC pin 26: GPIO_211 */
"GPIO-E", /* LSEC pin 27: GPIO_212 */
"[PCIE_CLKREQ_N]",
"[PCIE_WAKE_N]",
"[SPI0_CLK]"; /* LSEC pin 8: SPI2_CLK */
};
&gpio27 {
/* GPIO_216-GPIO_223 */
gpio-line-names =
"[SPI0_DIN]", /* LSEC pin 10: SPI2_DI */
"[SPI0_DOUT]", /* LSEC pin 14: SPI2_DO */
"[SPI0_CS]", /* LSEC pin 12: SPI2_CS0_N */
"GPIO_219_CC_INT",
"NC",
"NC",
"[PMU_INT]",
"";
};
&gpio28 {
/* GPIO_224-GPIO_231 */
gpio-line-names =
"", "", "", "", "", "", "", "";
};
&i2c0 {
/* On Low speed expansion */
label = "LS-I2C0";

7
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
View file

@ -979,5 +979,12 @@
clocks = <&crg_ctrl HI3660_OSC32K>;
clock-names = "apb_pclk";
};
tsensor: tsensor@fff30000 {
compatible = "hisilicon,hi3660-tsensor";
reg = <0x0 0xfff30000 0x0 0x1000>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <1>;
};
};
};

20
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
View file

@ -78,17 +78,17 @@
&gpio1 {
status = "okay";
gpio-line-names = "LS-GPIO-E", "",
gpio-line-names = "GPIO-E", "",
"", "",
"", "LS-GPIO-F",
"", "LS-GPIO-J";
"", "GPIO-F",
"", "GPIO-J";
};
&gpio2 {
status = "okay";
gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
"LS-GPIO-L", "LS-GPIO-G",
"LS-GPIO-K", "",
gpio-line-names = "GPIO-H", "GPIO-I",
"GPIO-L", "GPIO-G",
"GPIO-K", "",
"", "";
};
@ -96,15 +96,15 @@
status = "okay";
gpio-line-names = "", "",
"", "",
"LS-GPIO-C", "",
"", "LS-GPIO-B";
"GPIO-C", "",
"", "GPIO-B";
};
&gpio4 {
status = "okay";
gpio-line-names = "", "",
"", "",
"", "LS-GPIO-D",
"", "GPIO-D",
"", "";
};
@ -112,7 +112,7 @@
status = "okay";
gpio-line-names = "", "USER-LED-1",
"USER-LED-2", "",
"", "LS-GPIO-A",
"", "GPIO-A",
"", "";
};

381
arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi Normal file
View file

@ -0,0 +1,381 @@
/*
* dtsi file for Hisilicon Hi6220 coresight
*
* Copyright (C) 2017 Hisilicon Ltd.
*
* Author: Pengcheng Li <lipengcheng8@huawei.com>
* Leo Yan <leo.yan@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*
*/
/ {
soc {
funnel@f6401000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0xf6401000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
soc_funnel_out: endpoint {
remote-endpoint =
<&etf_in>;
};
};
port@1 {
reg = <0>;
soc_funnel_in: endpoint {
slave-mode;
remote-endpoint =
<&acpu_funnel_out>;
};
};
};
};
etf@f6402000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0xf6402000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
etf_in: endpoint {
slave-mode;
remote-endpoint =
<&soc_funnel_out>;
};
};
port@1 {
reg = <0>;
etf_out: endpoint {
remote-endpoint =
<&replicator_in>;
};
};
};
};
replicator {
compatible = "arm,coresight-replicator";
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator_in: endpoint {
slave-mode;
remote-endpoint =
<&etf_out>;
};
};
port@1 {
reg = <0>;
replicator_out0: endpoint {
remote-endpoint =
<&etr_in>;
};
};
port@2 {
reg = <1>;
replicator_out1: endpoint {
remote-endpoint =
<&tpiu_in>;
};
};
};
};
etr@f6404000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0xf6404000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
etr_in: endpoint {
slave-mode;
remote-endpoint =
<&replicator_out0>;
};
};
};
};
tpiu@f6405000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0 0xf6405000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpiu_in: endpoint {
slave-mode;
remote-endpoint =
<&replicator_out1>;
};
};
};
};
funnel@f6501000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0xf6501000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
acpu_funnel_out: endpoint {
remote-endpoint =
<&soc_funnel_in>;
};
};
port@1 {
reg = <0>;
acpu_funnel_in0: endpoint {
slave-mode;
remote-endpoint =
<&etm0_out>;
};
};
port@2 {
reg = <1>;
acpu_funnel_in1: endpoint {
slave-mode;
remote-endpoint =
<&etm1_out>;
};
};
port@3 {
reg = <2>;
acpu_funnel_in2: endpoint {
slave-mode;
remote-endpoint =
<&etm2_out>;
};
};
port@4 {
reg = <3>;
acpu_funnel_in3: endpoint {
slave-mode;
remote-endpoint =
<&etm3_out>;
};
};
port@5 {
reg = <4>;
acpu_funnel_in4: endpoint {
slave-mode;
remote-endpoint =
<&etm4_out>;
};
};
port@6 {
reg = <5>;
acpu_funnel_in5: endpoint {
slave-mode;
remote-endpoint =
<&etm5_out>;
};
};
port@7 {
reg = <6>;
acpu_funnel_in6: endpoint {
slave-mode;
remote-endpoint =
<&etm6_out>;
};
};
port@8 {
reg = <7>;
acpu_funnel_in7: endpoint {
slave-mode;
remote-endpoint =
<&etm7_out>;
};
};
};
};
etm@f659c000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf659c000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
port {
etm0_out: endpoint {
remote-endpoint =
<&acpu_funnel_in0>;
};
};
};
etm@f659d000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf659d000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu1>;
port {
etm1_out: endpoint {
remote-endpoint =
<&acpu_funnel_in1>;
};
};
};
etm@f659e000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf659e000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu2>;
port {
etm2_out: endpoint {
remote-endpoint =
<&acpu_funnel_in2>;
};
};
};
etm@f659f000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf659f000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu3>;
port {
etm3_out: endpoint {
remote-endpoint =
<&acpu_funnel_in3>;
};
};
};
etm@f65dc000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf65dc000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu4>;
port {
etm4_out: endpoint {
remote-endpoint =
<&acpu_funnel_in4>;
};
};
};
etm@f65dd000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf65dd000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu5>;
port {
etm5_out: endpoint {
remote-endpoint =
<&acpu_funnel_in5>;
};
};
};
etm@f65de000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf65de000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu6>;
port {
etm6_out: endpoint {
remote-endpoint =
<&acpu_funnel_in6>;
};
};
};
etm@f65df000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0xf65df000 0 0x1000>;
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
cpu = <&cpu7>;
port {
etm7_out: endpoint {
remote-endpoint =
<&acpu_funnel_in7>;
};
};
};
};
};

2
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View file

@ -987,3 +987,5 @@
};
};
};
#include "hi6220-coresight.dtsi"

2
arch/arm64/boot/dts/hisilicon/hip05-d02.dts
View file

@ -18,7 +18,7 @@
model = "Hisilicon Hip05 D02 Development Board";
compatible = "hisilicon,hip05-d02";
memory@00000000 {
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
};

2
arch/arm64/boot/dts/hisilicon/hip06-d03.dts
View file

@ -17,7 +17,7 @@
model = "Hisilicon Hip06 D03 Development Board";
compatible = "hisilicon,hip06-d03";
memory@00000000 {
memory@0 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
};

20
arch/arm64/boot/dts/marvell/armada-3720-db.dts
View file

@ -94,6 +94,16 @@
3300000 0x0>;
enable-active-high;
};
vcc_sd_reg2: regulator-vmcc {
compatible = "regulator-fixed";
regulator-name = "vcc_sd2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
};
};
/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
@ -179,6 +189,7 @@
bus-width = <4>;
marvell,pad-type = "sd";
vqmmc-supply = <&vcc_sd_reg1>;
vmmc-supply = <&vcc_sd_reg2>;
status = "okay";
};
@ -216,7 +227,7 @@
/*
* Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through
* an FTDI
* an FTDI (also on CON24(V2.0)/CON26(V1.4)).
*/
&uart0 {
pinctrl-names = "default";
@ -224,6 +235,13 @@
status = "okay";
};
/* CON26(V2.0)/CON28(V1.4) */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
/* CON27(V2.0)/CON29(V1.4) */
&usb2 {
status = "okay";

12
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
View file

@ -98,9 +98,21 @@
/* Exported on the micro USB connector J5 through an FTDI */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
/*
* Connector J17 and J18 expose a number of different features. Some pins are
* multiplexed. This is the case for instance for the following features:
* - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
* how to enable it. Beware that the signals are 1.8V TTL.
* - I2C
* - SPI
* - MMC
*/
/* J7 */
&usb3 {
status = "okay";

22
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View file

@ -55,6 +55,7 @@
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpus {
@ -134,8 +135,24 @@
uart0: serial@12000 {
compatible = "marvell,armada-3700-uart";
reg = <0x12000 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12000 0x200>;
clocks = <&xtalclk>;
interrupts =
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uart-sum", "uart-tx", "uart-rx";
status = "disabled";
};
uart1: serial@12200 {
compatible = "marvell,armada-3700-uart-ext";
reg = <0x12200 0x30>;
clocks = <&xtalclk>;
interrupts =
<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "uart-tx", "uart-rx";
status = "disabled";
};
@ -183,7 +200,6 @@
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
};
xtalclk: xtal-clk {

57
arch/arm64/boot/dts/marvell/armada-7040-db.dts
View file

@ -56,7 +56,7 @@
stdout-path = "serial0:115200n8";
};
memory@00000000 {
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
@ -124,6 +124,8 @@
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
@ -141,9 +143,49 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x21>;
/*
* IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect
* IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit
* IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
* IO0_3: USB2_DEVICE_DETECT
* IO0_4: GPIO_0 IO1_4: SD_Status
* IO0_5: GPIO_1 IO1_5: LDO_5V_Enable
* IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
* IO0_7: IO1_7: SDIO_Vcntrl
*/
};
};
&cpm_nand {
/*
* SPI on CPM and NAND have common pins on this board. We can
* use only one at a time. To enable the NAND (whihch will
* disable the SPI), the "status = "okay";" line have to be
* added here.
*/
num-cs = <1>;
pinctrl-0 = <&nand_pins>, <&nand_rb>;
pinctrl-names = "default";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
partition@0 {
label = "U-Boot";
reg = <0 0x200000>;
};
partition@200000 {
label = "Linux";
reg = <0x200000 0xe00000>;
};
partition@1000000 {
label = "Filesystem";
reg = <0x1000000 0x3f000000>;
};
};
&cpm_spi1 {
status = "okay";
@ -197,7 +239,7 @@
status = "okay";
bus-width = <4>;
no-1-8-v;
non-removable;
cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
};
&cpm_mdio {
@ -215,10 +257,21 @@
status = "okay";
};
&cpm_eth0 {
status = "okay";
/* Network PHY */
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy2 0>;
};
&cpm_eth1 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy0 1>;
};
&cpm_eth2 {

14
arch/arm64/boot/dts/marvell/armada-70x0.dtsi
View file

@ -64,5 +64,19 @@
&cpm_syscon0 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
nand_pins: nand-pins {
marvell,pins =
"mpp15", "mpp16", "mpp17", "mpp18",
"mpp19", "mpp20", "mpp21", "mpp22",
"mpp23", "mpp24", "mpp25", "mpp26",
"mpp27";
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp13";
marvell,function = "nf";
};
};
};

59
arch/arm64/boot/dts/marvell/armada-8040-db.dts
View file

@ -56,7 +56,7 @@
stdout-path = "serial0:115200n8";
};
memory@00000000 {
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
@ -139,8 +139,14 @@
/* Accessible over the mini-USB CON9 connector on the main board */
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
/* CON6 on CP0 expansion */
&cpm_pcie0 {
status = "okay";
};
/* CON5 on CP0 expansion */
&cpm_pcie2 {
@ -200,12 +206,27 @@
status = "okay";
};
&cpm_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
&cpm_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
/* CON6 on CP1 expansion */
&cps_pcie0 {
status = "okay";
};
/* CON7 on CP1 expansion */
&cps_pcie1 {
status = "okay";
};
/* CON5 on CP1 expansion */
&cps_pcie2 {
status = "okay";
@ -216,6 +237,37 @@
clock-frequency = <100000>;
};
&cps_spi1 {
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <20000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Boot";
reg = <0x0 0x200000>;
};
partition@200000 {
label = "Filesystem";
reg = <0x200000 0xd00000>;
};
partition@f00000 {
label = "Boot_2nd";
reg = <0xf00000 0x100000>;
};
};
};
};
/* CON4 on CP1 expansion */
&cps_sata0 {
status = "okay";
@ -244,6 +296,11 @@
status = "okay";
};
&cps_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
&cps_eth1 {
status = "okay";
phy = <&phy0>;

13
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
View file

@ -57,7 +57,7 @@
stdout-path = "serial0:115200n8";
};
memory@00000000 {
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
@ -101,6 +101,8 @@
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
&ap_sdhci0 {
@ -222,8 +224,11 @@
&cpm_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy4 0>;
};
&cpm_sata0 {
@ -257,15 +262,21 @@
&cps_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy8>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cps_comphy4 0>;
};
&cps_eth1 {
/* CPS Lane 0 - J5 (Gigabit RJ45) */
status = "okay";
/* Network PHY */
phy = <&ge_phy>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
phys = <&cps_comphy0 1>;
};
&cps_pinctrl {

2
arch/arm64/boot/dts/marvell/armada-8080-db.dts
View file

@ -55,7 +55,7 @@
stdout-path = "serial0:115200n8";
};
memory@00000000 {
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};

4
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
View file

@ -54,13 +54,13 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@000 {
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x000>;
enable-method = "psci";
};
cpu@001 {
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x001>;

4
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
View file

@ -54,13 +54,13 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@000 {
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x000>;
enable-method = "psci";
};
cpu@001 {
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x001>;

11
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View file

@ -241,6 +241,12 @@
};
watchdog: watchdog@600000 {
compatible = "arm,sbsa-gwdt";
reg = <0x610000 0x1000>, <0x600000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
ap_sdhci0: sdhci@6e0000 {
compatible = "marvell,armada-ap806-sdhci";
reg = <0x6e0000 0x300>;
@ -263,6 +269,11 @@
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
uart0_pins: uart0-pins {
marvell,pins = "mpp11", "mpp19";
marvell,function = "uart0";
};
};
ap_gpio: gpio@1040 {

4
arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
View file

@ -52,13 +52,13 @@
#size-cells = <0>;
compatible = "marvell,armada-ap810-octa";
cpu@000 {
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x000>;
enable-method = "psci";
};
cpu@001 {
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x001>;

59
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
View file

@ -74,9 +74,10 @@
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
@ -87,9 +88,10 @@
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
@ -100,15 +102,54 @@
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
};
};
cpm_comphy: phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&cpm_syscon0>;
#address-cells = <1>;
#size-cells = <0>;
cpm_comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
cpm_comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
cpm_comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
cpm_comphy3: phy@3 {
reg = <3>;
#phy-cells = <1>;
};
cpm_comphy4: phy@4 {
reg = <4>;
#phy-cells = <1>;
};
cpm_comphy5: phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
cpm_mdio: mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
@ -143,7 +184,7 @@
cpm_syscon0: system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
reg = <0x440000 0x2000>;
cpm_clk: clock {
compatible = "marvell,cp110-clock";
@ -274,12 +315,14 @@
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
compatible = "marvell,armada370-nand";
compatible = "marvell,armada-8k-nand",
"marvell,armada370-nand";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 2>;
marvell,system-controller = <&cpm_syscon0>;
status = "disabled";
};

58
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
View file

@ -74,9 +74,10 @@
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
@ -87,9 +88,10 @@
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
@ -100,15 +102,54 @@
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
};
};
cps_comphy: phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&cps_syscon0>;
#address-cells = <1>;
#size-cells = <0>;
cps_comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
cps_comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
cps_comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
cps_comphy3: phy@3 {
reg = <3>;
#phy-cells = <1>;
};
cps_comphy4: phy@4 {
reg = <4>;
#phy-cells = <1>;
};
cps_comphy5: phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
cps_mdio: mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
@ -143,7 +184,7 @@
cps_syscon0: system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
reg = <0x440000 0x2000>;
cps_clk: clock {
compatible = "marvell,cp110-clock";
@ -275,7 +316,8 @@
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
compatible = "marvell,armada370-nand";
compatible = "marvell,armada370-nand",
"marvell,armada370-nand";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <1>;

6
arch/arm64/boot/dts/marvell/berlin4ct.dtsi
View file

@ -167,7 +167,7 @@
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
gpio0: gpio@0400 {
gpio0: gpio@400 {
compatible = "snps,dw-apb-gpio";
reg = <0x0400 0x400>;
#address-cells = <1>;
@ -185,7 +185,7 @@
};
};
gpio1: gpio@0800 {
gpio1: gpio@800 {
compatible = "snps,dw-apb-gpio";
reg = <0x0800 0x400>;
#address-cells = <1>;
@ -203,7 +203,7 @@
};
};
gpio2: gpio@0c00 {
gpio2: gpio@c00 {
compatible = "snps,dw-apb-gpio";
reg = <0x0c00 0x400>;
#address-cells = <1>;

25
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View file

@ -39,6 +39,7 @@
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x000>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu1: cpu@1 {
@ -46,6 +47,7 @@
compatible = "arm,cortex-a35";
reg = <0x001>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu2: cpu@200 {
@ -53,6 +55,29 @@
compatible = "arm,cortex-a72";
reg = <0x200>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
entry-latency-us = <100>;
exit-latency-us = <80>;
min-residency-us = <2000>;
arm,psci-suspend-param = <0x0010000>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
entry-latency-us = <350>;
exit-latency-us = <80>;
min-residency-us = <3000>;
arm,psci-suspend-param = <0x1010000>;
};
};
};

24
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
View file

@ -50,6 +50,30 @@
vmmc-supply = <&vdd_sd>;
};
pcie@10003000 {
status = "okay";
dvdd-pex-supply = <&vdd_pex>;
hvdd-pex-pll-supply = <&vdd_1v8>;
hvdd-pex-supply = <&vdd_1v8>;
vddio-pexctl-aud-supply = <&vdd_1v8>;
pci@1,0 {
nvidia,num-lanes = <4>;
status = "okay";
};
pci@2,0 {
nvidia,num-lanes = <0>;
status = "disabled";
};
pci@3,0 {
nvidia,num-lanes = <1>;
status = "disabled";
};
};
gpio-keys {
compatible = "gpio-keys";

214
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View file

@ -5,6 +5,7 @@
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
/ {
compatible = "nvidia,tegra186";
@ -356,6 +357,116 @@
nvidia,bpmp = <&bpmp>;
};
pcie@10003000 {
compatible = "nvidia,tegra186-pcie";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
device_type = "pci";
reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
0x0 0x10003800 0x0 0x00000800 /* AFI registers */
0x0 0x40000000 0x0 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
clocks = <&bpmp TEGRA186_CLK_AFI>,
<&bpmp TEGRA186_CLK_PCIE>,
<&bpmp TEGRA186_CLK_PLLE>;
clock-names = "afi", "pex", "pll_e";
resets = <&bpmp TEGRA186_RESET_AFI>,
<&bpmp TEGRA186_RESET_PCIE>,
<&bpmp TEGRA186_RESET_PCIEXCLK>;
reset-names = "afi", "pex", "pcie_x";
status = "disabled";
pci@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <2>;
};
pci@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <1>;
};
pci@3,0 {
device_type = "pci";
assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
reg = <0x001800 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <1>;
};
};
host1x@13e00000 {
compatible = "nvidia,tegra186-host1x", "simple-bus";
reg = <0x0 0x13e00000 0x0 0x10000>,
<0x0 0x13e10000 0x0 0x10000>;
reg-names = "hypervisor", "vm";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_HOST1X>;
clock-names = "host1x";
resets = <&bpmp TEGRA186_RESET_HOST1X>;
reset-names = "host1x";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x15000000 0x0 0x15000000 0x01000000>;
vic@15340000 {
compatible = "nvidia,tegra186-vic";
reg = <0x15340000 0x40000>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_VIC>;
clock-names = "vic";
resets = <&bpmp TEGRA186_RESET_VIC>;
reset-names = "vic";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
};
};
gpu@17000000 {
compatible = "nvidia,gp10b";
reg = <0x0 0x17000000 0x0 0x1000000>,
@ -444,6 +555,7 @@
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
@ -452,6 +564,108 @@
#size-cells = <0>;
status = "disabled";
};
bpmp_thermal: thermal {
compatible = "nvidia,tegra186-bpmp-thermal";
#thermal-sensor-cells = <1>;
};
};
thermal-zones {
a57 {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors =
<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
trips {
critical {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
denver {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors =
<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
trips {
critical {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
gpu {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors =
<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
trips {
critical {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
pll {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors =
<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
trips {
critical {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
always_on {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors =
<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
trips {
critical {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
};
timer {

177
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View file

@ -19,6 +19,30 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/sound/apq8016-lpass.h>
/*
* GPIO name legend: proper name = the GPIO line is used as GPIO
* NC = not connected (pin out but not routed from the chip to
* anything the board)
* "[PER]" = pin is muxed for [peripheral] (not GPIO)
* LSEC = Low Speed External Connector
* HSEC = High Speed External Connector
*
* Line names are taken from the schematic "DragonBoard410c"
* dated monday, august 31, 2015. Page 5 in particular.
*
* For the lines routed to the external connectors the
* lines are named after the 96Boards CE Specification 1.0,
* Appendix "Expansion Connector Signal Description".
*
* When the 96Board naming of a line and the schematic name of
* the same line are in conflict, the 96Board specification
* takes precedence, which means that the external UART on the
* LSEC is named UART0 while the schematic and SoC names this
* UART3. This is only for the informational lines i.e. "[FOO]",
* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
* ones actually used for GPIO.
*/
/ {
aliases {
serial0 = &blsp1_uart2;
@ -47,6 +71,132 @@
};
soc {
pinctrl@1000000 {
gpio-line-names =
"[UART0_TX]", /* GPIO_0, LSEC pin 5 */
"[UART0_RX]", /* GPIO_1, LSEC pin 7 */
"[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */
"[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */
"[UART1_TX]", /* GPIO_4, LSEC pin 11 */
"[UART1_RX]", /* GPIO_5, LSEC pin 13 */
"[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */
"[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */
"[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */
"[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */
"[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */
"[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */
"GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */
"GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */
"[I2C3_SDA]", /* HSEC pin 38 */
"[I2C3_SCL]", /* HSEC pin 36 */
"[SPI0_MOSI]", /* LSEC pin 14 */
"[SPI0_MISO]", /* LSEC pin 10 */
"[SPI0_CS_N]", /* LSEC pin 12 */
"[SPI0_CLK]", /* LSEC pin 8 */
"HDMI_HPD_N", /* GPIO 20 */
"USR_LED_1_CTRL",
"[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */
"[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */
"GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */
"GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */
"[CSI0_MCLK]", /* HSEC pin 15 */
"[CSI1_MCLK]", /* HSEC pin 17 */
"GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */
"[I2C2_SDA]", /* HSEC pin 34 */
"[I2C2_SCL]", /* HSEC pin 32 */
"DSI2HDMI_INT_N",
"DSI_SW_SEL_APQ",
"GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */
"GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */
"GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */
"GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */
"FORCED_USB_BOOT",
"SD_CARD_DET_N",
"[WCSS_BT_SSBI]",
"[WCSS_WLAN_DATA_2]", /* GPIO 40 */
"[WCSS_WLAN_DATA_1]",
"[WCSS_WLAN_DATA_0]",
"[WCSS_WLAN_SET]",
"[WCSS_WLAN_CLK]",
"[WCSS_FM_SSBI]",
"[WCSS_FM_SDI]",
"[WCSS_BT_DAT_CTL]",
"[WCSS_BT_DAT_STB]",
"NC",
"NC", /* GPIO 50 */
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC", /* GPIO 60 */
"NC",
"NC",
"[CDC_PDM0_CLK]",
"[CDC_PDM0_SYNC]",
"[CDC_PDM0_TX0]",
"[CDC_PDM0_RX0]",
"[CDC_PDM0_RX1]",
"[CDC_PDM0_RX2]",
"GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */
"NC", /* GPIO 70 */
"NC",
"NC",
"NC",
"NC", /* GPIO 74 */
"NC",
"NC",
"NC",
"NC",
"NC",
"BOOT_CONFIG_0", /* GPIO 80 */
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_3",
"NC",
"NC",
"BOOT_CONFIG_5",
"NC",
"NC",
"NC",
"NC", /* GPIO 90 */
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC", /* GPIO 100 */
"NC",
"NC",
"NC",
"SSBI_GPS",
"NC",
"NC",
"KEY_VOLP_N",
"NC",
"NC",
"[LS_EXP_MI2S_WS]", /* GPIO 110 */
"NC",
"NC",
"[LS_EXP_MI2S_SCK]",
"[LS_EXP_MI2S_DATA0]",
"GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */
"NC",
"[DSI2HDMI_MI2S_WS]",
"[DSI2HDMI_MI2S_SCK]",
"[DSI2HDMI_MI2S_DATA0]",
"USR_LED_2_CTRL", /* GPIO 120 */
"SB_HS_ID";
};
dma@7884000 {
status = "okay";
};
@ -192,7 +342,7 @@
};
};
sdhci@07824000 {
sdhci@7824000 {
vmmc-supply = <&pm8916_l8>;
vqmmc-supply = <&pm8916_l5>;
@ -202,7 +352,7 @@
status = "okay";
};
sdhci@07864000 {
sdhci@7864000 {
vmmc-supply = <&pm8916_l11>;
vqmmc-supply = <&pm8916_l12>;
@ -232,7 +382,7 @@
};
};
lpass@07708000 {
lpass@7708000 {
status = "okay";
};
@ -329,6 +479,25 @@
};
};
spmi@200f000 {
pm8916@0 {
gpios@c000 {
gpio-line-names =
"USR_LED_3_CTRL",
"USR_LED_4_CTRL",
"USB_HUB_RESET_N_PM",
"USB_SW_SEL_PM";
};
mpps@a000 {
gpio-line-names =
"VDD_PX_BIAS",
"WLAN_LED_CTRL",
"BT_LED_CTRL",
"GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */
};
};
};
wcnss@a21b000 {
status = "okay";
};
@ -379,6 +548,8 @@
status = "okay";
clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
clock-names = "mclk";
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
};
&smd_rpm_regulators {

32
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
View file

@ -51,31 +51,31 @@
pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
};
i2c@07577000 {
i2c@7577000 {
/* On Low speed expansion */
label = "LS-I2C0";
status = "okay";
};
i2c@075b6000 {
i2c@75b6000 {
/* On Low speed expansion */
label = "LS-I2C1";
status = "okay";
};
spi@07575000 {
spi@7575000 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
i2c@075b5000 {
i2c@75b5000 {
/* On High speed expansion */
label = "HS-I2C2";
status = "okay";
};
spi@075ba000{
spi@75ba000{
/* On High speed expansion */
label = "HS-SPI1";
status = "okay";
@ -138,6 +138,22 @@
pinctrl-names = "default";
pinctrl-0 = <&usb2_vbus_det_gpio>;
};
agnoc@0 {
qcom,pcie@00600000 {
perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
};
qcom,pcie@00608000 {
status = "okay";
perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
};
qcom,pcie@00610000 {
status = "okay";
perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
};
};
};
@ -173,9 +189,15 @@
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
/**
* 1.8v required on LS expansion
* for mezzanine boards
*/
s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
s5 {
regulator-min-microvolt = <2150000>;

13
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file

@ -69,8 +69,11 @@
};
rmtfs@86700000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x86700000 0x0 0xe0000>;
no-map;
qcom,client-id = <1>;
};
rfsa@867e00000 {
@ -257,6 +260,8 @@
clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "core", "bus", "iface";
#reset-cells = <1>;
qcom,dload-mode = <&tcsr 0x6100>;
};
};
@ -495,7 +500,7 @@
status = "disabled";
};
lpass: lpass@07708000 {
lpass: lpass@7708000 {
status = "disabled";
compatible = "qcom,lpass-cpu-apq8016";
clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
@ -530,7 +535,7 @@
#sound-dai-cells = <1>;
};
sdhc_1: sdhci@07824000 {
sdhc_1: sdhci@7824000 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
reg-names = "hc_mem", "core_mem";
@ -547,7 +552,7 @@
status = "disabled";
};
sdhc_2: sdhci@07864000 {
sdhc_2: sdhci@7864000 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x07864900 0x11c>, <0x07864000 0x800>;
reg-names = "hc_mem", "core_mem";
@ -814,7 +819,7 @@
mdp: mdp@1a01000 {
compatible = "qcom,mdp5";
reg = <0x1a01000 0x90000>;
reg = <0x1a01000 0x89000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;

195
arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
View file

@ -300,4 +300,199 @@
drive-strength = <2>; /* 2 MA */
};
};
pcie0_clkreq_default: pcie0_clkreq_default {
mux {
pins = "gpio36";
function = "pci_e0";
};
config {
pins = "gpio36";
drive-strength = <2>;
bias-pull-up;
};
};
pcie0_perst_default: pcie0_perst_default {
mux {
pins = "gpio35";
function = "gpio";
};
config {
pins = "gpio35";
drive-strength = <2>;
bias-pull-down;
};
};
pcie0_wake_default: pcie0_wake_default {
mux {
pins = "gpio37";
function = "gpio";
};
config {
pins = "gpio37";
drive-strength = <2>;
bias-pull-up;
};
};
pcie0_clkreq_sleep: pcie0_clkreq_sleep {
mux {
pins = "gpio36";
function = "gpio";
};
config {
pins = "gpio36";
drive-strength = <2>;
bias-disable;
};
};
pcie0_wake_sleep: pcie0_wake_sleep {
mux {
pins = "gpio37";
function = "gpio";
};
config {
pins = "gpio37";
drive-strength = <2>;
bias-disable;
};
};
pcie1_clkreq_default: pcie1_clkreq_default {
mux {
pins = "gpio131";
function = "pci_e1";
};
config {
pins = "gpio131";
drive-strength = <2>;
bias-pull-up;
};
};
pcie1_perst_default: pcie1_perst_default {
mux {
pins = "gpio130";
function = "gpio";
};
config {
pins = "gpio130";
drive-strength = <2>;
bias-pull-down;
};
};
pcie1_wake_default: pcie1_wake_default {
mux {
pins = "gpio132";
function = "gpio";
};
config {
pins = "gpio132";
drive-strength = <2>;
bias-pull-down;
};
};
pcie1_clkreq_sleep: pcie1_clkreq_sleep {
mux {
pins = "gpio131";
function = "gpio";
};
config {
pins = "gpio131";
drive-strength = <2>;
bias-disable;
};
};
pcie1_wake_sleep: pcie1_wake_sleep {
mux {
pins = "gpio132";
function = "gpio";
};
config {
pins = "gpio132";
drive-strength = <2>;
bias-disable;
};
};
pcie2_clkreq_default: pcie2_clkreq_default {
mux {
pins = "gpio115";
function = "pci_e2";
};
config {
pins = "gpio115";
drive-strength = <2>;
bias-pull-up;
};
};
pcie2_perst_default: pcie2_perst_default {
mux {
pins = "gpio114";
function = "gpio";
};
config {
pins = "gpio114";
drive-strength = <2>;
bias-pull-down;
};
};
pcie2_wake_default: pcie2_wake_default {
mux {
pins = "gpio116";
function = "gpio";
};
config {
pins = "gpio116";
drive-strength = <2>;
bias-pull-down;
};
};
pcie2_clkreq_sleep: pcie2_clkreq_sleep {
mux {
pins = "gpio115";
function = "gpio";
};
config {
pins = "gpio115";
drive-strength = <2>;
bias-disable;
};
};
pcie2_wake_sleep: pcie2_wake_sleep {
mux {
pins = "gpio116";
function = "gpio";
};
config {
pins = "gpio116";
drive-strength = <2>;
bias-disable;
};
};
};

191
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file

@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8996";
@ -261,6 +262,8 @@
firmware {
scm {
compatible = "qcom,scm-msm8996";
qcom,dload-mode = <&tcsr 0x13000>;
};
};
@ -289,6 +292,11 @@
compatible = "qcom,rpm-msm8996";
qcom,glink-channels = "rpm_requests";
rpmcc: qcom,rpmcc {
compatible = "qcom,rpmcc-msm8996";
#clock-cells = <1>;
};
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
@ -358,6 +366,11 @@
reg = <0x740000 0x20000>;
};
tcsr: syscon@7a0000 {
compatible = "qcom,tcsr-msm8996", "syscon";
reg = <0x7a0000 0x18000>;
};
intc: interrupt-controller@9bc0000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
@ -395,7 +408,7 @@
#clock-cells = <1>;
};
blsp1_spi0: spi@07575000 {
blsp1_spi0: spi@7575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@ -410,7 +423,7 @@
status = "disabled";
};
blsp2_i2c0: i2c@075b5000 {
blsp2_i2c0: i2c@75b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 0>;
@ -441,7 +454,7 @@
status = "disabled";
};
blsp2_i2c1: i2c@075b6000 {
blsp2_i2c1: i2c@75b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 0>;
@ -466,7 +479,7 @@
status = "disabled";
};
blsp1_i2c2: i2c@07577000 {
blsp1_i2c2: i2c@7577000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 0>;
@ -481,7 +494,7 @@
status = "disabled";
};
blsp2_spi5: spi@075ba000{
blsp2_spi5: spi@75ba000{
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x075ba000 0x600>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
@ -522,7 +535,7 @@
#interrupt-cells = <2>;
};
timer@09840000 {
timer@9840000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
@ -819,6 +832,172 @@
phy-names = "usb2-phy", "usb3-phy";
};
};
agnoc@0 {
power-domains = <&gcc AGGRE0_NOC_GDSC>;
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pcie0: qcom,pcie@00600000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
status = "disabled";
power-domains = <&gcc PCIE0_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
reg = <0x00600000 0x2000>,
<0x0c000000 0xf1d>,
<0x0c000f20 0xa8>,
<0x0c100000 0x100000>;
reg-names = "parf", "dbi", "elbi","config";
phys = <&pciephy_0>;
phy-names = "pciephy";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
interrupts = <GIC_SPI 405 IRQ_TYPE_NONE>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
vdda-supply = <&pm8994_l28>;
linux,pci-domain = <0>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
};
pcie1: qcom,pcie@00608000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
power-domains = <&gcc PCIE1_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
status = "disabled";
reg = <0x00608000 0x2000>,
<0x0d000000 0xf1d>,
<0x0d000f20 0xa8>,
<0x0d100000 0x100000>;
reg-names = "parf", "dbi", "elbi","config";
phys = <&pciephy_1>;
phy-names = "pciephy";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
interrupts = <GIC_SPI 413 IRQ_TYPE_NONE>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
vdda-supply = <&pm8994_l28>;
linux,pci-domain = <1>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
};
pcie2: qcom,pcie@00610000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
power-domains = <&gcc PCIE2_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
status = "disabled";
reg = <0x00610000 0x2000>,
<0x0e000000 0xf1d>,
<0x0e000f20 0xa8>,
<0x0e100000 0x100000>;
reg-names = "parf", "dbi", "elbi","config";
phys = <&pciephy_2>;
phy-names = "pciephy";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
device_type = "pci";
interrupts = <GIC_SPI 421 IRQ_TYPE_NONE>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
vdda-supply = <&pm8994_l28>;
linux,pci-domain = <2>;
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
<&gcc GCC_PCIE_2_AUX_CLK>,
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
};
};
};
adsp-pil {

2
arch/arm64/boot/dts/realtek/Makefile
View file

@ -1 +1,3 @@
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb

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