From 5d1603cad2b63b9995c9f0f6aea06a3253069b7a Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 2 Jul 2020 23:12:39 +0530 Subject: [PATCH 1/2] clk: qcom: dispcc: Add support for dispcc driver Display clock controller for clients to be able to vote/devote on the clocks. Change-Id: I3e09282b06668ec87475425f8cecea6022e72aad Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-holi.c | 694 +++++++++++++++++++++++++++++++++ 3 files changed, 703 insertions(+) create mode 100644 drivers/clk/qcom/dispcc-holi.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 8e6b27219908..6b71a6cc777d 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -465,4 +465,12 @@ config SM_DEBUGCC_SHIMA Say Y if you want to support the debug clocks such as clock measurement functionality. +config SM_DISPCC_HOLI + tristate "HOLI Display Clock Controller" + select SM_GCC_HOLI + help + Support for the display clock controller on Qualcomm Technologies, + Inc. HOLI devices. + Say Y if you want to support display devices and functionality such as + splash screen. endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 666cf1426134..bac2b3271185 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SM_CAMCC_SHIMA) += camcc-shima.o obj-$(CONFIG_SM_DEBUGCC_SHIMA) += debugcc-shima.o +obj-$(CONFIG_SM_DISPCC_HOLI) += dispcc-holi.o obj-$(CONFIG_SM_DISPCC_SHIMA) += dispcc-shima.o obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o obj-$(CONFIG_SM_GCC_HOLI) += gcc-holi.o diff --git a/drivers/clk/qcom/dispcc-holi.c b/drivers/clk/qcom/dispcc-holi.c new file mode 100644 index 000000000000..913c888965ee --- /dev/null +++ b/drivers/clk/qcom/dispcc-holi.c @@ -0,0 +1,694 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "reset.h" +#include "vdd-level-holi.h" + +static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); + +enum { + P_BI_TCXO, + P_CORE_BI_PLL_TEST_SE, + P_DISP_CC_PLL0_OUT_EVEN, + P_DISP_CC_PLL0_OUT_MAIN, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_GCC_DISP_GPLL0_CLK, +}; + +static struct pll_vco fabia_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +/* 1120MHz */ +static const struct alpha_pll_config disp_cc_pll0_config = { + .l = 0x3A, + .cal_l = 0x32, + .alpha = 0x5555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002067, + .test_ctl_val = 0x40000000, + .test_ctl_hi_val = 0x00000002, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00004805, +}; + +static struct clk_alpha_pll disp_cc_pll0 = { + .offset = 0x0, + .vco_table = fabia_vco, + .num_vco = ARRAY_SIZE(fabia_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + .vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1600000000, + [VDD_NOMINAL] = 2000000000}, + }, + }, +}; + +static const struct parent_map disp_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_byteclk", .name = + "dsi0_phy_pll_out_byteclk" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_GCC_DISP_GPLL0_CLK, 4 }, + { P_DISP_CC_PLL0_OUT_EVEN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &disp_cc_pll0.clkr.hw }, + { .fw_name = "gcc_disp_gpll0_clk" }, + { .hw = &disp_cc_pll0.clkr.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GCC_DISP_GPLL0_CLK, 4 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "gcc_disp_gpll0_clk" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_dsiclk", .name = + "dsi0_phy_pll_out_dsiclk" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0), + F(75000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { + .cmd_rcgr = 0x115c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 37500000, + [VDD_NOMINAL] = 75000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { + .cmd_rcgr = 0x10c4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = 3, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_byte2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 187500000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 358000000}, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { + .cmd_rcgr = 0x10e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = 3, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { + F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0), + F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0), + F(373333333, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(448000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { + .cmd_rcgr = 0x107c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 200000000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 373333333, + [VDD_NOMINAL] = 448000000, + [VDD_HIGH] = 560000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { + .cmd_rcgr = 0x1064, + .mnd_width = 8, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = 3, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_pixel_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 300000000, + [VDD_LOW] = 525000000, + [VDD_LOW_L1] = 625000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { + .cmd_rcgr = 0x1094, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = 5, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 200000000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 373333333, + [VDD_NOMINAL] = 448000000, + [VDD_HIGH] = 560000000}, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { + .cmd_rcgr = 0x10ac, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, + .clkr.vdd_data = { + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { + .reg = 0x10dc, + .shift = 0, + .width = 2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_byte0_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk = { + .halt_reg = 0x104c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x104c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk = { + .halt_reg = 0x102c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x102c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk = { + .halt_reg = 0x1030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_intf_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk = { + .halt_reg = 0x1034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk = { + .halt_reg = 0x1010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk = { + .halt_reg = 0x1020, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_lut_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { + .halt_reg = 0x2004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x2004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk = { + .halt_reg = 0x100c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rot_clk = { + .halt_reg = 0x1018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_rot_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { + .halt_reg = 0x200c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x200c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rscc_ahb_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { + .halt_reg = 0x2008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rscc_vsync_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk = { + .halt_reg = 0x1028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_sleep_clk = { + .halt_reg = 0x5004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_xo_clk = { + .halt_reg = 0x5008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_xo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *disp_cc_holi_clocks[] = { + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, + [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, + [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, + [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] = &disp_cc_pll0.clkr, + [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, + [DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr, +}; + +static const struct qcom_reset_map disp_cc_holi_resets[] = { + [DISP_CC_MDSS_CORE_BCR] = { 0x1000 }, + [DISP_CC_MDSS_RSCC_BCR] = { 0x2000 }, +}; + +static const struct regmap_config disp_cc_holi_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static const struct qcom_cc_desc disp_cc_holi_desc = { + .config = &disp_cc_holi_regmap_config, + .clks = disp_cc_holi_clocks, + .num_clks = ARRAY_SIZE(disp_cc_holi_clocks), + .resets = disp_cc_holi_resets, + .num_resets = ARRAY_SIZE(disp_cc_holi_resets), +}; + +static const struct of_device_id disp_cc_holi_match_table[] = { + { .compatible = "qcom,holi-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_holi_match_table); + +static int disp_cc_holi_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); + if (IS_ERR(vdd_cx.regulator[0])) { + if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n"); + return PTR_ERR(vdd_cx.regulator[0]); + } + + regmap = qcom_cc_map(pdev, &disp_cc_holi_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); + + ret = qcom_cc_really_probe(pdev, &disp_cc_holi_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register DISP CC clocks\n"); + return ret; + } + + dev_info(&pdev->dev, "Registered DISP CC clocks\n"); + + return ret; +} + +static void disp_cc_holi_sync_state(struct device *dev) +{ + qcom_cc_sync_state(dev, &disp_cc_holi_desc); +} + +static struct platform_driver disp_cc_holi_driver = { + .probe = disp_cc_holi_probe, + .driver = { + .name = "disp_cc-holi", + .of_match_table = disp_cc_holi_match_table, + .sync_state = disp_cc_holi_sync_state, + }, +}; + +static int __init disp_cc_holi_init(void) +{ + return platform_driver_register(&disp_cc_holi_driver); +} +subsys_initcall(disp_cc_holi_init); + +static void __exit disp_cc_holi_exit(void) +{ + platform_driver_unregister(&disp_cc_holi_driver); +} +module_exit(disp_cc_holi_exit); + +MODULE_DESCRIPTION("QTI DISP_CC HOLI Driver"); +MODULE_LICENSE("GPL v2"); From 2c8b628f1894b40589e531699179e637b8959840 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 8 Jul 2020 11:18:47 +0530 Subject: [PATCH 2/2] clk: qcom: debugcc: Add support for Debugcc for HOLI Add support for clock measurement for Global clock and other clock controllers. Change-Id: I0598785ba4464450f654ee6ce8f0238af7fd553b Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/debugcc-holi.c | 636 ++++++++++++++++++++++++++++++++ 3 files changed, 646 insertions(+) create mode 100644 drivers/clk/qcom/debugcc-holi.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6b71a6cc777d..d902f6a1d9ab 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -473,4 +473,13 @@ config SM_DISPCC_HOLI Inc. HOLI devices. Say Y if you want to support display devices and functionality such as splash screen. + +config SM_DEBUGCC_HOLI + tristate "HOLI Debug Clock Controller" + depends on SM_GCC_HOLI + help + Support for the debug clock controller on Qualcomm Technologies, Inc. + HOLI devices. + Say Y if you want to support the debug clocks such as + clock measurement functionality. endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index bac2b3271185..356043e5e789 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SM_CAMCC_SHIMA) += camcc-shima.o +obj-$(CONFIG_SM_DEBUGCC_HOLI) += debugcc-holi.o obj-$(CONFIG_SM_DEBUGCC_SHIMA) += debugcc-shima.o obj-$(CONFIG_SM_DISPCC_HOLI) += dispcc-holi.o obj-$(CONFIG_SM_DISPCC_SHIMA) += dispcc-shima.o diff --git a/drivers/clk/qcom/debugcc-holi.c b/drivers/clk/qcom/debugcc-holi.c new file mode 100644 index 000000000000..85556f9de908 --- /dev/null +++ b/drivers/clk/qcom/debugcc-holi.c @@ -0,0 +1,636 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#define pr_fmt(fmt) "clk: %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-debug.h" +#include "common.h" + +static struct measure_clk_data debug_mux_priv = { + .ctl_reg = 0x62038, + .status_reg = 0x6203C, + .xo_div4_cbcr = 0x28008, +}; + +static const char *const cpu_cc_debug_mux_parent_names[] = { + "perfcl_clk", + "pwrcl_clk", +}; + +static int cpu_cc_debug_mux_sels[] = { + 0x1, /* perfcl_clk */ + 0x0, /* pwrcl_clk */ +}; + +static int apss_cc_debug_mux_pre_divs[] = { + 0x8, /* perfcl_clk */ + 0x8, /* pwrcl_clk */ +}; + +static struct clk_debug_mux cpu_cc_debug_mux = { + .priv = &debug_mux_priv, + .debug_offset = 0x0, + .post_div_offset = 0x0, + .cbcr_offset = U32_MAX, + .src_sel_mask = 0x3FF00, + .src_sel_shift = 8, + .post_div_mask = 0xF0000000, + .post_div_shift = 28, + .post_div_val = 1, + .mux_sels = cpu_cc_debug_mux_sels, + .pre_div_vals = apss_cc_debug_mux_pre_divs, + .hw.init = &(struct clk_init_data){ + .name = "cpu_cc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = cpu_cc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(cpu_cc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + + +static const char *const disp_cc_debug_mux_parent_names[] = { + "disp_cc_mdss_ahb_clk", + "disp_cc_mdss_byte0_clk", + "disp_cc_mdss_byte0_intf_clk", + "disp_cc_mdss_esc0_clk", + "disp_cc_mdss_mdp_clk", + "disp_cc_mdss_mdp_lut_clk", + "disp_cc_mdss_non_gdsc_ahb_clk", + "disp_cc_mdss_pclk0_clk", + "disp_cc_mdss_rot_clk", + "disp_cc_mdss_rscc_ahb_clk", + "disp_cc_mdss_rscc_vsync_clk", + "disp_cc_mdss_vsync_clk", + "disp_cc_sleep_clk", + "disp_cc_xo_clk", +}; + +static int disp_cc_debug_mux_sels[] = { + 0x14, /* disp_cc_mdss_ahb_clk */ + 0xC, /* disp_cc_mdss_byte0_clk */ + 0xD, /* disp_cc_mdss_byte0_intf_clk */ + 0xE, /* disp_cc_mdss_esc0_clk */ + 0x8, /* disp_cc_mdss_mdp_clk */ + 0xA, /* disp_cc_mdss_mdp_lut_clk */ + 0x15, /* disp_cc_mdss_non_gdsc_ahb_clk */ + 0x7, /* disp_cc_mdss_pclk0_clk */ + 0x9, /* disp_cc_mdss_rot_clk */ + 0x17, /* disp_cc_mdss_rscc_ahb_clk */ + 0x16, /* disp_cc_mdss_rscc_vsync_clk */ + 0xB, /* disp_cc_mdss_vsync_clk */ + 0x1D, /* disp_cc_sleep_clk */ + 0x1E, /* disp_cc_xo_clk */ +}; + +static struct clk_debug_mux disp_cc_debug_mux = { + .priv = &debug_mux_priv, + .debug_offset = 0x7000, + .post_div_offset = 0x3000, + .cbcr_offset = 0x3004, + .src_sel_mask = 0xFF, + .src_sel_shift = 0, + .post_div_mask = 0x3, + .post_div_shift = 0, + .post_div_val = 4, + .mux_sels = disp_cc_debug_mux_sels, + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = disp_cc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(disp_cc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const char *const gcc_debug_mux_parent_names[] = { + "cpu_cc_debug_mux", + "disp_cc_debug_mux", + "gcc_ahb2phy_csi_clk", + "gcc_ahb2phy_usb_clk", + "gcc_bimc_gpu_axi_clk", + "gcc_boot_rom_ahb_clk", + "gcc_cam_throttle_nrt_clk", + "gcc_cam_throttle_rt_clk", + "gcc_camera_ahb_clk", + "gcc_camera_xo_clk", + "gcc_camss_axi_clk", + "gcc_camss_camnoc_atb_clk", + "gcc_camss_camnoc_nts_xo_clk", + "gcc_camss_cci_0_clk", + "gcc_camss_cci_1_clk", + "gcc_camss_cphy_0_clk", + "gcc_camss_cphy_1_clk", + "gcc_camss_cphy_2_clk", + "gcc_camss_cphy_3_clk", + "gcc_camss_csi0phytimer_clk", + "gcc_camss_csi1phytimer_clk", + "gcc_camss_csi2phytimer_clk", + "gcc_camss_mclk0_clk", + "gcc_camss_mclk1_clk", + "gcc_camss_mclk2_clk", + "gcc_camss_mclk3_clk", + "gcc_camss_nrt_axi_clk", + "gcc_camss_ope_ahb_clk", + "gcc_camss_ope_clk", + "gcc_camss_rt_axi_clk", + "gcc_camss_tfe_0_clk", + "gcc_camss_tfe_0_cphy_rx_clk", + "gcc_camss_tfe_0_csid_clk", + "gcc_camss_tfe_1_clk", + "gcc_camss_tfe_1_cphy_rx_clk", + "gcc_camss_tfe_1_csid_clk", + "gcc_camss_tfe_2_clk", + "gcc_camss_tfe_2_cphy_rx_clk", + "gcc_camss_tfe_2_csid_clk", + "gcc_camss_top_ahb_clk", + "gcc_cfg_noc_usb3_prim_axi_clk", + "gcc_cpuss_gnoc_clk", + "gcc_disp_ahb_clk", + "gcc_disp_gpll0_div_clk_src", + "gcc_disp_hf_axi_clk", + "gcc_disp_sleep_clk", + "gcc_disp_throttle_core_clk", + "gcc_disp_xo_clk", + "gcc_gp1_clk", + "gcc_gp2_clk", + "gcc_gp3_clk", + "gcc_gpu_cfg_ahb_clk", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src", + "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gcc_gpu_throttle_core_clk", + "gcc_pdm2_clk", + "gcc_pdm_ahb_clk", + "gcc_pdm_xo4_clk", + "gcc_prng_ahb_clk", + "gcc_qmip_camera_nrt_ahb_clk", + "gcc_qmip_camera_rt_ahb_clk", + "gcc_qmip_disp_ahb_clk", + "gcc_qmip_gpu_cfg_ahb_clk", + "gcc_qmip_video_vcodec_ahb_clk", + "gcc_qupv3_wrap0_core_2x_clk", + "gcc_qupv3_wrap0_core_clk", + "gcc_qupv3_wrap0_s0_clk", + "gcc_qupv3_wrap0_s1_clk", + "gcc_qupv3_wrap0_s2_clk", + "gcc_qupv3_wrap0_s3_clk", + "gcc_qupv3_wrap0_s4_clk", + "gcc_qupv3_wrap0_s5_clk", + "gcc_qupv3_wrap1_core_2x_clk", + "gcc_qupv3_wrap1_core_clk", + "gcc_qupv3_wrap1_s0_clk", + "gcc_qupv3_wrap1_s1_clk", + "gcc_qupv3_wrap1_s2_clk", + "gcc_qupv3_wrap1_s3_clk", + "gcc_qupv3_wrap1_s4_clk", + "gcc_qupv3_wrap1_s5_clk", + "gcc_qupv3_wrap_0_m_ahb_clk", + "gcc_qupv3_wrap_0_s_ahb_clk", + "gcc_qupv3_wrap_1_m_ahb_clk", + "gcc_qupv3_wrap_1_s_ahb_clk", + "gcc_sdcc1_ahb_clk", + "gcc_sdcc1_apps_clk", + "gcc_sdcc1_ice_core_clk", + "gcc_sdcc2_ahb_clk", + "gcc_sdcc2_apps_clk", + "gcc_sys_noc_cpuss_ahb_clk", + "gcc_sys_noc_ufs_phy_axi_clk", + "gcc_sys_noc_usb3_prim_axi_clk", + "gcc_ufs_phy_ahb_clk", + "gcc_ufs_phy_axi_clk", + "gcc_ufs_phy_ice_core_clk", + "gcc_ufs_phy_phy_aux_clk", + "gcc_ufs_phy_rx_symbol_0_clk", + "gcc_ufs_phy_tx_symbol_0_clk", + "gcc_ufs_phy_unipro_core_clk", + "gcc_usb30_prim_master_clk", + "gcc_usb30_prim_mock_utmi_clk", + "gcc_usb30_prim_sleep_clk", + "gcc_usb3_prim_phy_com_aux_clk", + "gcc_usb3_prim_phy_pipe_clk", + "gcc_vcodec0_axi_clk", + "gcc_venus_ahb_clk", + "gcc_venus_ctl_axi_clk", + "gcc_video_ahb_clk", + "gcc_video_axi0_clk", + "gcc_video_throttle_core_clk", + "gcc_video_vcodec0_sys_clk", + "gcc_video_venus_ctl_clk", + "gcc_video_xo_clk", + "gpu_cc_debug_mux", + "mc_cc_debug_mux", + "measure_only_cnoc_clk", + "measure_only_ipa_2x_clk", + "measure_only_snoc_clk", + "measure_only_hwkm_km_core_clk", + "measure_only_hwkm_ahb_clk", + "measure_only_pka_core_clk", + "measure_only_pka_ahb_clk", +}; + +static int gcc_debug_mux_sels[] = { + 0xBA, /* cpu_cc_debug_mux */ + 0x41, /* disp_cc_debug_mux */ + 0x63, /* gcc_ahb2phy_csi_clk */ + 0x64, /* gcc_ahb2phy_usb_clk */ + 0x99, /* gcc_bimc_gpu_axi_clk */ + 0x80, /* gcc_boot_rom_ahb_clk */ + 0x4B, /* gcc_cam_throttle_nrt_clk */ + 0x4A, /* gcc_cam_throttle_rt_clk */ + 0x36, /* gcc_camera_ahb_clk */ + 0x3E, /* gcc_camera_xo_clk */ + 0x14F, /* gcc_camss_axi_clk */ + 0x151, /* gcc_camss_camnoc_atb_clk */ + 0x152, /* gcc_camss_camnoc_nts_xo_clk */ + 0x14C, /* gcc_camss_cci_0_clk */ + 0x14D, /* gcc_camss_cci_1_clk */ + 0x13B, /* gcc_camss_cphy_0_clk */ + 0x13C, /* gcc_camss_cphy_1_clk */ + 0x13D, /* gcc_camss_cphy_2_clk */ + 0x13E, /* gcc_camss_cphy_3_clk */ + 0x12B, /* gcc_camss_csi0phytimer_clk */ + 0x12C, /* gcc_camss_csi1phytimer_clk */ + 0x12D, /* gcc_camss_csi2phytimer_clk */ + 0x12F, /* gcc_camss_mclk0_clk */ + 0x130, /* gcc_camss_mclk1_clk */ + 0x131, /* gcc_camss_mclk2_clk */ + 0x132, /* gcc_camss_mclk3_clk */ + 0x153, /* gcc_camss_nrt_axi_clk */ + 0x14B, /* gcc_camss_ope_ahb_clk */ + 0x149, /* gcc_camss_ope_clk */ + 0x155, /* gcc_camss_rt_axi_clk */ + 0x134, /* gcc_camss_tfe_0_clk */ + 0x138, /* gcc_camss_tfe_0_cphy_rx_clk */ + 0x13F, /* gcc_camss_tfe_0_csid_clk */ + 0x135, /* gcc_camss_tfe_1_clk */ + 0x139, /* gcc_camss_tfe_1_cphy_rx_clk */ + 0x141, /* gcc_camss_tfe_1_csid_clk */ + 0x136, /* gcc_camss_tfe_2_clk */ + 0x13A, /* gcc_camss_tfe_2_cphy_rx_clk */ + 0x143, /* gcc_camss_tfe_2_csid_clk */ + 0x14E, /* gcc_camss_top_ahb_clk */ + 0x1E, /* gcc_cfg_noc_usb3_prim_axi_clk */ + 0xB5, /* gcc_cpuss_gnoc_clk */ + 0x37, /* gcc_disp_ahb_clk */ + 0x46, /* gcc_disp_gpll0_div_clk_src */ + 0x3C, /* gcc_disp_hf_axi_clk */ + 0x4C, /* gcc_disp_sleep_clk */ + 0x48, /* gcc_disp_throttle_core_clk */ + 0x3F, /* gcc_disp_xo_clk */ + 0xC5, /* gcc_gp1_clk */ + 0xC6, /* gcc_gp2_clk */ + 0xC7, /* gcc_gp3_clk */ + 0xF5, /* gcc_gpu_cfg_ahb_clk */ + 0xFB, /* gcc_gpu_gpll0_clk_src */ + 0xFC, /* gcc_gpu_gpll0_div_clk_src */ + 0xF8, /* gcc_gpu_memnoc_gfx_clk */ + 0xFA, /* gcc_gpu_snoc_dvm_gfx_clk */ + 0xFF, /* gcc_gpu_throttle_core_clk */ + 0x7D, /* gcc_pdm2_clk */ + 0x7B, /* gcc_pdm_ahb_clk */ + 0x7C, /* gcc_pdm_xo4_clk */ + 0x7E, /* gcc_prng_ahb_clk */ + 0x39, /* gcc_qmip_camera_nrt_ahb_clk */ + 0x47, /* gcc_qmip_camera_rt_ahb_clk */ + 0x3A, /* gcc_qmip_disp_ahb_clk */ + 0xFD, /* gcc_qmip_gpu_cfg_ahb_clk */ + 0x38, /* gcc_qmip_video_vcodec_ahb_clk */ + 0x6A, /* gcc_qupv3_wrap0_core_2x_clk */ + 0x69, /* gcc_qupv3_wrap0_core_clk */ + 0x6B, /* gcc_qupv3_wrap0_s0_clk */ + 0x6C, /* gcc_qupv3_wrap0_s1_clk */ + 0x6D, /* gcc_qupv3_wrap0_s2_clk */ + 0x6E, /* gcc_qupv3_wrap0_s3_clk */ + 0x6F, /* gcc_qupv3_wrap0_s4_clk */ + 0x70, /* gcc_qupv3_wrap0_s5_clk */ + 0x74, /* gcc_qupv3_wrap1_core_2x_clk */ + 0x73, /* gcc_qupv3_wrap1_core_clk */ + 0x75, /* gcc_qupv3_wrap1_s0_clk */ + 0x76, /* gcc_qupv3_wrap1_s1_clk */ + 0x77, /* gcc_qupv3_wrap1_s2_clk */ + 0x78, /* gcc_qupv3_wrap1_s3_clk */ + 0x79, /* gcc_qupv3_wrap1_s4_clk */ + 0x7A, /* gcc_qupv3_wrap1_s5_clk */ + 0x67, /* gcc_qupv3_wrap_0_m_ahb_clk */ + 0x68, /* gcc_qupv3_wrap_0_s_ahb_clk */ + 0x71, /* gcc_qupv3_wrap_1_m_ahb_clk */ + 0x72, /* gcc_qupv3_wrap_1_s_ahb_clk */ + 0x103, /* gcc_sdcc1_ahb_clk */ + 0x102, /* gcc_sdcc1_apps_clk */ + 0x104, /* gcc_sdcc1_ice_core_clk */ + 0x66, /* gcc_sdcc2_ahb_clk */ + 0x65, /* gcc_sdcc2_apps_clk */ + 0x9, /* gcc_sys_noc_cpuss_ahb_clk */ + 0x1B, /* gcc_sys_noc_ufs_phy_axi_clk */ + 0x1A, /* gcc_sys_noc_usb3_prim_axi_clk */ + 0x122, /* gcc_ufs_phy_ahb_clk */ + 0x121, /* gcc_ufs_phy_axi_clk */ + 0x128, /* gcc_ufs_phy_ice_core_clk */ + 0x129, /* gcc_ufs_phy_phy_aux_clk */ + 0x124, /* gcc_ufs_phy_rx_symbol_0_clk */ + 0x123, /* gcc_ufs_phy_tx_symbol_0_clk */ + 0x127, /* gcc_ufs_phy_unipro_core_clk */ + 0x5C, /* gcc_usb30_prim_master_clk */ + 0x5E, /* gcc_usb30_prim_mock_utmi_clk */ + 0x5D, /* gcc_usb30_prim_sleep_clk */ + 0x5F, /* gcc_usb3_prim_phy_com_aux_clk */ + 0x60, /* gcc_usb3_prim_phy_pipe_clk */ + 0x15B, /* gcc_vcodec0_axi_clk */ + 0x15C, /* gcc_venus_ahb_clk */ + 0x15A, /* gcc_venus_ctl_axi_clk */ + 0x35, /* gcc_video_ahb_clk */ + 0x3B, /* gcc_video_axi0_clk */ + 0x49, /* gcc_video_throttle_core_clk */ + 0x158, /* gcc_video_vcodec0_sys_clk */ + 0x156, /* gcc_video_venus_ctl_clk */ + 0x3D, /* gcc_video_xo_clk */ + 0xF7, /* gpu_cc_debug_mux */ + 0xA9, /* mc_cc_debug_mux */ + 0x1C, /* measure_only_cnoc_clk */ + 0xD2, /* measure_only_ipa_2x_clk */ + 0x7, /* measure_only_snoc_clk */ + 0x162, /* measure_only_hwkm_km_core_clk */ + 0x161, /* measure_only_hwkm_ahb_clk */ + 0x15E, /* measure_only_pka_core_clk */ + 0x15D, /* measure_only_pka_ahb_clk */ +}; + +static struct clk_debug_mux gcc_debug_mux = { + .priv = &debug_mux_priv, + .debug_offset = 0x62000, + .post_div_offset = 0x30000, + .cbcr_offset = 0x30004, + .src_sel_mask = 0x3FF, + .src_sel_shift = 0, + .post_div_mask = 0xF, + .post_div_shift = 0, + .post_div_val = 1, + .mux_sels = gcc_debug_mux_sels, + .hw.init = &(struct clk_init_data){ + .name = "gcc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = gcc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(gcc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const char *const gpu_cc_debug_mux_parent_names[] = { + "gpu_cc_ahb_clk", + "gpu_cc_cx_gfx3d_clk", + "gpu_cc_cx_gfx3d_slv_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_cx_snoc_dvm_clk", + "gpu_cc_cxo_aon_clk", + "gpu_cc_cxo_clk", + "gpu_cc_gx_cxo_clk", + "gpu_cc_gx_gfx3d_clk", + "gpu_cc_gx_gmu_clk", + "gpu_cc_sleep_clk", +}; + +static int gpu_cc_debug_mux_sels[] = { + 0x11, /* gpu_cc_ahb_clk */ + 0x1A, /* gpu_cc_cx_gfx3d_clk */ + 0x1B, /* gpu_cc_cx_gfx3d_slv_clk */ + 0x19, /* gpu_cc_cx_gmu_clk */ + 0x16, /* gpu_cc_cx_snoc_dvm_clk */ + 0xB, /* gpu_cc_cxo_aon_clk */ + 0xA, /* gpu_cc_cxo_clk */ + 0xF, /* gpu_cc_gx_cxo_clk */ + 0xC, /* gpu_cc_gx_gfx3d_clk */ + 0x10, /* gpu_cc_gx_gmu_clk */ + 0x17, /* gpu_cc_sleep_clk */ +}; + +static struct clk_debug_mux gpu_cc_debug_mux = { + .priv = &debug_mux_priv, + .debug_offset = 0x1568, + .post_div_offset = 0x10FC, + .cbcr_offset = 0x1100, + .src_sel_mask = 0xFF, + .src_sel_shift = 0, + .post_div_mask = 0x3, + .post_div_shift = 0, + .post_div_val = 2, + .mux_sels = gpu_cc_debug_mux_sels, + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = gpu_cc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(gpu_cc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const char *const mc_cc_debug_mux_parent_names[] = { + "measure_only_mccc_clk", +}; + +static struct clk_debug_mux mc_cc_debug_mux = { + .period_offset = 0x20, + .hw.init = &(struct clk_init_data){ + .name = "mc_cc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = mc_cc_debug_mux_parent_names, + .num_parents = ARRAY_SIZE(mc_cc_debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static struct mux_regmap_names mux_list[] = { + { .mux = &cpu_cc_debug_mux, .regmap_name = "qcom,cpucc" }, + { .mux = &disp_cc_debug_mux, .regmap_name = "qcom,dispcc" }, + { .mux = &gcc_debug_mux, .regmap_name = "qcom,gcc" }, + { .mux = &gpu_cc_debug_mux, .regmap_name = "qcom,gpucc" }, + { .mux = &mc_cc_debug_mux, .regmap_name = "qcom,mccc" }, +}; + +static struct clk_dummy measure_only_mccc_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_mccc_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_cnoc_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_cnoc_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_ipa_2x_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_ipa_2x_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_snoc_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_snoc_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_hwkm_km_core_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_hwkm_km_core_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_hwkm_ahb_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_hwkm_ahb_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_pka_core_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_pka_core_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy measure_only_pka_ahb_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "measure_only_pka_ahb_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy perfcl_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "perfcl_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_dummy pwrcl_clk = { + .rrate = 1000, + .hw.init = &(struct clk_init_data){ + .name = "pwrcl_clk", + .ops = &clk_dummy_ops, + }, +}; + +struct clk_hw *debugcc_holi_hws[] = { + &measure_only_cnoc_clk.hw, + &measure_only_ipa_2x_clk.hw, + &measure_only_mccc_clk.hw, + &measure_only_snoc_clk.hw, + &measure_only_hwkm_km_core_clk.hw, + &measure_only_hwkm_ahb_clk.hw, + &measure_only_pka_core_clk.hw, + &measure_only_pka_ahb_clk.hw, + &perfcl_clk.hw, + &pwrcl_clk.hw, +}; + +static const struct of_device_id clk_debug_match_table[] = { + { .compatible = "qcom,holi-debugcc" }, + { } +}; + +static int clk_debug_holi_probe(struct platform_device *pdev) +{ + struct clk *clk; + int ret = 0, i; + + BUILD_BUG_ON(ARRAY_SIZE(disp_cc_debug_mux_parent_names) != + ARRAY_SIZE(disp_cc_debug_mux_sels)); + BUILD_BUG_ON(ARRAY_SIZE(gcc_debug_mux_parent_names) != + ARRAY_SIZE(gcc_debug_mux_sels)); + BUILD_BUG_ON(ARRAY_SIZE(gpu_cc_debug_mux_parent_names) != + ARRAY_SIZE(gpu_cc_debug_mux_sels)); + + clk = devm_clk_get(&pdev->dev, "xo_clk_src"); + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get xo clock\n"); + return PTR_ERR(clk); + } + + debug_mux_priv.cxo = clk; + + for (i = 0; i < ARRAY_SIZE(mux_list); i++) { + ret = map_debug_bases(pdev, mux_list[i].regmap_name, + mux_list[i].mux); + if (ret == -EBADR) + continue; + else if (ret) + return ret; + + clk = devm_clk_register(&pdev->dev, &mux_list[i].mux->hw); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n", + clk_hw_get_name(&mux_list[i].mux->hw), + PTR_ERR(clk)); + return PTR_ERR(clk); + } + } + + ret = clk_debug_measure_register(&gcc_debug_mux.hw); + if (ret) { + dev_err(&pdev->dev, "Could not register Measure clocks\n"); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(debugcc_holi_hws); i++) { + clk = devm_clk_register(&pdev->dev, debugcc_holi_hws[i]); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n", + clk_hw_get_name(debugcc_holi_hws[i]), + PTR_ERR(clk)); + return PTR_ERR(clk); + } + } + + dev_info(&pdev->dev, "Registered debug measure clocks\n"); + + return ret; +} + +static struct platform_driver clk_debug_driver = { + .probe = clk_debug_holi_probe, + .driver = { + .name = "holi-debugcc", + .of_match_table = clk_debug_match_table, + }, +}; + +static int __init clk_debug_holi_init(void) +{ + return platform_driver_register(&clk_debug_driver); +} +arch_initcall_sync(clk_debug_holi_init); + +MODULE_DESCRIPTION("QTI DEBUG CC HOLI Driver"); +MODULE_LICENSE("GPL v2");