From 52b8ab20bbec7252cac1afe4cf24a16d4a7ffd08 Mon Sep 17 00:00:00 2001
From: Shreyas K K <shrekk@qti.qualcomm.com>
Date: Wed, 6 Jan 2021 11:29:40 +0530
Subject: [PATCH] ARM: dts: msm: Add NPU-DDR devfreq nodes to SA8155

Add NPU-DDR device tree nodes for devfreq support on
target SA8155.

Change-Id: I95f71ec7bd77dc7935571f96a70fcec030f1ec15
---
 qcom/sm8150.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi
index fa02382e5424..37dec501ad8a 100644
--- a/qcom/sm8150.dtsi
+++ b/qcom/sm8150.dtsi
@@ -882,6 +882,25 @@
 		};
 	};
 
+	npu_npu_ddr_bw: qcom,npu-npu-ddr-bw {
+		compatible = "qcom,devfreq-icc-ddr";
+		governor = "performance";
+		interconnects = <&compute_noc MASTER_NPU &mc_virt SLAVE_EBI1>;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+		qcom,active-only;
+	};
+
+	npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 {
+		compatible = "qcom,bimc-bwmon4";
+		reg = <0x9960300 0x300>, <0x9960200 0x200>;
+		reg-names = "base", "global_base";
+		interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,mport = <0>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,target-dev = <&npu_npu_ddr_bw>;
+		qcom,count-unit = <0x10000>;
+	};
+
 	cpu_pmu: cpu-pmu {
 		compatible = "arm,armv8-pmuv3";
 		qcom,irq-is-percpu;