mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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[ARM] 4461/1: MXC platform and i.MX31ADS core support
This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen <[email protected]> Acked-by: Lennert Buytenhek <[email protected]> Signed-off-by: Russell King <[email protected]>
This commit is contained in:
Quinn Jensen
Russell King
parent
4b300c362d
commit
52c543f90c
26 changed files with 1563 additions and 2 deletions
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@ -324,6 +324,12 @@ config ARCH_NS9XXX
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<http://www.digi.com/products/microprocessors/index.jsp>
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config ARCH_MXC
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bool "Freescale MXC/iMX-based"
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select ARCH_MTD_XIP
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help
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Support for Freescale MXC/iMX-based family of processors
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config ARCH_PNX4008
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bool "Philips Nexperia PNX4008 Mobile"
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help
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@ -456,6 +462,8 @@ source "arch/arm/mach-realview/Kconfig"
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source "arch/arm/mach-at91/Kconfig"
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source "arch/arm/plat-mxc/Kconfig"
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source "arch/arm/mach-netx/Kconfig"
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source "arch/arm/mach-ns9xxx/Kconfig"
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@ -137,6 +137,8 @@ endif
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textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000
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machine-$(CONFIG_ARCH_DAVINCI) := davinci
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machine-$(CONFIG_ARCH_KS8695) := ks8695
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incdir-$(CONFIG_ARCH_MXC) := mxc
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machine-$(CONFIG_ARCH_MX3) := mx3
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ifeq ($(CONFIG_ARCH_EBSA110),y)
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# This is what happens if you forget the IOCS16 line.
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@ -183,6 +185,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/
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core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/
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core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/
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core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/
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core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/
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drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
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drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/
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12
arch/arm/mach-mx3/Kconfig
Normal file
12
arch/arm/mach-mx3/Kconfig
Normal file
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@ -0,0 +1,12 @@
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menu "MX3 Options"
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depends on ARCH_MX3
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config MACH_MX31ADS
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bool "Support MX31ADS platforms"
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default y
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help
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Include support for MX31ADS platform. This includes specific
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configurations for the board and its peripherals.
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endmenu
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8
arch/arm/mach-mx3/Makefile
Normal file
8
arch/arm/mach-mx3/Makefile
Normal file
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@ -0,0 +1,8 @@
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#
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# Makefile for the linux kernel.
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#
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# Object file lists.
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obj-y := mm.o time.o
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obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o
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3
arch/arm/mach-mx3/Makefile.boot
Normal file
3
arch/arm/mach-mx3/Makefile.boot
Normal file
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@ -0,0 +1,3 @@
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zreladdr-y := 0x80008000
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params_phys-y := 0x80000100
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initrd_phys-y := 0x80800000
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64
arch/arm/mach-mx3/mm.c
Normal file
64
arch/arm/mach-mx3/mm.c
Normal file
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@ -0,0 +1,64 @@
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/*
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* Copyright (C) 1999,2000 Arm Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* - add MX31 specific definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <asm/hardware.h>
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#include <asm/pgtable.h>
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#include <asm/mach/map.h>
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#include <asm/arch/common.h>
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/*!
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* @file mm.c
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*
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* @brief This file creates static virtual to physical mappings, common to all MX3 boards.
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*
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* @ingroup Memory
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*/
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/*!
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* This table defines static virtual address mappings for I/O regions.
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* These are the mappings common across all MX3 boards.
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*/
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static struct map_desc mxc_io_desc[] __initdata = {
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{
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.virtual = X_MEMC_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
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.length = X_MEMC_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = AVIC_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(AVIC_BASE_ADDR),
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.length = AVIC_SIZE,
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.type = MT_NONSHARED_DEVICE
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},
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};
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/*!
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* This function initializes the memory map. It is called during the
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* system startup to create static physical to virtual memory mappings
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* for the IO modules.
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*/
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void __init mxc_map_io(void)
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{
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iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
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}
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142
arch/arm/mach-mx3/mx31ads.c
Normal file
142
arch/arm/mach-mx3/mx31ads.c
Normal file
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@ -0,0 +1,142 @@
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/*
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/serial_8250.h>
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/memory.h>
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#include <asm/mach/map.h>
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#include <asm/arch/common.h>
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/*!
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* @file mx31ads.c
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*
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* @brief This file contains the board-specific initialization routines.
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*
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* @ingroup System
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*/
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#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
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/*!
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* The serial port definition structure.
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*/
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static struct plat_serial8250_port serial_platform_data[] = {
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{
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.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
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.mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA),
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.irq = EXPIO_INT_XUART_INTA,
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.uartclk = 14745600,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
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}, {
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.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
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.mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB),
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.irq = EXPIO_INT_XUART_INTB,
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.uartclk = 14745600,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
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},
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{},
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};
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static struct platform_device serial_device = {
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.name = "serial8250",
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.id = 0,
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.dev = {
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.platform_data = serial_platform_data,
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},
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};
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static int __init mxc_init_extuart(void)
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{
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return platform_device_register(&serial_device);
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}
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#else
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static inline int mxc_init_extuart(void)
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{
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return 0;
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}
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#endif
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/*!
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* This structure defines static mappings for the i.MX31ADS board.
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*/
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static struct map_desc mx31ads_io_desc[] __initdata = {
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{
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.virtual = AIPS1_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
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.length = AIPS1_SIZE,
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.type = MT_NONSHARED_DEVICE
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}, {
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.virtual = SPBA0_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
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.length = SPBA0_SIZE,
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.type = MT_NONSHARED_DEVICE
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}, {
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.virtual = AIPS2_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
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.length = AIPS2_SIZE,
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.type = MT_NONSHARED_DEVICE
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}, {
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.virtual = CS4_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(CS4_BASE_ADDR),
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.length = CS4_SIZE / 2,
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.type = MT_DEVICE
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},
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};
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/*!
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* Set up static virtual mappings.
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*/
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void __init mx31ads_map_io(void)
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{
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mxc_map_io();
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iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
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}
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/*!
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* Board specific initialization.
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*/
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static void __init mxc_board_init(void)
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{
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mxc_init_extuart();
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}
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/*
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* The following uses standard kernel macros defined in arch.h in order to
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* initialize __mach_desc_MX31ADS data structure.
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*/
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MACHINE_START(MX31ADS, "Freescale MX31ADS")
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/* Maintainer: Freescale Semiconductor, Inc. */
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.phys_io = AIPS1_BASE_ADDR,
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.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
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.boot_params = PHYS_OFFSET + 0x100,
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.map_io = mx31ads_map_io,
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.init_irq = mxc_init_irq,
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.init_machine = mxc_board_init,
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.timer = &mxc_timer,
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MACHINE_END
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152
arch/arm/mach-mx3/time.c
Normal file
152
arch/arm/mach-mx3/time.c
Normal file
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@ -0,0 +1,152 @@
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/*
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* System Timer Interrupt reconfigured to run in free-run mode.
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* Author: Vitaly Wool
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* Copyright 2004 MontaVista Software Inc.
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*!
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* @file time.c
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* @brief This file contains OS tick and wdog timer implementations.
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*
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* This file contains OS tick and wdog timer implementations.
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*
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* @ingroup Timers
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/hardware.h>
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#include <asm/mach/time.h>
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#include <asm/io.h>
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#include <asm/arch/common.h>
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/*!
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* This is the timer interrupt service routine to do required tasks.
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* It also services the WDOG timer at the frequency of twice per WDOG
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* timeout value. For example, if the WDOG's timeout value is 4 (2
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* seconds since the WDOG runs at 0.5Hz), it will be serviced once
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* every 2/2=1 second.
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*
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* @param irq GPT interrupt source number (not used)
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* @param dev_id this parameter is not used
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* @return always returns \b IRQ_HANDLED as defined in
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* include/linux/interrupt.h.
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*/
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static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
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{
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unsigned int next_match;
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write_seqlock(&xtime_lock);
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if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) {
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do {
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timer_tick();
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next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH;
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__raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
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__raw_writel(next_match, MXC_GPT_GPTOCR1);
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} while ((signed long)(next_match -
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__raw_readl(MXC_GPT_GPTCNT)) <= 0);
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}
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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/*!
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* This function is used to obtain the number of microseconds since the last
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* timer interrupt. Note that interrupts is disabled by do_gettimeofday().
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*
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* @return the number of microseconds since the last timer interrupt.
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*/
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static unsigned long mxc_gettimeoffset(void)
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{
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unsigned long ticks_to_match, elapsed, usec, tick_usec, i;
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/* Get ticks before next timer match */
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ticks_to_match =
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__raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT);
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/* We need elapsed ticks since last match */
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elapsed = LATCH - ticks_to_match;
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/* Now convert them to usec */
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/* Insure no overflow when calculating the usec below */
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for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) {
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tick_usec /= i;
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if ((0xFFFFFFFF / tick_usec) > elapsed)
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break;
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}
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usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i);
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return usec;
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}
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/*!
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* The OS tick timer interrupt structure.
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*/
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static struct irqaction timer_irq = {
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.name = "MXC Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = mxc_timer_interrupt
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};
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/*!
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* This function is used to initialize the GPT to produce an interrupt
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* based on HZ. It is called by start_kernel() during system startup.
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*/
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void __init mxc_init_time(void)
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{
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u32 reg, v;
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reg = __raw_readl(MXC_GPT_GPTCR);
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reg &= ~GPTCR_ENABLE;
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__raw_writel(reg, MXC_GPT_GPTCR);
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reg |= GPTCR_SWR;
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__raw_writel(reg, MXC_GPT_GPTCR);
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while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
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cpu_relax();
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reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ;
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__raw_writel(reg, MXC_GPT_GPTCR);
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/* TODO: get timer rate from clk driver */
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v = 66500000;
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__raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR);
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if ((v % CLOCK_TICK_RATE) != 0) {
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pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n",
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CLOCK_TICK_RATE);
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}
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pr_info("Actual CLOCK_TICK_RATE is %d Hz\n",
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v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1));
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reg = __raw_readl(MXC_GPT_GPTCNT);
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reg += LATCH;
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__raw_writel(reg, MXC_GPT_GPTOCR1);
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setup_irq(MXC_INT_GPT, &timer_irq);
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reg = __raw_readl(MXC_GPT_GPTCR);
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reg =
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GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN |
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GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE;
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__raw_writel(reg, MXC_GPT_GPTCR);
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__raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR);
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}
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struct sys_timer mxc_timer = {
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.init = mxc_init_time,
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.offset = mxc_gettimeoffset,
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};
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@ -345,7 +345,8 @@ config CPU_XSC3
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# ARMv6
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config CPU_V6
|
||||
bool "Support ARM V6 processor"
|
||||
depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
|
||||
depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3
|
||||
default y if ARCH_MX3
|
||||
select CPU_32v6
|
||||
select CPU_ABRT_EV6
|
||||
select CPU_CACHE_V6
|
||||
|
|
@ -359,7 +360,7 @@ config CPU_V6
|
|||
config CPU_32v6K
|
||||
bool "Support ARM V6K processor extensions" if !SMP
|
||||
depends on CPU_V6
|
||||
default y if SMP
|
||||
default y if SMP && !ARCH_MX3
|
||||
help
|
||||
Say Y here if your ARMv6 processor supports the 'K' extension.
|
||||
This enables the kernel to use some instructions not present
|
||||
|
|
|
|||
20
arch/arm/plat-mxc/Kconfig
Normal file
20
arch/arm/plat-mxc/Kconfig
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
if ARCH_MXC
|
||||
|
||||
menu "Freescale MXC Implementations"
|
||||
|
||||
choice
|
||||
prompt "MXC/iMX System Type"
|
||||
default 0
|
||||
|
||||
config ARCH_MX3
|
||||
bool "MX3-based"
|
||||
help
|
||||
This enables support for systems based on the Freescale i.MX3 family
|
||||
|
||||
endchoice
|
||||
|
||||
source "arch/arm/mach-mx3/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
10
arch/arm/plat-mxc/Makefile
Normal file
10
arch/arm/plat-mxc/Makefile
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
#
|
||||
# Makefile for the linux kernel.
|
||||
#
|
||||
|
||||
# Common support
|
||||
obj-y := irq.o
|
||||
|
||||
obj-m :=
|
||||
obj-n :=
|
||||
obj- :=
|
||||
83
arch/arm/plat-mxc/irq.c
Normal file
83
arch/arm/plat-mxc/irq.c
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/arch/common.h>
|
||||
|
||||
/*!
|
||||
* Disable interrupt number "irq" in the AVIC
|
||||
*
|
||||
* @param irq interrupt source number
|
||||
*/
|
||||
static void mxc_mask_irq(unsigned int irq)
|
||||
{
|
||||
__raw_writel(irq, AVIC_INTDISNUM);
|
||||
}
|
||||
|
||||
/*!
|
||||
* Enable interrupt number "irq" in the AVIC
|
||||
*
|
||||
* @param irq interrupt source number
|
||||
*/
|
||||
static void mxc_unmask_irq(unsigned int irq)
|
||||
{
|
||||
__raw_writel(irq, AVIC_INTENNUM);
|
||||
}
|
||||
|
||||
static struct irq_chip mxc_avic_chip = {
|
||||
.mask_ack = mxc_mask_irq,
|
||||
.mask = mxc_mask_irq,
|
||||
.unmask = mxc_unmask_irq,
|
||||
};
|
||||
|
||||
/*!
|
||||
* This function initializes the AVIC hardware and disables all the
|
||||
* interrupts. It registers the interrupt enable and disable functions
|
||||
* to the kernel for each interrupt source.
|
||||
*/
|
||||
void __init mxc_init_irq(void)
|
||||
{
|
||||
int i;
|
||||
u32 reg;
|
||||
|
||||
/* put the AVIC into the reset value with
|
||||
* all interrupts disabled
|
||||
*/
|
||||
__raw_writel(0, AVIC_INTCNTL);
|
||||
__raw_writel(0x1f, AVIC_NIMASK);
|
||||
|
||||
/* disable all interrupts */
|
||||
__raw_writel(0, AVIC_INTENABLEH);
|
||||
__raw_writel(0, AVIC_INTENABLEL);
|
||||
|
||||
/* all IRQ no FIQ */
|
||||
__raw_writel(0, AVIC_INTTYPEH);
|
||||
__raw_writel(0, AVIC_INTTYPEL);
|
||||
for (i = 0; i < MXC_MAX_INT_LINES; i++) {
|
||||
set_irq_chip(i, &mxc_avic_chip);
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID);
|
||||
}
|
||||
|
||||
/* Set WDOG2's interrupt the highest priority level (bit 28-31) */
|
||||
reg = __raw_readl(AVIC_NIPRIORITY6);
|
||||
reg |= (0xF << 28);
|
||||
__raw_writel(reg, AVIC_NIPRIORITY6);
|
||||
|
||||
printk(KERN_INFO "MXC IRQ initialized\n");
|
||||
}
|
||||
Loading…
Reference in a new issue