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msm: kgsl: Add support for A660 GPU variant

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Add A660 GPU variant support to deal with different
settings of A660 GPU.

Change-Id: I8dc4a5918777ca5ec2c6d14e5e26c603cd5e7390
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
This commit is contained in:
Deepak Kumar 2020-07-05 12:08:08 +05:30 • committed by Gerrit - the friendly Code Review server
commit 52c58461b7
4 changed files with 46 additions and 3 deletions
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30
drivers/gpu/msm/adreno-gpulist.h
View file

@ -1573,6 +1573,35 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660 = {
.pdc_in_aop = true,
};
static const struct adreno_a6xx_core adreno_gpu_core_a660_shima = {
.base = {
DEFINE_ADRENO_REV(ADRENO_REV_A660, 6, 6, 0, ANY_ID),
.compatible = "qcom,adreno-gpu-a660-shima",
.features = ADRENO_RPMH | ADRENO_GPMU | ADRENO_APRIV |
ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION,
.gpudev = &adreno_a6xx_gpudev,
.gmem_base = 0,
.gmem_size = SZ_1M + SZ_512K,
.bus_width = 32,
.snapshot_size = SZ_2M,
},
.prim_fifo_threshold = 0x00300000,
.gmu_major = 2,
.gmu_minor = 0,
.sqefw_name = "a660_sqe.fw",
.gmufw_name = "a660_gmu.bin",
.zap_name = "a660_zap",
.hwcg = a660_hwcg_regs,
.hwcg_count = ARRAY_SIZE(a660_hwcg_regs),
.vbif = a650_gbif_regs,
.vbif_count = ARRAY_SIZE(a650_gbif_regs),
.hang_detect_cycles = 0x3ffff,
.protected_regs = a660_protected_regs,
.disable_tseskip = true,
.highest_bank_bit = 15,
.pdc_in_aop = true,
};
static const struct adreno_gpu_core *adreno_gpulist[] = {
&adreno_gpu_core_a306.base,
&adreno_gpu_core_a306a.base,
@ -1606,4 +1635,5 @@ static const struct adreno_gpu_core *adreno_gpulist[] = {
&adreno_gpu_core_a612.base,
&adreno_gpu_core_a616.base,
&adreno_gpu_core_a610.base,
&adreno_gpu_core_a660_shima.base,
};

8
drivers/gpu/msm/adreno.h
View file

@ -1067,6 +1067,14 @@ static inline int adreno_is_a660v1(struct adreno_device *adreno_dev)
(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0);
}
static inline int adreno_is_a660_shima(struct adreno_device *adreno_dev)
{
return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A660) &&
(adreno_dev->gpucore->compatible &&
!strcmp(adreno_dev->gpucore->compatible,
"qcom,adreno-gpu-a660-shima"));
}
ADRENO_TARGET(a610, ADRENO_REV_A610)
ADRENO_TARGET(a612, ADRENO_REV_A612)
ADRENO_TARGET(a618, ADRENO_REV_A618)

10
drivers/gpu/msm/adreno_a6xx.c
View file

@ -127,9 +127,13 @@ int a6xx_init(struct adreno_device *adreno_dev)
adreno_dev->highest_bank_bit = a6xx_core->highest_bank_bit;
/* If the memory type is DDR 4, override the existing configuration */
if ((adreno_is_a650(adreno_dev) || adreno_is_a660(adreno_dev)) &&
of_fdt_get_ddrtype() == 0x7)
adreno_dev->highest_bank_bit = 15;
if (of_fdt_get_ddrtype() == 0x7) {
if (adreno_is_a660_shima(adreno_dev))
adreno_dev->highest_bank_bit = 14;
else if ((adreno_is_a650(adreno_dev) ||
adreno_is_a660(adreno_dev)))
adreno_dev->highest_bank_bit = 15;
}
a6xx_crashdump_init(adreno_dev);

1
drivers/gpu/msm/kgsl_iommu.c
View file

@ -2505,6 +2505,7 @@ static const char * const kgsl_iommu_clocks[] = {
"gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb",
"gpu_cc_hlos1_vote_gpu_smmu_clk",
};
static struct kgsl_mmu_ops kgsl_iommu_ops;