mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
[IA64] Cleanup of arch/ia64/sn and include/asm-ia64/sn
Replace uintX_t declarations with uX declarations. Replace intX_t declarations with sX declarations. Signed-off-by: Prarit Bhargava <[email protected]> Signed-off-by: Tony Luck <[email protected]>
This commit is contained in:
Prarit Bhargava
Tony Luck
parent
f15ac5801f
commit
53493dcf6e
25 changed files with 1758 additions and 1748 deletions
|
|
@ -40,7 +40,7 @@ struct sn_irq_info {
|
|||
int irq_cpuid; /* kernel logical cpuid */
|
||||
int irq_irq; /* the IRQ number */
|
||||
int irq_int_bit; /* Bridge interrupt pin */
|
||||
uint64_t irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
|
||||
u64 irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
|
||||
int irq_bridge_type;/* pciio asic type (pciio.h) */
|
||||
void *irq_bridge; /* bridge generating irq */
|
||||
void *irq_pciioinfo; /* associated pciio_info_t */
|
||||
|
|
|
|||
|
|
@ -44,9 +44,9 @@
|
|||
#define PCI32_MAPPED_BASE 0x40000000
|
||||
#define PCI32_DIRECT_BASE 0x80000000
|
||||
|
||||
#define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \
|
||||
(uint64_t)(x) >= PCI32_MAPPED_BASE)
|
||||
#define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE)
|
||||
#define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \
|
||||
(u64)(x) >= PCI32_MAPPED_BASE)
|
||||
#define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE)
|
||||
|
||||
|
||||
/*
|
||||
|
|
@ -63,7 +63,7 @@
|
|||
(IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
|
||||
|
||||
#define MINIMAL_ATE_FLAG(addr, size) \
|
||||
(MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0)
|
||||
(MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
|
||||
|
||||
/* bit 29 of the pci address is the SWAP bit */
|
||||
#define ATE_SWAPSHIFT 29
|
||||
|
|
@ -90,27 +90,27 @@
|
|||
* PMU resources.
|
||||
*/
|
||||
struct ate_resource{
|
||||
uint64_t *ate;
|
||||
uint64_t num_ate;
|
||||
uint64_t lowest_free_index;
|
||||
u64 *ate;
|
||||
u64 num_ate;
|
||||
u64 lowest_free_index;
|
||||
};
|
||||
|
||||
struct pcibus_info {
|
||||
struct pcibus_bussoft pbi_buscommon; /* common header */
|
||||
uint32_t pbi_moduleid;
|
||||
u32 pbi_moduleid;
|
||||
short pbi_bridge_type;
|
||||
short pbi_bridge_mode;
|
||||
|
||||
struct ate_resource pbi_int_ate_resource;
|
||||
uint64_t pbi_int_ate_size;
|
||||
u64 pbi_int_ate_size;
|
||||
|
||||
uint64_t pbi_dir_xbase;
|
||||
u64 pbi_dir_xbase;
|
||||
char pbi_hub_xid;
|
||||
|
||||
uint64_t pbi_devreg[8];
|
||||
u64 pbi_devreg[8];
|
||||
|
||||
uint32_t pbi_valid_devices;
|
||||
uint32_t pbi_enabled_devices;
|
||||
u32 pbi_valid_devices;
|
||||
u32 pbi_enabled_devices;
|
||||
|
||||
spinlock_t pbi_lock;
|
||||
};
|
||||
|
|
@ -136,22 +136,22 @@ extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
|
|||
/*
|
||||
* prototypes for the bridge asic register access routines in pcibr_reg.c
|
||||
*/
|
||||
extern void pcireg_control_bit_clr(struct pcibus_info *, uint64_t);
|
||||
extern void pcireg_control_bit_set(struct pcibus_info *, uint64_t);
|
||||
extern uint64_t pcireg_tflush_get(struct pcibus_info *);
|
||||
extern uint64_t pcireg_intr_status_get(struct pcibus_info *);
|
||||
extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t);
|
||||
extern void pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t);
|
||||
extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t);
|
||||
extern void pcireg_control_bit_clr(struct pcibus_info *, u64);
|
||||
extern void pcireg_control_bit_set(struct pcibus_info *, u64);
|
||||
extern u64 pcireg_tflush_get(struct pcibus_info *);
|
||||
extern u64 pcireg_intr_status_get(struct pcibus_info *);
|
||||
extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
|
||||
extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
|
||||
extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
|
||||
extern void pcireg_force_intr_set(struct pcibus_info *, int);
|
||||
extern uint64_t pcireg_wrb_flush_get(struct pcibus_info *, int);
|
||||
extern void pcireg_int_ate_set(struct pcibus_info *, int, uint64_t);
|
||||
extern uint64_t * pcireg_int_ate_addr(struct pcibus_info *, int);
|
||||
extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
|
||||
extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
|
||||
extern u64 * pcireg_int_ate_addr(struct pcibus_info *, int);
|
||||
extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
|
||||
extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
|
||||
extern int pcibr_ate_alloc(struct pcibus_info *, int);
|
||||
extern void pcibr_ate_free(struct pcibus_info *, int);
|
||||
extern void ate_write(struct pcibus_info *, int, int, uint64_t);
|
||||
extern void ate_write(struct pcibus_info *, int, int, u64);
|
||||
extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
|
||||
void *resp);
|
||||
extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
|
||||
|
|
|
|||
|
|
@ -29,13 +29,13 @@
|
|||
*/
|
||||
|
||||
struct pcibus_bussoft {
|
||||
uint32_t bs_asic_type; /* chipset type */
|
||||
uint32_t bs_xid; /* xwidget id */
|
||||
uint32_t bs_persist_busnum; /* Persistent Bus Number */
|
||||
uint32_t bs_persist_segment; /* Segment Number */
|
||||
uint64_t bs_legacy_io; /* legacy io pio addr */
|
||||
uint64_t bs_legacy_mem; /* legacy mem pio addr */
|
||||
uint64_t bs_base; /* widget base */
|
||||
u32 bs_asic_type; /* chipset type */
|
||||
u32 bs_xid; /* xwidget id */
|
||||
u32 bs_persist_busnum; /* Persistent Bus Number */
|
||||
u32 bs_persist_segment; /* Segment Number */
|
||||
u64 bs_legacy_io; /* legacy io pio addr */
|
||||
u64 bs_legacy_mem; /* legacy mem pio addr */
|
||||
u64 bs_base; /* widget base */
|
||||
struct xwidget_info *bs_xwidget_info;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -55,8 +55,8 @@ struct sn_pci_controller {
|
|||
#define PCIIO_VENDOR_ID_NONE (-1)
|
||||
|
||||
struct pcidev_info {
|
||||
uint64_t pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
|
||||
uint64_t pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
|
||||
u64 pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
|
||||
u64 pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
|
||||
|
||||
struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */
|
||||
struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */
|
||||
|
|
|
|||
|
|
@ -74,120 +74,120 @@ struct pic {
|
|||
/* 0x000000-0x00FFFF -- Local Registers */
|
||||
|
||||
/* 0x000000-0x000057 -- Standard Widget Configuration */
|
||||
uint64_t p_wid_id; /* 0x000000 */
|
||||
uint64_t p_wid_stat; /* 0x000008 */
|
||||
uint64_t p_wid_err_upper; /* 0x000010 */
|
||||
uint64_t p_wid_err_lower; /* 0x000018 */
|
||||
u64 p_wid_id; /* 0x000000 */
|
||||
u64 p_wid_stat; /* 0x000008 */
|
||||
u64 p_wid_err_upper; /* 0x000010 */
|
||||
u64 p_wid_err_lower; /* 0x000018 */
|
||||
#define p_wid_err p_wid_err_lower
|
||||
uint64_t p_wid_control; /* 0x000020 */
|
||||
uint64_t p_wid_req_timeout; /* 0x000028 */
|
||||
uint64_t p_wid_int_upper; /* 0x000030 */
|
||||
uint64_t p_wid_int_lower; /* 0x000038 */
|
||||
u64 p_wid_control; /* 0x000020 */
|
||||
u64 p_wid_req_timeout; /* 0x000028 */
|
||||
u64 p_wid_int_upper; /* 0x000030 */
|
||||
u64 p_wid_int_lower; /* 0x000038 */
|
||||
#define p_wid_int p_wid_int_lower
|
||||
uint64_t p_wid_err_cmdword; /* 0x000040 */
|
||||
uint64_t p_wid_llp; /* 0x000048 */
|
||||
uint64_t p_wid_tflush; /* 0x000050 */
|
||||
u64 p_wid_err_cmdword; /* 0x000040 */
|
||||
u64 p_wid_llp; /* 0x000048 */
|
||||
u64 p_wid_tflush; /* 0x000050 */
|
||||
|
||||
/* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
|
||||
uint64_t p_wid_aux_err; /* 0x000058 */
|
||||
uint64_t p_wid_resp_upper; /* 0x000060 */
|
||||
uint64_t p_wid_resp_lower; /* 0x000068 */
|
||||
u64 p_wid_aux_err; /* 0x000058 */
|
||||
u64 p_wid_resp_upper; /* 0x000060 */
|
||||
u64 p_wid_resp_lower; /* 0x000068 */
|
||||
#define p_wid_resp p_wid_resp_lower
|
||||
uint64_t p_wid_tst_pin_ctrl; /* 0x000070 */
|
||||
uint64_t p_wid_addr_lkerr; /* 0x000078 */
|
||||
u64 p_wid_tst_pin_ctrl; /* 0x000070 */
|
||||
u64 p_wid_addr_lkerr; /* 0x000078 */
|
||||
|
||||
/* 0x000080-0x00008F -- PMU & MAP */
|
||||
uint64_t p_dir_map; /* 0x000080 */
|
||||
uint64_t _pad_000088; /* 0x000088 */
|
||||
u64 p_dir_map; /* 0x000080 */
|
||||
u64 _pad_000088; /* 0x000088 */
|
||||
|
||||
/* 0x000090-0x00009F -- SSRAM */
|
||||
uint64_t p_map_fault; /* 0x000090 */
|
||||
uint64_t _pad_000098; /* 0x000098 */
|
||||
u64 p_map_fault; /* 0x000090 */
|
||||
u64 _pad_000098; /* 0x000098 */
|
||||
|
||||
/* 0x0000A0-0x0000AF -- Arbitration */
|
||||
uint64_t p_arb; /* 0x0000A0 */
|
||||
uint64_t _pad_0000A8; /* 0x0000A8 */
|
||||
u64 p_arb; /* 0x0000A0 */
|
||||
u64 _pad_0000A8; /* 0x0000A8 */
|
||||
|
||||
/* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
|
||||
uint64_t p_ate_parity_err; /* 0x0000B0 */
|
||||
uint64_t _pad_0000B8; /* 0x0000B8 */
|
||||
u64 p_ate_parity_err; /* 0x0000B0 */
|
||||
u64 _pad_0000B8; /* 0x0000B8 */
|
||||
|
||||
/* 0x0000C0-0x0000FF -- PCI/GIO */
|
||||
uint64_t p_bus_timeout; /* 0x0000C0 */
|
||||
uint64_t p_pci_cfg; /* 0x0000C8 */
|
||||
uint64_t p_pci_err_upper; /* 0x0000D0 */
|
||||
uint64_t p_pci_err_lower; /* 0x0000D8 */
|
||||
u64 p_bus_timeout; /* 0x0000C0 */
|
||||
u64 p_pci_cfg; /* 0x0000C8 */
|
||||
u64 p_pci_err_upper; /* 0x0000D0 */
|
||||
u64 p_pci_err_lower; /* 0x0000D8 */
|
||||
#define p_pci_err p_pci_err_lower
|
||||
uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */
|
||||
u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
|
||||
|
||||
/* 0x000100-0x0001FF -- Interrupt */
|
||||
uint64_t p_int_status; /* 0x000100 */
|
||||
uint64_t p_int_enable; /* 0x000108 */
|
||||
uint64_t p_int_rst_stat; /* 0x000110 */
|
||||
uint64_t p_int_mode; /* 0x000118 */
|
||||
uint64_t p_int_device; /* 0x000120 */
|
||||
uint64_t p_int_host_err; /* 0x000128 */
|
||||
uint64_t p_int_addr[8]; /* 0x0001{30,,,68} */
|
||||
uint64_t p_err_int_view; /* 0x000170 */
|
||||
uint64_t p_mult_int; /* 0x000178 */
|
||||
uint64_t p_force_always[8]; /* 0x0001{80,,,B8} */
|
||||
uint64_t p_force_pin[8]; /* 0x0001{C0,,,F8} */
|
||||
u64 p_int_status; /* 0x000100 */
|
||||
u64 p_int_enable; /* 0x000108 */
|
||||
u64 p_int_rst_stat; /* 0x000110 */
|
||||
u64 p_int_mode; /* 0x000118 */
|
||||
u64 p_int_device; /* 0x000120 */
|
||||
u64 p_int_host_err; /* 0x000128 */
|
||||
u64 p_int_addr[8]; /* 0x0001{30,,,68} */
|
||||
u64 p_err_int_view; /* 0x000170 */
|
||||
u64 p_mult_int; /* 0x000178 */
|
||||
u64 p_force_always[8]; /* 0x0001{80,,,B8} */
|
||||
u64 p_force_pin[8]; /* 0x0001{C0,,,F8} */
|
||||
|
||||
/* 0x000200-0x000298 -- Device */
|
||||
uint64_t p_device[4]; /* 0x0002{00,,,18} */
|
||||
uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */
|
||||
uint64_t p_wr_req_buf[4]; /* 0x0002{40,,,58} */
|
||||
uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */
|
||||
uint64_t p_rrb_map[2]; /* 0x0002{80,,,88} */
|
||||
u64 p_device[4]; /* 0x0002{00,,,18} */
|
||||
u64 _pad_000220[4]; /* 0x0002{20,,,38} */
|
||||
u64 p_wr_req_buf[4]; /* 0x0002{40,,,58} */
|
||||
u64 _pad_000260[4]; /* 0x0002{60,,,78} */
|
||||
u64 p_rrb_map[2]; /* 0x0002{80,,,88} */
|
||||
#define p_even_resp p_rrb_map[0] /* 0x000280 */
|
||||
#define p_odd_resp p_rrb_map[1] /* 0x000288 */
|
||||
uint64_t p_resp_status; /* 0x000290 */
|
||||
uint64_t p_resp_clear; /* 0x000298 */
|
||||
u64 p_resp_status; /* 0x000290 */
|
||||
u64 p_resp_clear; /* 0x000298 */
|
||||
|
||||
uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */
|
||||
u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
|
||||
|
||||
/* 0x000300-0x0003F8 -- Buffer Address Match Registers */
|
||||
struct {
|
||||
uint64_t upper; /* 0x0003{00,,,F0} */
|
||||
uint64_t lower; /* 0x0003{08,,,F8} */
|
||||
u64 upper; /* 0x0003{00,,,F0} */
|
||||
u64 lower; /* 0x0003{08,,,F8} */
|
||||
} p_buf_addr_match[16];
|
||||
|
||||
/* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
|
||||
struct {
|
||||
uint64_t flush_w_touch; /* 0x000{400,,,5C0} */
|
||||
uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */
|
||||
uint64_t inflight; /* 0x000{410,,,5D0} */
|
||||
uint64_t prefetch; /* 0x000{418,,,5D8} */
|
||||
uint64_t total_pci_retry; /* 0x000{420,,,5E0} */
|
||||
uint64_t max_pci_retry; /* 0x000{428,,,5E8} */
|
||||
uint64_t max_latency; /* 0x000{430,,,5F0} */
|
||||
uint64_t clear_all; /* 0x000{438,,,5F8} */
|
||||
u64 flush_w_touch; /* 0x000{400,,,5C0} */
|
||||
u64 flush_wo_touch; /* 0x000{408,,,5C8} */
|
||||
u64 inflight; /* 0x000{410,,,5D0} */
|
||||
u64 prefetch; /* 0x000{418,,,5D8} */
|
||||
u64 total_pci_retry; /* 0x000{420,,,5E0} */
|
||||
u64 max_pci_retry; /* 0x000{428,,,5E8} */
|
||||
u64 max_latency; /* 0x000{430,,,5F0} */
|
||||
u64 clear_all; /* 0x000{438,,,5F8} */
|
||||
} p_buf_count[8];
|
||||
|
||||
|
||||
/* 0x000600-0x0009FF -- PCI/X registers */
|
||||
uint64_t p_pcix_bus_err_addr; /* 0x000600 */
|
||||
uint64_t p_pcix_bus_err_attr; /* 0x000608 */
|
||||
uint64_t p_pcix_bus_err_data; /* 0x000610 */
|
||||
uint64_t p_pcix_pio_split_addr; /* 0x000618 */
|
||||
uint64_t p_pcix_pio_split_attr; /* 0x000620 */
|
||||
uint64_t p_pcix_dma_req_err_attr; /* 0x000628 */
|
||||
uint64_t p_pcix_dma_req_err_addr; /* 0x000630 */
|
||||
uint64_t p_pcix_timeout; /* 0x000638 */
|
||||
u64 p_pcix_bus_err_addr; /* 0x000600 */
|
||||
u64 p_pcix_bus_err_attr; /* 0x000608 */
|
||||
u64 p_pcix_bus_err_data; /* 0x000610 */
|
||||
u64 p_pcix_pio_split_addr; /* 0x000618 */
|
||||
u64 p_pcix_pio_split_attr; /* 0x000620 */
|
||||
u64 p_pcix_dma_req_err_attr; /* 0x000628 */
|
||||
u64 p_pcix_dma_req_err_addr; /* 0x000630 */
|
||||
u64 p_pcix_timeout; /* 0x000638 */
|
||||
|
||||
uint64_t _pad_000640[120]; /* 0x000{640,,,9F8} */
|
||||
u64 _pad_000640[120]; /* 0x000{640,,,9F8} */
|
||||
|
||||
/* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
|
||||
struct {
|
||||
uint64_t p_buf_addr; /* 0x000{A00,,,AF0} */
|
||||
uint64_t p_buf_attr; /* 0X000{A08,,,AF8} */
|
||||
u64 p_buf_addr; /* 0x000{A00,,,AF0} */
|
||||
u64 p_buf_attr; /* 0X000{A08,,,AF8} */
|
||||
} p_pcix_read_buf_64[16];
|
||||
|
||||
struct {
|
||||
uint64_t p_buf_addr; /* 0x000{B00,,,BE0} */
|
||||
uint64_t p_buf_attr; /* 0x000{B08,,,BE8} */
|
||||
uint64_t p_buf_valid; /* 0x000{B10,,,BF0} */
|
||||
uint64_t __pad1; /* 0x000{B18,,,BF8} */
|
||||
u64 p_buf_addr; /* 0x000{B00,,,BE0} */
|
||||
u64 p_buf_attr; /* 0x000{B08,,,BE8} */
|
||||
u64 p_buf_valid; /* 0x000{B10,,,BF0} */
|
||||
u64 __pad1; /* 0x000{B18,,,BF8} */
|
||||
} p_pcix_write_buf_64[8];
|
||||
|
||||
/* End of Local Registers -- Start of Address Map space */
|
||||
|
|
@ -195,45 +195,45 @@ struct pic {
|
|||
char _pad_000c00[0x010000 - 0x000c00];
|
||||
|
||||
/* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
|
||||
uint64_t p_int_ate_ram[1024]; /* 0x010000-0x011fff */
|
||||
u64 p_int_ate_ram[1024]; /* 0x010000-0x011fff */
|
||||
|
||||
/* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
|
||||
uint64_t p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
|
||||
u64 p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
|
||||
|
||||
char _pad_014000[0x18000 - 0x014000];
|
||||
|
||||
/* 0x18000-0x197F8 -- PIC Write Request Ram */
|
||||
uint64_t p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
|
||||
uint64_t p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
|
||||
uint64_t p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
|
||||
u64 p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
|
||||
u64 p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
|
||||
u64 p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
|
||||
|
||||
char _pad_019800[0x20000 - 0x019800];
|
||||
|
||||
/* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
|
||||
union {
|
||||
uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
|
||||
uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
|
||||
uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
|
||||
uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
|
||||
u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
|
||||
u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
|
||||
u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
|
||||
u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
|
||||
union {
|
||||
uint8_t c[0x100 / 1];
|
||||
uint16_t s[0x100 / 2];
|
||||
uint32_t l[0x100 / 4];
|
||||
uint64_t d[0x100 / 8];
|
||||
u8 c[0x100 / 1];
|
||||
u16 s[0x100 / 2];
|
||||
u32 l[0x100 / 4];
|
||||
u64 d[0x100 / 8];
|
||||
} f[8];
|
||||
} p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
|
||||
|
||||
/* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
|
||||
union {
|
||||
uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */
|
||||
uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */
|
||||
uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */
|
||||
uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */
|
||||
u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
|
||||
u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
|
||||
u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
|
||||
u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
|
||||
union {
|
||||
uint8_t c[0x100 / 1];
|
||||
uint16_t s[0x100 / 2];
|
||||
uint32_t l[0x100 / 4];
|
||||
uint64_t d[0x100 / 8];
|
||||
u8 c[0x100 / 1];
|
||||
u16 s[0x100 / 2];
|
||||
u32 l[0x100 / 4];
|
||||
u64 d[0x100 / 8];
|
||||
} f[8];
|
||||
} p_type1_cfg; /* 0x028000-0x029000 */
|
||||
|
||||
|
|
@ -241,20 +241,20 @@ struct pic {
|
|||
|
||||
/* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
|
||||
union {
|
||||
uint8_t c[8 / 1];
|
||||
uint16_t s[8 / 2];
|
||||
uint32_t l[8 / 4];
|
||||
uint64_t d[8 / 8];
|
||||
u8 c[8 / 1];
|
||||
u16 s[8 / 2];
|
||||
u32 l[8 / 4];
|
||||
u64 d[8 / 8];
|
||||
} p_pci_iack; /* 0x030000-0x030007 */
|
||||
|
||||
char _pad_030007[0x040000-0x030008];
|
||||
|
||||
/* 0x040000-0x030007 -- PCIX Special Cycle */
|
||||
union {
|
||||
uint8_t c[8 / 1];
|
||||
uint16_t s[8 / 2];
|
||||
uint32_t l[8 / 4];
|
||||
uint64_t d[8 / 8];
|
||||
u8 c[8 / 1];
|
||||
u16 s[8 / 2];
|
||||
u32 l[8 / 4];
|
||||
u64 d[8 / 8];
|
||||
} p_pcix_cycle; /* 0x040000-0x040007 */
|
||||
};
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -273,7 +273,7 @@ ia64_sn_console_putc(char ch)
|
|||
ret_stuff.v0 = 0;
|
||||
ret_stuff.v1 = 0;
|
||||
ret_stuff.v2 = 0;
|
||||
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (uint64_t)ch, 0, 0, 0, 0, 0, 0);
|
||||
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (u64)ch, 0, 0, 0, 0, 0, 0);
|
||||
|
||||
return ret_stuff.status;
|
||||
}
|
||||
|
|
@ -290,7 +290,7 @@ ia64_sn_console_putb(const char *buf, int len)
|
|||
ret_stuff.v0 = 0;
|
||||
ret_stuff.v1 = 0;
|
||||
ret_stuff.v2 = 0;
|
||||
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (uint64_t)buf, (uint64_t)len, 0, 0, 0, 0, 0);
|
||||
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (u64)buf, (u64)len, 0, 0, 0, 0, 0);
|
||||
|
||||
if ( ret_stuff.status == 0 ) {
|
||||
return ret_stuff.v0;
|
||||
|
|
@ -310,7 +310,7 @@ ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec)
|
|||
ret_stuff.v0 = 0;
|
||||
ret_stuff.v1 = 0;
|
||||
ret_stuff.v2 = 0;
|
||||
SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0);
|
||||
SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (u64)hook, (u64)rec, 0, 0, 0, 0, 0);
|
||||
|
||||
return ret_stuff.status;
|
||||
}
|
||||
|
|
@ -398,7 +398,7 @@ ia64_sn_console_intr_status(void)
|
|||
* Enable an interrupt on the SAL console device.
|
||||
*/
|
||||
static inline void
|
||||
ia64_sn_console_intr_enable(uint64_t intr)
|
||||
ia64_sn_console_intr_enable(u64 intr)
|
||||
{
|
||||
struct ia64_sal_retval ret_stuff;
|
||||
|
||||
|
|
@ -415,7 +415,7 @@ ia64_sn_console_intr_enable(uint64_t intr)
|
|||
* Disable an interrupt on the SAL console device.
|
||||
*/
|
||||
static inline void
|
||||
ia64_sn_console_intr_disable(uint64_t intr)
|
||||
ia64_sn_console_intr_disable(u64 intr)
|
||||
{
|
||||
struct ia64_sal_retval ret_stuff;
|
||||
|
||||
|
|
@ -441,7 +441,7 @@ ia64_sn_console_xmit_chars(char *buf, int len)
|
|||
ret_stuff.v1 = 0;
|
||||
ret_stuff.v2 = 0;
|
||||
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS,
|
||||
(uint64_t)buf, (uint64_t)len,
|
||||
(u64)buf, (u64)len,
|
||||
0, 0, 0, 0, 0);
|
||||
|
||||
if (ret_stuff.status == 0) {
|
||||
|
|
|
|||
|
|
@ -19,47 +19,47 @@
|
|||
*/
|
||||
|
||||
struct tioca {
|
||||
uint64_t ca_id; /* 0x000000 */
|
||||
uint64_t ca_control1; /* 0x000008 */
|
||||
uint64_t ca_control2; /* 0x000010 */
|
||||
uint64_t ca_status1; /* 0x000018 */
|
||||
uint64_t ca_status2; /* 0x000020 */
|
||||
uint64_t ca_gart_aperature; /* 0x000028 */
|
||||
uint64_t ca_gfx_detach; /* 0x000030 */
|
||||
uint64_t ca_inta_dest_addr; /* 0x000038 */
|
||||
uint64_t ca_intb_dest_addr; /* 0x000040 */
|
||||
uint64_t ca_err_int_dest_addr; /* 0x000048 */
|
||||
uint64_t ca_int_status; /* 0x000050 */
|
||||
uint64_t ca_int_status_alias; /* 0x000058 */
|
||||
uint64_t ca_mult_error; /* 0x000060 */
|
||||
uint64_t ca_mult_error_alias; /* 0x000068 */
|
||||
uint64_t ca_first_error; /* 0x000070 */
|
||||
uint64_t ca_int_mask; /* 0x000078 */
|
||||
uint64_t ca_crm_pkterr_type; /* 0x000080 */
|
||||
uint64_t ca_crm_pkterr_type_alias; /* 0x000088 */
|
||||
uint64_t ca_crm_ct_error_detail_1; /* 0x000090 */
|
||||
uint64_t ca_crm_ct_error_detail_2; /* 0x000098 */
|
||||
uint64_t ca_crm_tnumto; /* 0x0000A0 */
|
||||
uint64_t ca_gart_err; /* 0x0000A8 */
|
||||
uint64_t ca_pcierr_type; /* 0x0000B0 */
|
||||
uint64_t ca_pcierr_addr; /* 0x0000B8 */
|
||||
u64 ca_id; /* 0x000000 */
|
||||
u64 ca_control1; /* 0x000008 */
|
||||
u64 ca_control2; /* 0x000010 */
|
||||
u64 ca_status1; /* 0x000018 */
|
||||
u64 ca_status2; /* 0x000020 */
|
||||
u64 ca_gart_aperature; /* 0x000028 */
|
||||
u64 ca_gfx_detach; /* 0x000030 */
|
||||
u64 ca_inta_dest_addr; /* 0x000038 */
|
||||
u64 ca_intb_dest_addr; /* 0x000040 */
|
||||
u64 ca_err_int_dest_addr; /* 0x000048 */
|
||||
u64 ca_int_status; /* 0x000050 */
|
||||
u64 ca_int_status_alias; /* 0x000058 */
|
||||
u64 ca_mult_error; /* 0x000060 */
|
||||
u64 ca_mult_error_alias; /* 0x000068 */
|
||||
u64 ca_first_error; /* 0x000070 */
|
||||
u64 ca_int_mask; /* 0x000078 */
|
||||
u64 ca_crm_pkterr_type; /* 0x000080 */
|
||||
u64 ca_crm_pkterr_type_alias; /* 0x000088 */
|
||||
u64 ca_crm_ct_error_detail_1; /* 0x000090 */
|
||||
u64 ca_crm_ct_error_detail_2; /* 0x000098 */
|
||||
u64 ca_crm_tnumto; /* 0x0000A0 */
|
||||
u64 ca_gart_err; /* 0x0000A8 */
|
||||
u64 ca_pcierr_type; /* 0x0000B0 */
|
||||
u64 ca_pcierr_addr; /* 0x0000B8 */
|
||||
|
||||
uint64_t ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
|
||||
u64 ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
|
||||
|
||||
uint64_t ca_pci_rd_buf_flush; /* 0x0000D8 */
|
||||
uint64_t ca_pci_dma_addr_extn; /* 0x0000E0 */
|
||||
uint64_t ca_agp_dma_addr_extn; /* 0x0000E8 */
|
||||
uint64_t ca_force_inta; /* 0x0000F0 */
|
||||
uint64_t ca_force_intb; /* 0x0000F8 */
|
||||
uint64_t ca_debug_vector_sel; /* 0x000100 */
|
||||
uint64_t ca_debug_mux_core_sel; /* 0x000108 */
|
||||
uint64_t ca_debug_mux_pci_sel; /* 0x000110 */
|
||||
uint64_t ca_debug_domain_sel; /* 0x000118 */
|
||||
u64 ca_pci_rd_buf_flush; /* 0x0000D8 */
|
||||
u64 ca_pci_dma_addr_extn; /* 0x0000E0 */
|
||||
u64 ca_agp_dma_addr_extn; /* 0x0000E8 */
|
||||
u64 ca_force_inta; /* 0x0000F0 */
|
||||
u64 ca_force_intb; /* 0x0000F8 */
|
||||
u64 ca_debug_vector_sel; /* 0x000100 */
|
||||
u64 ca_debug_mux_core_sel; /* 0x000108 */
|
||||
u64 ca_debug_mux_pci_sel; /* 0x000110 */
|
||||
u64 ca_debug_domain_sel; /* 0x000118 */
|
||||
|
||||
uint64_t ca_pad_000120[28]; /* 0x0001{20..F8} */
|
||||
u64 ca_pad_000120[28]; /* 0x0001{20..F8} */
|
||||
|
||||
uint64_t ca_gart_ptr_table; /* 0x200 */
|
||||
uint64_t ca_gart_tlb_addr[8]; /* 0x2{08..40} */
|
||||
u64 ca_gart_ptr_table; /* 0x200 */
|
||||
u64 ca_gart_tlb_addr[8]; /* 0x2{08..40} */
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -56,31 +56,31 @@ struct tioca_kernel {
|
|||
/*
|
||||
* General GART stuff
|
||||
*/
|
||||
uint64_t ca_ap_size; /* size of aperature in bytes */
|
||||
uint32_t ca_gart_entries; /* # uint64_t entries in gart */
|
||||
uint32_t ca_ap_pagesize; /* aperature page size in bytes */
|
||||
uint64_t ca_ap_bus_base; /* bus address of CA aperature */
|
||||
uint64_t ca_gart_size; /* gart size in bytes */
|
||||
uint64_t *ca_gart; /* gart table vaddr */
|
||||
uint64_t ca_gart_coretalk_addr; /* gart coretalk addr */
|
||||
uint8_t ca_gart_iscoherent; /* used in tioca_tlbflush */
|
||||
u64 ca_ap_size; /* size of aperature in bytes */
|
||||
u32 ca_gart_entries; /* # u64 entries in gart */
|
||||
u32 ca_ap_pagesize; /* aperature page size in bytes */
|
||||
u64 ca_ap_bus_base; /* bus address of CA aperature */
|
||||
u64 ca_gart_size; /* gart size in bytes */
|
||||
u64 *ca_gart; /* gart table vaddr */
|
||||
u64 ca_gart_coretalk_addr; /* gart coretalk addr */
|
||||
u8 ca_gart_iscoherent; /* used in tioca_tlbflush */
|
||||
|
||||
/* PCI GART convenience values */
|
||||
uint64_t ca_pciap_base; /* pci aperature bus base address */
|
||||
uint64_t ca_pciap_size; /* pci aperature size (bytes) */
|
||||
uint64_t ca_pcigart_base; /* gfx GART bus base address */
|
||||
uint64_t *ca_pcigart; /* gfx GART vm address */
|
||||
uint32_t ca_pcigart_entries;
|
||||
uint32_t ca_pcigart_start; /* PCI start index in ca_gart */
|
||||
u64 ca_pciap_base; /* pci aperature bus base address */
|
||||
u64 ca_pciap_size; /* pci aperature size (bytes) */
|
||||
u64 ca_pcigart_base; /* gfx GART bus base address */
|
||||
u64 *ca_pcigart; /* gfx GART vm address */
|
||||
u32 ca_pcigart_entries;
|
||||
u32 ca_pcigart_start; /* PCI start index in ca_gart */
|
||||
void *ca_pcigart_pagemap;
|
||||
|
||||
/* AGP GART convenience values */
|
||||
uint64_t ca_gfxap_base; /* gfx aperature bus base address */
|
||||
uint64_t ca_gfxap_size; /* gfx aperature size (bytes) */
|
||||
uint64_t ca_gfxgart_base; /* gfx GART bus base address */
|
||||
uint64_t *ca_gfxgart; /* gfx GART vm address */
|
||||
uint32_t ca_gfxgart_entries;
|
||||
uint32_t ca_gfxgart_start; /* agpgart start index in ca_gart */
|
||||
u64 ca_gfxap_base; /* gfx aperature bus base address */
|
||||
u64 ca_gfxap_size; /* gfx aperature size (bytes) */
|
||||
u64 ca_gfxgart_base; /* gfx GART bus base address */
|
||||
u64 *ca_gfxgart; /* gfx GART vm address */
|
||||
u32 ca_gfxgart_entries;
|
||||
u32 ca_gfxgart_start; /* agpgart start index in ca_gart */
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -93,11 +93,11 @@ struct tioca_kernel {
|
|||
struct tioca_common {
|
||||
struct pcibus_bussoft ca_common; /* common pciio header */
|
||||
|
||||
uint32_t ca_rev;
|
||||
uint32_t ca_closest_nasid;
|
||||
u32 ca_rev;
|
||||
u32 ca_closest_nasid;
|
||||
|
||||
uint64_t ca_prom_private;
|
||||
uint64_t ca_kernel_private;
|
||||
u64 ca_prom_private;
|
||||
u64 ca_kernel_private;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -139,9 +139,9 @@ tioca_paddr_to_gart(unsigned long paddr)
|
|||
*/
|
||||
|
||||
static inline unsigned long
|
||||
tioca_physpage_to_gart(uint64_t page_addr)
|
||||
tioca_physpage_to_gart(u64 page_addr)
|
||||
{
|
||||
uint64_t coretalk_addr;
|
||||
u64 coretalk_addr;
|
||||
|
||||
coretalk_addr = PHYS_TO_TIODMA(page_addr);
|
||||
if (!coretalk_addr) {
|
||||
|
|
@ -161,7 +161,7 @@ tioca_physpage_to_gart(uint64_t page_addr)
|
|||
static inline void
|
||||
tioca_tlbflush(struct tioca_kernel *tioca_kernel)
|
||||
{
|
||||
volatile uint64_t tmp;
|
||||
volatile u64 tmp;
|
||||
volatile struct tioca *ca_base;
|
||||
struct tioca_common *tioca_common;
|
||||
|
||||
|
|
@ -200,7 +200,7 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
|
|||
tmp = __sn_readq_relaxed(&ca_base->ca_control2);
|
||||
}
|
||||
|
||||
extern uint32_t tioca_gart_found;
|
||||
extern u32 tioca_gart_found;
|
||||
extern struct list_head tioca_list;
|
||||
extern int tioca_init_provider(void);
|
||||
extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
|
||||
|
|
|
|||
|
|
@ -35,72 +35,72 @@ typedef volatile struct tioce {
|
|||
/*
|
||||
* ADMIN : Administration Registers
|
||||
*/
|
||||
uint64_t ce_adm_id; /* 0x000000 */
|
||||
uint64_t ce_pad_000008; /* 0x000008 */
|
||||
uint64_t ce_adm_dyn_credit_status; /* 0x000010 */
|
||||
uint64_t ce_adm_last_credit_status; /* 0x000018 */
|
||||
uint64_t ce_adm_credit_limit; /* 0x000020 */
|
||||
uint64_t ce_adm_force_credit; /* 0x000028 */
|
||||
uint64_t ce_adm_control; /* 0x000030 */
|
||||
uint64_t ce_adm_mmr_chn_timeout; /* 0x000038 */
|
||||
uint64_t ce_adm_ssp_ure_timeout; /* 0x000040 */
|
||||
uint64_t ce_adm_ssp_dre_timeout; /* 0x000048 */
|
||||
uint64_t ce_adm_ssp_debug_sel; /* 0x000050 */
|
||||
uint64_t ce_adm_int_status; /* 0x000058 */
|
||||
uint64_t ce_adm_int_status_alias; /* 0x000060 */
|
||||
uint64_t ce_adm_int_mask; /* 0x000068 */
|
||||
uint64_t ce_adm_int_pending; /* 0x000070 */
|
||||
uint64_t ce_adm_force_int; /* 0x000078 */
|
||||
uint64_t ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */
|
||||
uint64_t ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */
|
||||
uint64_t ce_adm_error_summary; /* 0x000100 */
|
||||
uint64_t ce_adm_error_summary_alias; /* 0x000108 */
|
||||
uint64_t ce_adm_error_mask; /* 0x000110 */
|
||||
uint64_t ce_adm_first_error; /* 0x000118 */
|
||||
uint64_t ce_adm_error_overflow; /* 0x000120 */
|
||||
uint64_t ce_adm_error_overflow_alias; /* 0x000128 */
|
||||
uint64_t ce_pad_000130[2]; /* 0x000130 -- 0x000138 */
|
||||
uint64_t ce_adm_tnum_error; /* 0x000140 */
|
||||
uint64_t ce_adm_mmr_err_detail; /* 0x000148 */
|
||||
uint64_t ce_adm_msg_sram_perr_detail; /* 0x000150 */
|
||||
uint64_t ce_adm_bap_sram_perr_detail; /* 0x000158 */
|
||||
uint64_t ce_adm_ce_sram_perr_detail; /* 0x000160 */
|
||||
uint64_t ce_adm_ce_credit_oflow_detail; /* 0x000168 */
|
||||
uint64_t ce_adm_tx_link_idle_max_timer; /* 0x000170 */
|
||||
uint64_t ce_adm_pcie_debug_sel; /* 0x000178 */
|
||||
uint64_t ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */
|
||||
u64 ce_adm_id; /* 0x000000 */
|
||||
u64 ce_pad_000008; /* 0x000008 */
|
||||
u64 ce_adm_dyn_credit_status; /* 0x000010 */
|
||||
u64 ce_adm_last_credit_status; /* 0x000018 */
|
||||
u64 ce_adm_credit_limit; /* 0x000020 */
|
||||
u64 ce_adm_force_credit; /* 0x000028 */
|
||||
u64 ce_adm_control; /* 0x000030 */
|
||||
u64 ce_adm_mmr_chn_timeout; /* 0x000038 */
|
||||
u64 ce_adm_ssp_ure_timeout; /* 0x000040 */
|
||||
u64 ce_adm_ssp_dre_timeout; /* 0x000048 */
|
||||
u64 ce_adm_ssp_debug_sel; /* 0x000050 */
|
||||
u64 ce_adm_int_status; /* 0x000058 */
|
||||
u64 ce_adm_int_status_alias; /* 0x000060 */
|
||||
u64 ce_adm_int_mask; /* 0x000068 */
|
||||
u64 ce_adm_int_pending; /* 0x000070 */
|
||||
u64 ce_adm_force_int; /* 0x000078 */
|
||||
u64 ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */
|
||||
u64 ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */
|
||||
u64 ce_adm_error_summary; /* 0x000100 */
|
||||
u64 ce_adm_error_summary_alias; /* 0x000108 */
|
||||
u64 ce_adm_error_mask; /* 0x000110 */
|
||||
u64 ce_adm_first_error; /* 0x000118 */
|
||||
u64 ce_adm_error_overflow; /* 0x000120 */
|
||||
u64 ce_adm_error_overflow_alias; /* 0x000128 */
|
||||
u64 ce_pad_000130[2]; /* 0x000130 -- 0x000138 */
|
||||
u64 ce_adm_tnum_error; /* 0x000140 */
|
||||
u64 ce_adm_mmr_err_detail; /* 0x000148 */
|
||||
u64 ce_adm_msg_sram_perr_detail; /* 0x000150 */
|
||||
u64 ce_adm_bap_sram_perr_detail; /* 0x000158 */
|
||||
u64 ce_adm_ce_sram_perr_detail; /* 0x000160 */
|
||||
u64 ce_adm_ce_credit_oflow_detail; /* 0x000168 */
|
||||
u64 ce_adm_tx_link_idle_max_timer; /* 0x000170 */
|
||||
u64 ce_adm_pcie_debug_sel; /* 0x000178 */
|
||||
u64 ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */
|
||||
|
||||
uint64_t ce_adm_pcie_debug_sel_top; /* 0x000200 */
|
||||
uint64_t ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */
|
||||
uint64_t ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */
|
||||
uint64_t ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */
|
||||
uint64_t ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */
|
||||
uint64_t ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */
|
||||
uint64_t ce_adm_pcie_trig_compare_top; /* 0x000230 */
|
||||
uint64_t ce_adm_pcie_trig_compare_en_top; /* 0x000238 */
|
||||
uint64_t ce_adm_ssp_debug_sel_top; /* 0x000240 */
|
||||
uint64_t ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */
|
||||
uint64_t ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */
|
||||
uint64_t ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */
|
||||
uint64_t ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */
|
||||
uint64_t ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */
|
||||
uint64_t ce_adm_ssp_trig_compare_top; /* 0x000270 */
|
||||
uint64_t ce_adm_ssp_trig_compare_en_top; /* 0x000278 */
|
||||
uint64_t ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */
|
||||
u64 ce_adm_pcie_debug_sel_top; /* 0x000200 */
|
||||
u64 ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */
|
||||
u64 ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */
|
||||
u64 ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */
|
||||
u64 ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */
|
||||
u64 ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */
|
||||
u64 ce_adm_pcie_trig_compare_top; /* 0x000230 */
|
||||
u64 ce_adm_pcie_trig_compare_en_top; /* 0x000238 */
|
||||
u64 ce_adm_ssp_debug_sel_top; /* 0x000240 */
|
||||
u64 ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */
|
||||
u64 ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */
|
||||
u64 ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */
|
||||
u64 ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */
|
||||
u64 ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */
|
||||
u64 ce_adm_ssp_trig_compare_top; /* 0x000270 */
|
||||
u64 ce_adm_ssp_trig_compare_en_top; /* 0x000278 */
|
||||
u64 ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */
|
||||
|
||||
uint64_t ce_adm_bap_ctrl; /* 0x000400 */
|
||||
uint64_t ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */
|
||||
u64 ce_adm_bap_ctrl; /* 0x000400 */
|
||||
u64 ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */
|
||||
|
||||
uint64_t ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */
|
||||
uint64_t ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */
|
||||
u64 ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */
|
||||
u64 ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */
|
||||
|
||||
uint64_t ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */
|
||||
uint64_t ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */
|
||||
u64 ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */
|
||||
u64 ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */
|
||||
|
||||
uint64_t ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */
|
||||
uint64_t ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */
|
||||
u64 ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */
|
||||
u64 ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */
|
||||
|
||||
uint64_t ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */
|
||||
u64 ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */
|
||||
|
||||
/*
|
||||
* LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
|
||||
|
|
@ -109,141 +109,141 @@ typedef volatile struct tioce {
|
|||
*/
|
||||
#define ce_lsi(link_num) ce_lsi[link_num-1]
|
||||
struct ce_lsi_reg {
|
||||
uint64_t ce_lsi_lpu_id; /* 0x00z000 */
|
||||
uint64_t ce_lsi_rst; /* 0x00z008 */
|
||||
uint64_t ce_lsi_dbg_stat; /* 0x00z010 */
|
||||
uint64_t ce_lsi_dbg_cfg; /* 0x00z018 */
|
||||
uint64_t ce_lsi_ltssm_ctrl; /* 0x00z020 */
|
||||
uint64_t ce_lsi_lk_stat; /* 0x00z028 */
|
||||
uint64_t ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */
|
||||
uint64_t ce_lsi_int_and_stat; /* 0x00z040 */
|
||||
uint64_t ce_lsi_int_mask; /* 0x00z048 */
|
||||
uint64_t ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */
|
||||
uint64_t ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */
|
||||
uint64_t ce_pad_00z108; /* 0x00z108 */
|
||||
uint64_t ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */
|
||||
uint64_t ce_pad_00z118; /* 0x00z118 */
|
||||
uint64_t ce_lsi_lk_perf_cnt1; /* 0x00z120 */
|
||||
uint64_t ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */
|
||||
uint64_t ce_lsi_lk_perf_cnt2; /* 0x00z130 */
|
||||
uint64_t ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */
|
||||
uint64_t ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */
|
||||
uint64_t ce_lsi_lk_lyr_cfg; /* 0x00z200 */
|
||||
uint64_t ce_lsi_lk_lyr_status; /* 0x00z208 */
|
||||
uint64_t ce_lsi_lk_lyr_int_stat; /* 0x00z210 */
|
||||
uint64_t ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */
|
||||
uint64_t ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */
|
||||
uint64_t ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */
|
||||
uint64_t ce_lsi_fc_upd_ctl; /* 0x00z240 */
|
||||
uint64_t ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */
|
||||
uint64_t ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */
|
||||
uint64_t ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */
|
||||
uint64_t ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */
|
||||
uint64_t ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */
|
||||
uint64_t ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */
|
||||
uint64_t ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */
|
||||
uint64_t ce_lsi_rply_tmr_thr; /* 0x00z410 */
|
||||
uint64_t ce_lsi_rply_tmr; /* 0x00z418 */
|
||||
uint64_t ce_lsi_rply_num_stat; /* 0x00z420 */
|
||||
uint64_t ce_lsi_rty_buf_max_addr; /* 0x00z428 */
|
||||
uint64_t ce_lsi_rty_fifo_ptr; /* 0x00z430 */
|
||||
uint64_t ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */
|
||||
uint64_t ce_lsi_rty_fifo_cred; /* 0x00z440 */
|
||||
uint64_t ce_lsi_seq_cnt; /* 0x00z448 */
|
||||
uint64_t ce_lsi_ack_sent_seq_num; /* 0x00z450 */
|
||||
uint64_t ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */
|
||||
uint64_t ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */
|
||||
uint64_t ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */
|
||||
uint64_t ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */
|
||||
uint64_t ce_pad_00z478; /* 0x00z478 */
|
||||
uint64_t ce_lsi_mem_addr_ctl; /* 0x00z480 */
|
||||
uint64_t ce_lsi_mem_d_ld0; /* 0x00z488 */
|
||||
uint64_t ce_lsi_mem_d_ld1; /* 0x00z490 */
|
||||
uint64_t ce_lsi_mem_d_ld2; /* 0x00z498 */
|
||||
uint64_t ce_lsi_mem_d_ld3; /* 0x00z4A0 */
|
||||
uint64_t ce_lsi_mem_d_ld4; /* 0x00z4A8 */
|
||||
uint64_t ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */
|
||||
uint64_t ce_lsi_rty_d_cnt; /* 0x00z4C0 */
|
||||
uint64_t ce_lsi_seq_buf_cnt; /* 0x00z4C8 */
|
||||
uint64_t ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */
|
||||
uint64_t ce_pad_00z4D8; /* 0x00z4D8 */
|
||||
uint64_t ce_lsi_ack_lat_thr; /* 0x00z4E0 */
|
||||
uint64_t ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */
|
||||
uint64_t ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */
|
||||
uint64_t ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */
|
||||
uint64_t ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */
|
||||
uint64_t ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */
|
||||
uint64_t ce_lsi_phy_lyr_cfg; /* 0x00z600 */
|
||||
uint64_t ce_pad_00z608; /* 0x00z608 */
|
||||
uint64_t ce_lsi_phy_lyr_int_stat; /* 0x00z610 */
|
||||
uint64_t ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */
|
||||
uint64_t ce_lsi_phy_lyr_int_mask; /* 0x00z620 */
|
||||
uint64_t ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */
|
||||
uint64_t ce_lsi_rcv_phy_cfg; /* 0x00z680 */
|
||||
uint64_t ce_lsi_rcv_phy_stat1; /* 0x00z688 */
|
||||
uint64_t ce_lsi_rcv_phy_stat2; /* 0x00z690 */
|
||||
uint64_t ce_lsi_rcv_phy_stat3; /* 0x00z698 */
|
||||
uint64_t ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */
|
||||
uint64_t ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */
|
||||
uint64_t ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */
|
||||
uint64_t ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */
|
||||
uint64_t ce_lsi_tx_phy_cfg; /* 0x00z700 */
|
||||
uint64_t ce_lsi_tx_phy_stat; /* 0x00z708 */
|
||||
uint64_t ce_lsi_tx_phy_int_stat; /* 0x00z710 */
|
||||
uint64_t ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */
|
||||
uint64_t ce_lsi_tx_phy_int_mask; /* 0x00z720 */
|
||||
uint64_t ce_lsi_tx_phy_stat2; /* 0x00z728 */
|
||||
uint64_t ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */
|
||||
uint64_t ce_lsi_ltssm_cfg1; /* 0x00z780 */
|
||||
uint64_t ce_lsi_ltssm_cfg2; /* 0x00z788 */
|
||||
uint64_t ce_lsi_ltssm_cfg3; /* 0x00z790 */
|
||||
uint64_t ce_lsi_ltssm_cfg4; /* 0x00z798 */
|
||||
uint64_t ce_lsi_ltssm_cfg5; /* 0x00z7A0 */
|
||||
uint64_t ce_lsi_ltssm_stat1; /* 0x00z7A8 */
|
||||
uint64_t ce_lsi_ltssm_stat2; /* 0x00z7B0 */
|
||||
uint64_t ce_lsi_ltssm_int_stat; /* 0x00z7B8 */
|
||||
uint64_t ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */
|
||||
uint64_t ce_lsi_ltssm_int_mask; /* 0x00z7C8 */
|
||||
uint64_t ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */
|
||||
uint64_t ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */
|
||||
uint64_t ce_lsi_gb_cfg1; /* 0x00z800 */
|
||||
uint64_t ce_lsi_gb_cfg2; /* 0x00z808 */
|
||||
uint64_t ce_lsi_gb_cfg3; /* 0x00z810 */
|
||||
uint64_t ce_lsi_gb_cfg4; /* 0x00z818 */
|
||||
uint64_t ce_lsi_gb_stat; /* 0x00z820 */
|
||||
uint64_t ce_lsi_gb_int_stat; /* 0x00z828 */
|
||||
uint64_t ce_lsi_gb_int_stat_test; /* 0x00z830 */
|
||||
uint64_t ce_lsi_gb_int_mask; /* 0x00z838 */
|
||||
uint64_t ce_lsi_gb_pwr_dn1; /* 0x00z840 */
|
||||
uint64_t ce_lsi_gb_pwr_dn2; /* 0x00z848 */
|
||||
uint64_t ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
|
||||
u64 ce_lsi_lpu_id; /* 0x00z000 */
|
||||
u64 ce_lsi_rst; /* 0x00z008 */
|
||||
u64 ce_lsi_dbg_stat; /* 0x00z010 */
|
||||
u64 ce_lsi_dbg_cfg; /* 0x00z018 */
|
||||
u64 ce_lsi_ltssm_ctrl; /* 0x00z020 */
|
||||
u64 ce_lsi_lk_stat; /* 0x00z028 */
|
||||
u64 ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */
|
||||
u64 ce_lsi_int_and_stat; /* 0x00z040 */
|
||||
u64 ce_lsi_int_mask; /* 0x00z048 */
|
||||
u64 ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */
|
||||
u64 ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */
|
||||
u64 ce_pad_00z108; /* 0x00z108 */
|
||||
u64 ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */
|
||||
u64 ce_pad_00z118; /* 0x00z118 */
|
||||
u64 ce_lsi_lk_perf_cnt1; /* 0x00z120 */
|
||||
u64 ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */
|
||||
u64 ce_lsi_lk_perf_cnt2; /* 0x00z130 */
|
||||
u64 ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */
|
||||
u64 ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */
|
||||
u64 ce_lsi_lk_lyr_cfg; /* 0x00z200 */
|
||||
u64 ce_lsi_lk_lyr_status; /* 0x00z208 */
|
||||
u64 ce_lsi_lk_lyr_int_stat; /* 0x00z210 */
|
||||
u64 ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */
|
||||
u64 ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */
|
||||
u64 ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */
|
||||
u64 ce_lsi_fc_upd_ctl; /* 0x00z240 */
|
||||
u64 ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */
|
||||
u64 ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */
|
||||
u64 ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */
|
||||
u64 ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */
|
||||
u64 ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */
|
||||
u64 ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */
|
||||
u64 ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */
|
||||
u64 ce_lsi_rply_tmr_thr; /* 0x00z410 */
|
||||
u64 ce_lsi_rply_tmr; /* 0x00z418 */
|
||||
u64 ce_lsi_rply_num_stat; /* 0x00z420 */
|
||||
u64 ce_lsi_rty_buf_max_addr; /* 0x00z428 */
|
||||
u64 ce_lsi_rty_fifo_ptr; /* 0x00z430 */
|
||||
u64 ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */
|
||||
u64 ce_lsi_rty_fifo_cred; /* 0x00z440 */
|
||||
u64 ce_lsi_seq_cnt; /* 0x00z448 */
|
||||
u64 ce_lsi_ack_sent_seq_num; /* 0x00z450 */
|
||||
u64 ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */
|
||||
u64 ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */
|
||||
u64 ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */
|
||||
u64 ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */
|
||||
u64 ce_pad_00z478; /* 0x00z478 */
|
||||
u64 ce_lsi_mem_addr_ctl; /* 0x00z480 */
|
||||
u64 ce_lsi_mem_d_ld0; /* 0x00z488 */
|
||||
u64 ce_lsi_mem_d_ld1; /* 0x00z490 */
|
||||
u64 ce_lsi_mem_d_ld2; /* 0x00z498 */
|
||||
u64 ce_lsi_mem_d_ld3; /* 0x00z4A0 */
|
||||
u64 ce_lsi_mem_d_ld4; /* 0x00z4A8 */
|
||||
u64 ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */
|
||||
u64 ce_lsi_rty_d_cnt; /* 0x00z4C0 */
|
||||
u64 ce_lsi_seq_buf_cnt; /* 0x00z4C8 */
|
||||
u64 ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */
|
||||
u64 ce_pad_00z4D8; /* 0x00z4D8 */
|
||||
u64 ce_lsi_ack_lat_thr; /* 0x00z4E0 */
|
||||
u64 ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */
|
||||
u64 ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */
|
||||
u64 ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */
|
||||
u64 ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */
|
||||
u64 ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */
|
||||
u64 ce_lsi_phy_lyr_cfg; /* 0x00z600 */
|
||||
u64 ce_pad_00z608; /* 0x00z608 */
|
||||
u64 ce_lsi_phy_lyr_int_stat; /* 0x00z610 */
|
||||
u64 ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */
|
||||
u64 ce_lsi_phy_lyr_int_mask; /* 0x00z620 */
|
||||
u64 ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */
|
||||
u64 ce_lsi_rcv_phy_cfg; /* 0x00z680 */
|
||||
u64 ce_lsi_rcv_phy_stat1; /* 0x00z688 */
|
||||
u64 ce_lsi_rcv_phy_stat2; /* 0x00z690 */
|
||||
u64 ce_lsi_rcv_phy_stat3; /* 0x00z698 */
|
||||
u64 ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */
|
||||
u64 ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */
|
||||
u64 ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */
|
||||
u64 ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */
|
||||
u64 ce_lsi_tx_phy_cfg; /* 0x00z700 */
|
||||
u64 ce_lsi_tx_phy_stat; /* 0x00z708 */
|
||||
u64 ce_lsi_tx_phy_int_stat; /* 0x00z710 */
|
||||
u64 ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */
|
||||
u64 ce_lsi_tx_phy_int_mask; /* 0x00z720 */
|
||||
u64 ce_lsi_tx_phy_stat2; /* 0x00z728 */
|
||||
u64 ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */
|
||||
u64 ce_lsi_ltssm_cfg1; /* 0x00z780 */
|
||||
u64 ce_lsi_ltssm_cfg2; /* 0x00z788 */
|
||||
u64 ce_lsi_ltssm_cfg3; /* 0x00z790 */
|
||||
u64 ce_lsi_ltssm_cfg4; /* 0x00z798 */
|
||||
u64 ce_lsi_ltssm_cfg5; /* 0x00z7A0 */
|
||||
u64 ce_lsi_ltssm_stat1; /* 0x00z7A8 */
|
||||
u64 ce_lsi_ltssm_stat2; /* 0x00z7B0 */
|
||||
u64 ce_lsi_ltssm_int_stat; /* 0x00z7B8 */
|
||||
u64 ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */
|
||||
u64 ce_lsi_ltssm_int_mask; /* 0x00z7C8 */
|
||||
u64 ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */
|
||||
u64 ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */
|
||||
u64 ce_lsi_gb_cfg1; /* 0x00z800 */
|
||||
u64 ce_lsi_gb_cfg2; /* 0x00z808 */
|
||||
u64 ce_lsi_gb_cfg3; /* 0x00z810 */
|
||||
u64 ce_lsi_gb_cfg4; /* 0x00z818 */
|
||||
u64 ce_lsi_gb_stat; /* 0x00z820 */
|
||||
u64 ce_lsi_gb_int_stat; /* 0x00z828 */
|
||||
u64 ce_lsi_gb_int_stat_test; /* 0x00z830 */
|
||||
u64 ce_lsi_gb_int_mask; /* 0x00z838 */
|
||||
u64 ce_lsi_gb_pwr_dn1; /* 0x00z840 */
|
||||
u64 ce_lsi_gb_pwr_dn2; /* 0x00z848 */
|
||||
u64 ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
|
||||
} ce_lsi[2];
|
||||
|
||||
uint64_t ce_pad_004000[10]; /* 0x004000 -- 0x004048 */
|
||||
u64 ce_pad_004000[10]; /* 0x004000 -- 0x004048 */
|
||||
|
||||
/*
|
||||
* CRM: Coretalk Receive Module Registers
|
||||
*/
|
||||
uint64_t ce_crm_debug_mux; /* 0x004050 */
|
||||
uint64_t ce_pad_004058; /* 0x004058 */
|
||||
uint64_t ce_crm_ssp_err_cmd_wrd; /* 0x004060 */
|
||||
uint64_t ce_crm_ssp_err_addr; /* 0x004068 */
|
||||
uint64_t ce_crm_ssp_err_syn; /* 0x004070 */
|
||||
u64 ce_crm_debug_mux; /* 0x004050 */
|
||||
u64 ce_pad_004058; /* 0x004058 */
|
||||
u64 ce_crm_ssp_err_cmd_wrd; /* 0x004060 */
|
||||
u64 ce_crm_ssp_err_addr; /* 0x004068 */
|
||||
u64 ce_crm_ssp_err_syn; /* 0x004070 */
|
||||
|
||||
uint64_t ce_pad_004078[499]; /* 0x004078 -- 0x005008 */
|
||||
u64 ce_pad_004078[499]; /* 0x004078 -- 0x005008 */
|
||||
|
||||
/*
|
||||
* CXM: Coretalk Xmit Module Registers
|
||||
*/
|
||||
uint64_t ce_cxm_dyn_credit_status; /* 0x005010 */
|
||||
uint64_t ce_cxm_last_credit_status; /* 0x005018 */
|
||||
uint64_t ce_cxm_credit_limit; /* 0x005020 */
|
||||
uint64_t ce_cxm_force_credit; /* 0x005028 */
|
||||
uint64_t ce_cxm_disable_bypass; /* 0x005030 */
|
||||
uint64_t ce_pad_005038[3]; /* 0x005038 -- 0x005048 */
|
||||
uint64_t ce_cxm_debug_mux; /* 0x005050 */
|
||||
u64 ce_cxm_dyn_credit_status; /* 0x005010 */
|
||||
u64 ce_cxm_last_credit_status; /* 0x005018 */
|
||||
u64 ce_cxm_credit_limit; /* 0x005020 */
|
||||
u64 ce_cxm_force_credit; /* 0x005028 */
|
||||
u64 ce_cxm_disable_bypass; /* 0x005030 */
|
||||
u64 ce_pad_005038[3]; /* 0x005038 -- 0x005048 */
|
||||
u64 ce_cxm_debug_mux; /* 0x005050 */
|
||||
|
||||
uint64_t ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */
|
||||
u64 ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */
|
||||
|
||||
/*
|
||||
* DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
|
||||
|
|
@ -258,209 +258,209 @@ typedef volatile struct tioce {
|
|||
#define ce_utl(link_num) ce_dtl_utl[link_num-1]
|
||||
struct ce_dtl_utl_reg {
|
||||
/* DTL */
|
||||
uint64_t ce_dtl_dtdr_credit_limit; /* 0x00y000 */
|
||||
uint64_t ce_dtl_dtdr_credit_force; /* 0x00y008 */
|
||||
uint64_t ce_dtl_dyn_credit_status; /* 0x00y010 */
|
||||
uint64_t ce_dtl_dtl_last_credit_stat; /* 0x00y018 */
|
||||
uint64_t ce_dtl_dtl_ctrl; /* 0x00y020 */
|
||||
uint64_t ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */
|
||||
uint64_t ce_dtl_debug_sel; /* 0x00y050 */
|
||||
uint64_t ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
|
||||
u64 ce_dtl_dtdr_credit_limit; /* 0x00y000 */
|
||||
u64 ce_dtl_dtdr_credit_force; /* 0x00y008 */
|
||||
u64 ce_dtl_dyn_credit_status; /* 0x00y010 */
|
||||
u64 ce_dtl_dtl_last_credit_stat; /* 0x00y018 */
|
||||
u64 ce_dtl_dtl_ctrl; /* 0x00y020 */
|
||||
u64 ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */
|
||||
u64 ce_dtl_debug_sel; /* 0x00y050 */
|
||||
u64 ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
|
||||
|
||||
/* UTL */
|
||||
uint64_t ce_utl_utl_ctrl; /* 0x00z000 */
|
||||
uint64_t ce_utl_debug_sel; /* 0x00z008 */
|
||||
uint64_t ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
|
||||
u64 ce_utl_utl_ctrl; /* 0x00z000 */
|
||||
u64 ce_utl_debug_sel; /* 0x00z008 */
|
||||
u64 ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
|
||||
} ce_dtl_utl[2];
|
||||
|
||||
uint64_t ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */
|
||||
u64 ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */
|
||||
|
||||
/*
|
||||
* URE: Upstream Request Engine
|
||||
*/
|
||||
uint64_t ce_ure_dyn_credit_status; /* 0x00B010 */
|
||||
uint64_t ce_ure_last_credit_status; /* 0x00B018 */
|
||||
uint64_t ce_ure_credit_limit; /* 0x00B020 */
|
||||
uint64_t ce_pad_00B028; /* 0x00B028 */
|
||||
uint64_t ce_ure_control; /* 0x00B030 */
|
||||
uint64_t ce_ure_status; /* 0x00B038 */
|
||||
uint64_t ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */
|
||||
uint64_t ce_ure_debug_sel; /* 0x00B050 */
|
||||
uint64_t ce_ure_pcie_debug_sel; /* 0x00B058 */
|
||||
uint64_t ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */
|
||||
uint64_t ce_ure_ssp_err_addr; /* 0x00B068 */
|
||||
uint64_t ce_ure_page_map; /* 0x00B070 */
|
||||
uint64_t ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */
|
||||
uint64_t ce_ure_pipe_sel1; /* 0x00B088 */
|
||||
uint64_t ce_ure_pipe_mask1; /* 0x00B090 */
|
||||
uint64_t ce_ure_pipe_sel2; /* 0x00B098 */
|
||||
uint64_t ce_ure_pipe_mask2; /* 0x00B0A0 */
|
||||
uint64_t ce_ure_pcie1_credits_sent; /* 0x00B0A8 */
|
||||
uint64_t ce_ure_pcie1_credits_used; /* 0x00B0B0 */
|
||||
uint64_t ce_ure_pcie1_credit_limit; /* 0x00B0B8 */
|
||||
uint64_t ce_ure_pcie2_credits_sent; /* 0x00B0C0 */
|
||||
uint64_t ce_ure_pcie2_credits_used; /* 0x00B0C8 */
|
||||
uint64_t ce_ure_pcie2_credit_limit; /* 0x00B0D0 */
|
||||
uint64_t ce_ure_pcie_force_credit; /* 0x00B0D8 */
|
||||
uint64_t ce_ure_rd_tnum_val; /* 0x00B0E0 */
|
||||
uint64_t ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */
|
||||
uint64_t ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */
|
||||
uint64_t ce_ure_rd_tnum_error; /* 0x00B0F8 */
|
||||
uint64_t ce_ure_rd_tnum_first_cl; /* 0x00B100 */
|
||||
uint64_t ce_ure_rd_tnum_link_buf; /* 0x00B108 */
|
||||
uint64_t ce_ure_wr_tnum_val; /* 0x00B110 */
|
||||
uint64_t ce_ure_sram_err_addr0; /* 0x00B118 */
|
||||
uint64_t ce_ure_sram_err_addr1; /* 0x00B120 */
|
||||
uint64_t ce_ure_sram_err_addr2; /* 0x00B128 */
|
||||
uint64_t ce_ure_sram_rd_addr0; /* 0x00B130 */
|
||||
uint64_t ce_ure_sram_rd_addr1; /* 0x00B138 */
|
||||
uint64_t ce_ure_sram_rd_addr2; /* 0x00B140 */
|
||||
uint64_t ce_ure_sram_wr_addr0; /* 0x00B148 */
|
||||
uint64_t ce_ure_sram_wr_addr1; /* 0x00B150 */
|
||||
uint64_t ce_ure_sram_wr_addr2; /* 0x00B158 */
|
||||
uint64_t ce_ure_buf_flush10; /* 0x00B160 */
|
||||
uint64_t ce_ure_buf_flush11; /* 0x00B168 */
|
||||
uint64_t ce_ure_buf_flush12; /* 0x00B170 */
|
||||
uint64_t ce_ure_buf_flush13; /* 0x00B178 */
|
||||
uint64_t ce_ure_buf_flush20; /* 0x00B180 */
|
||||
uint64_t ce_ure_buf_flush21; /* 0x00B188 */
|
||||
uint64_t ce_ure_buf_flush22; /* 0x00B190 */
|
||||
uint64_t ce_ure_buf_flush23; /* 0x00B198 */
|
||||
uint64_t ce_ure_pcie_control1; /* 0x00B1A0 */
|
||||
uint64_t ce_ure_pcie_control2; /* 0x00B1A8 */
|
||||
u64 ce_ure_dyn_credit_status; /* 0x00B010 */
|
||||
u64 ce_ure_last_credit_status; /* 0x00B018 */
|
||||
u64 ce_ure_credit_limit; /* 0x00B020 */
|
||||
u64 ce_pad_00B028; /* 0x00B028 */
|
||||
u64 ce_ure_control; /* 0x00B030 */
|
||||
u64 ce_ure_status; /* 0x00B038 */
|
||||
u64 ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */
|
||||
u64 ce_ure_debug_sel; /* 0x00B050 */
|
||||
u64 ce_ure_pcie_debug_sel; /* 0x00B058 */
|
||||
u64 ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */
|
||||
u64 ce_ure_ssp_err_addr; /* 0x00B068 */
|
||||
u64 ce_ure_page_map; /* 0x00B070 */
|
||||
u64 ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */
|
||||
u64 ce_ure_pipe_sel1; /* 0x00B088 */
|
||||
u64 ce_ure_pipe_mask1; /* 0x00B090 */
|
||||
u64 ce_ure_pipe_sel2; /* 0x00B098 */
|
||||
u64 ce_ure_pipe_mask2; /* 0x00B0A0 */
|
||||
u64 ce_ure_pcie1_credits_sent; /* 0x00B0A8 */
|
||||
u64 ce_ure_pcie1_credits_used; /* 0x00B0B0 */
|
||||
u64 ce_ure_pcie1_credit_limit; /* 0x00B0B8 */
|
||||
u64 ce_ure_pcie2_credits_sent; /* 0x00B0C0 */
|
||||
u64 ce_ure_pcie2_credits_used; /* 0x00B0C8 */
|
||||
u64 ce_ure_pcie2_credit_limit; /* 0x00B0D0 */
|
||||
u64 ce_ure_pcie_force_credit; /* 0x00B0D8 */
|
||||
u64 ce_ure_rd_tnum_val; /* 0x00B0E0 */
|
||||
u64 ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */
|
||||
u64 ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */
|
||||
u64 ce_ure_rd_tnum_error; /* 0x00B0F8 */
|
||||
u64 ce_ure_rd_tnum_first_cl; /* 0x00B100 */
|
||||
u64 ce_ure_rd_tnum_link_buf; /* 0x00B108 */
|
||||
u64 ce_ure_wr_tnum_val; /* 0x00B110 */
|
||||
u64 ce_ure_sram_err_addr0; /* 0x00B118 */
|
||||
u64 ce_ure_sram_err_addr1; /* 0x00B120 */
|
||||
u64 ce_ure_sram_err_addr2; /* 0x00B128 */
|
||||
u64 ce_ure_sram_rd_addr0; /* 0x00B130 */
|
||||
u64 ce_ure_sram_rd_addr1; /* 0x00B138 */
|
||||
u64 ce_ure_sram_rd_addr2; /* 0x00B140 */
|
||||
u64 ce_ure_sram_wr_addr0; /* 0x00B148 */
|
||||
u64 ce_ure_sram_wr_addr1; /* 0x00B150 */
|
||||
u64 ce_ure_sram_wr_addr2; /* 0x00B158 */
|
||||
u64 ce_ure_buf_flush10; /* 0x00B160 */
|
||||
u64 ce_ure_buf_flush11; /* 0x00B168 */
|
||||
u64 ce_ure_buf_flush12; /* 0x00B170 */
|
||||
u64 ce_ure_buf_flush13; /* 0x00B178 */
|
||||
u64 ce_ure_buf_flush20; /* 0x00B180 */
|
||||
u64 ce_ure_buf_flush21; /* 0x00B188 */
|
||||
u64 ce_ure_buf_flush22; /* 0x00B190 */
|
||||
u64 ce_ure_buf_flush23; /* 0x00B198 */
|
||||
u64 ce_ure_pcie_control1; /* 0x00B1A0 */
|
||||
u64 ce_ure_pcie_control2; /* 0x00B1A8 */
|
||||
|
||||
uint64_t ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */
|
||||
u64 ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */
|
||||
|
||||
/* Upstream Data Buffer, Port1 */
|
||||
struct ce_ure_maint_ups_dat1_data {
|
||||
uint64_t data63_0[512]; /* 0x00C000 -- 0x00CFF8 */
|
||||
uint64_t data127_64[512]; /* 0x00D000 -- 0x00DFF8 */
|
||||
uint64_t parity[512]; /* 0x00E000 -- 0x00EFF8 */
|
||||
u64 data63_0[512]; /* 0x00C000 -- 0x00CFF8 */
|
||||
u64 data127_64[512]; /* 0x00D000 -- 0x00DFF8 */
|
||||
u64 parity[512]; /* 0x00E000 -- 0x00EFF8 */
|
||||
} ce_ure_maint_ups_dat1;
|
||||
|
||||
/* Upstream Header Buffer, Port1 */
|
||||
struct ce_ure_maint_ups_hdr1_data {
|
||||
uint64_t data63_0[512]; /* 0x00F000 -- 0x00FFF8 */
|
||||
uint64_t data127_64[512]; /* 0x010000 -- 0x010FF8 */
|
||||
uint64_t parity[512]; /* 0x011000 -- 0x011FF8 */
|
||||
u64 data63_0[512]; /* 0x00F000 -- 0x00FFF8 */
|
||||
u64 data127_64[512]; /* 0x010000 -- 0x010FF8 */
|
||||
u64 parity[512]; /* 0x011000 -- 0x011FF8 */
|
||||
} ce_ure_maint_ups_hdr1;
|
||||
|
||||
/* Upstream Data Buffer, Port2 */
|
||||
struct ce_ure_maint_ups_dat2_data {
|
||||
uint64_t data63_0[512]; /* 0x012000 -- 0x012FF8 */
|
||||
uint64_t data127_64[512]; /* 0x013000 -- 0x013FF8 */
|
||||
uint64_t parity[512]; /* 0x014000 -- 0x014FF8 */
|
||||
u64 data63_0[512]; /* 0x012000 -- 0x012FF8 */
|
||||
u64 data127_64[512]; /* 0x013000 -- 0x013FF8 */
|
||||
u64 parity[512]; /* 0x014000 -- 0x014FF8 */
|
||||
} ce_ure_maint_ups_dat2;
|
||||
|
||||
/* Upstream Header Buffer, Port2 */
|
||||
struct ce_ure_maint_ups_hdr2_data {
|
||||
uint64_t data63_0[512]; /* 0x015000 -- 0x015FF8 */
|
||||
uint64_t data127_64[512]; /* 0x016000 -- 0x016FF8 */
|
||||
uint64_t parity[512]; /* 0x017000 -- 0x017FF8 */
|
||||
u64 data63_0[512]; /* 0x015000 -- 0x015FF8 */
|
||||
u64 data127_64[512]; /* 0x016000 -- 0x016FF8 */
|
||||
u64 parity[512]; /* 0x017000 -- 0x017FF8 */
|
||||
} ce_ure_maint_ups_hdr2;
|
||||
|
||||
/* Downstream Data Buffer */
|
||||
struct ce_ure_maint_dns_dat_data {
|
||||
uint64_t data63_0[512]; /* 0x018000 -- 0x018FF8 */
|
||||
uint64_t data127_64[512]; /* 0x019000 -- 0x019FF8 */
|
||||
uint64_t parity[512]; /* 0x01A000 -- 0x01AFF8 */
|
||||
u64 data63_0[512]; /* 0x018000 -- 0x018FF8 */
|
||||
u64 data127_64[512]; /* 0x019000 -- 0x019FF8 */
|
||||
u64 parity[512]; /* 0x01A000 -- 0x01AFF8 */
|
||||
} ce_ure_maint_dns_dat;
|
||||
|
||||
/* Downstream Header Buffer */
|
||||
struct ce_ure_maint_dns_hdr_data {
|
||||
uint64_t data31_0[64]; /* 0x01B000 -- 0x01B1F8 */
|
||||
uint64_t data95_32[64]; /* 0x01B200 -- 0x01B3F8 */
|
||||
uint64_t parity[64]; /* 0x01B400 -- 0x01B5F8 */
|
||||
u64 data31_0[64]; /* 0x01B000 -- 0x01B1F8 */
|
||||
u64 data95_32[64]; /* 0x01B200 -- 0x01B3F8 */
|
||||
u64 parity[64]; /* 0x01B400 -- 0x01B5F8 */
|
||||
} ce_ure_maint_dns_hdr;
|
||||
|
||||
/* RCI Buffer Data */
|
||||
struct ce_ure_maint_rci_data {
|
||||
uint64_t data41_0[64]; /* 0x01B600 -- 0x01B7F8 */
|
||||
uint64_t data69_42[64]; /* 0x01B800 -- 0x01B9F8 */
|
||||
u64 data41_0[64]; /* 0x01B600 -- 0x01B7F8 */
|
||||
u64 data69_42[64]; /* 0x01B800 -- 0x01B9F8 */
|
||||
} ce_ure_maint_rci;
|
||||
|
||||
/* Response Queue */
|
||||
uint64_t ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */
|
||||
u64 ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */
|
||||
|
||||
uint64_t ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */
|
||||
u64 ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */
|
||||
|
||||
/* Admin Build-a-Packet Buffer */
|
||||
struct ce_adm_maint_bap_buf_data {
|
||||
uint64_t data63_0[258]; /* 0x024000 -- 0x024808 */
|
||||
uint64_t data127_64[258]; /* 0x024810 -- 0x025018 */
|
||||
uint64_t parity[258]; /* 0x025020 -- 0x025828 */
|
||||
u64 data63_0[258]; /* 0x024000 -- 0x024808 */
|
||||
u64 data127_64[258]; /* 0x024810 -- 0x025018 */
|
||||
u64 parity[258]; /* 0x025020 -- 0x025828 */
|
||||
} ce_adm_maint_bap_buf;
|
||||
|
||||
uint64_t ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */
|
||||
u64 ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */
|
||||
|
||||
/* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */
|
||||
uint64_t ce_ure_ate40[TIOCE_NUM_M40_ATES];
|
||||
u64 ce_ure_ate40[TIOCE_NUM_M40_ATES];
|
||||
|
||||
/* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */
|
||||
uint64_t ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
|
||||
u64 ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
|
||||
|
||||
uint64_t ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */
|
||||
u64 ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */
|
||||
|
||||
/*
|
||||
* DRE: Down Stream Request Engine
|
||||
*/
|
||||
uint64_t ce_dre_dyn_credit_status1; /* 0x040010 */
|
||||
uint64_t ce_dre_dyn_credit_status2; /* 0x040018 */
|
||||
uint64_t ce_dre_last_credit_status1; /* 0x040020 */
|
||||
uint64_t ce_dre_last_credit_status2; /* 0x040028 */
|
||||
uint64_t ce_dre_credit_limit1; /* 0x040030 */
|
||||
uint64_t ce_dre_credit_limit2; /* 0x040038 */
|
||||
uint64_t ce_dre_force_credit1; /* 0x040040 */
|
||||
uint64_t ce_dre_force_credit2; /* 0x040048 */
|
||||
uint64_t ce_dre_debug_mux1; /* 0x040050 */
|
||||
uint64_t ce_dre_debug_mux2; /* 0x040058 */
|
||||
uint64_t ce_dre_ssp_err_cmd_wrd; /* 0x040060 */
|
||||
uint64_t ce_dre_ssp_err_addr; /* 0x040068 */
|
||||
uint64_t ce_dre_comp_err_cmd_wrd; /* 0x040070 */
|
||||
uint64_t ce_dre_comp_err_addr; /* 0x040078 */
|
||||
uint64_t ce_dre_req_status; /* 0x040080 */
|
||||
uint64_t ce_dre_config1; /* 0x040088 */
|
||||
uint64_t ce_dre_config2; /* 0x040090 */
|
||||
uint64_t ce_dre_config_req_status; /* 0x040098 */
|
||||
uint64_t ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */
|
||||
uint64_t ce_dre_dyn_fifo; /* 0x040100 */
|
||||
uint64_t ce_pad_040108[3]; /* 0x040108 -- 0x040118 */
|
||||
uint64_t ce_dre_last_fifo; /* 0x040120 */
|
||||
u64 ce_dre_dyn_credit_status1; /* 0x040010 */
|
||||
u64 ce_dre_dyn_credit_status2; /* 0x040018 */
|
||||
u64 ce_dre_last_credit_status1; /* 0x040020 */
|
||||
u64 ce_dre_last_credit_status2; /* 0x040028 */
|
||||
u64 ce_dre_credit_limit1; /* 0x040030 */
|
||||
u64 ce_dre_credit_limit2; /* 0x040038 */
|
||||
u64 ce_dre_force_credit1; /* 0x040040 */
|
||||
u64 ce_dre_force_credit2; /* 0x040048 */
|
||||
u64 ce_dre_debug_mux1; /* 0x040050 */
|
||||
u64 ce_dre_debug_mux2; /* 0x040058 */
|
||||
u64 ce_dre_ssp_err_cmd_wrd; /* 0x040060 */
|
||||
u64 ce_dre_ssp_err_addr; /* 0x040068 */
|
||||
u64 ce_dre_comp_err_cmd_wrd; /* 0x040070 */
|
||||
u64 ce_dre_comp_err_addr; /* 0x040078 */
|
||||
u64 ce_dre_req_status; /* 0x040080 */
|
||||
u64 ce_dre_config1; /* 0x040088 */
|
||||
u64 ce_dre_config2; /* 0x040090 */
|
||||
u64 ce_dre_config_req_status; /* 0x040098 */
|
||||
u64 ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */
|
||||
u64 ce_dre_dyn_fifo; /* 0x040100 */
|
||||
u64 ce_pad_040108[3]; /* 0x040108 -- 0x040118 */
|
||||
u64 ce_dre_last_fifo; /* 0x040120 */
|
||||
|
||||
uint64_t ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */
|
||||
u64 ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */
|
||||
|
||||
/* DRE Downstream Head Queue */
|
||||
struct ce_dre_maint_ds_head_queue {
|
||||
uint64_t data63_0[32]; /* 0x040200 -- 0x0402F8 */
|
||||
uint64_t data127_64[32]; /* 0x040300 -- 0x0403F8 */
|
||||
uint64_t parity[32]; /* 0x040400 -- 0x0404F8 */
|
||||
u64 data63_0[32]; /* 0x040200 -- 0x0402F8 */
|
||||
u64 data127_64[32]; /* 0x040300 -- 0x0403F8 */
|
||||
u64 parity[32]; /* 0x040400 -- 0x0404F8 */
|
||||
} ce_dre_maint_ds_head_q;
|
||||
|
||||
uint64_t ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */
|
||||
u64 ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */
|
||||
|
||||
/* DRE Downstream Data Queue */
|
||||
struct ce_dre_maint_ds_data_queue {
|
||||
uint64_t data63_0[256]; /* 0x041000 -- 0x0417F8 */
|
||||
uint64_t ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
|
||||
uint64_t data127_64[256]; /* 0x042000 -- 0x0427F8 */
|
||||
uint64_t ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
|
||||
uint64_t parity[256]; /* 0x043000 -- 0x0437F8 */
|
||||
uint64_t ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
|
||||
u64 data63_0[256]; /* 0x041000 -- 0x0417F8 */
|
||||
u64 ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
|
||||
u64 data127_64[256]; /* 0x042000 -- 0x0427F8 */
|
||||
u64 ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
|
||||
u64 parity[256]; /* 0x043000 -- 0x0437F8 */
|
||||
u64 ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
|
||||
} ce_dre_maint_ds_data_q;
|
||||
|
||||
/* DRE URE Upstream Response Queue */
|
||||
struct ce_dre_maint_ure_us_rsp_queue {
|
||||
uint64_t data63_0[8]; /* 0x044000 -- 0x044038 */
|
||||
uint64_t ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */
|
||||
uint64_t data127_64[8]; /* 0x044100 -- 0x044138 */
|
||||
uint64_t ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */
|
||||
uint64_t parity[8]; /* 0x044200 -- 0x044238 */
|
||||
uint64_t ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */
|
||||
u64 data63_0[8]; /* 0x044000 -- 0x044038 */
|
||||
u64 ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */
|
||||
u64 data127_64[8]; /* 0x044100 -- 0x044138 */
|
||||
u64 ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */
|
||||
u64 parity[8]; /* 0x044200 -- 0x044238 */
|
||||
u64 ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */
|
||||
} ce_dre_maint_ure_us_rsp_q;
|
||||
|
||||
uint64_t ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
|
||||
u64 ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
|
||||
|
||||
uint64_t ce_end_of_struct; /* 0x044400 */
|
||||
u64 ce_end_of_struct; /* 0x044400 */
|
||||
} tioce_t;
|
||||
|
||||
|
||||
|
|
@ -625,11 +625,11 @@ typedef volatile struct tioce {
|
|||
#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT)
|
||||
#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT)
|
||||
#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT)
|
||||
#define CE_URE_PIPE_BUS(b) (((uint64_t)(b) << BUS_SRC_ID_SHFT) & \
|
||||
#define CE_URE_PIPE_BUS(b) (((u64)(b) << BUS_SRC_ID_SHFT) & \
|
||||
CE_URE_BUS_MASK)
|
||||
#define CE_URE_PIPE_DEV(d) (((uint64_t)(d) << DEV_SRC_ID_SHFT) & \
|
||||
#define CE_URE_PIPE_DEV(d) (((u64)(d) << DEV_SRC_ID_SHFT) & \
|
||||
CE_URE_DEV_MASK)
|
||||
#define CE_URE_PIPE_FNC(f) (((uint64_t)(f) << FNC_SRC_ID_SHFT) & \
|
||||
#define CE_URE_PIPE_FNC(f) (((u64)(f) << FNC_SRC_ID_SHFT) & \
|
||||
CE_URE_FNC_MASK)
|
||||
|
||||
#define CE_URE_SEL1_SHFT 0
|
||||
|
|
@ -660,9 +660,9 @@ typedef volatile struct tioce {
|
|||
#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT)
|
||||
#define CE_URE_PN2_SHFT 24
|
||||
#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT)
|
||||
#define CE_URE_PN1_SET(n) (((uint64_t)(n) << CE_URE_PN1_SHFT) & \
|
||||
#define CE_URE_PN1_SET(n) (((u64)(n) << CE_URE_PN1_SHFT) & \
|
||||
CE_URE_PN1_MASK)
|
||||
#define CE_URE_PN2_SET(n) (((uint64_t)(n) << CE_URE_PN2_SHFT) & \
|
||||
#define CE_URE_PN2_SET(n) (((u64)(n) << CE_URE_PN2_SHFT) & \
|
||||
CE_URE_PN2_MASK)
|
||||
|
||||
/* ce_ure_pcie_control2 register bit masks & shifts */
|
||||
|
|
@ -681,9 +681,9 @@ typedef volatile struct tioce {
|
|||
#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT)
|
||||
#define CE_URE_PSN2_SHFT 32
|
||||
#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT)
|
||||
#define CE_URE_PSN1_SET(n) (((uint64_t)(n) << CE_URE_PSN1_SHFT) & \
|
||||
#define CE_URE_PSN1_SET(n) (((u64)(n) << CE_URE_PSN1_SHFT) & \
|
||||
CE_URE_PSN1_MASK)
|
||||
#define CE_URE_PSN2_SET(n) (((uint64_t)(n) << CE_URE_PSN2_SHFT) & \
|
||||
#define CE_URE_PSN2_SET(n) (((u64)(n) << CE_URE_PSN2_SHFT) & \
|
||||
CE_URE_PSN2_MASK)
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -21,9 +21,9 @@
|
|||
struct tioce_common {
|
||||
struct pcibus_bussoft ce_pcibus; /* common pciio header */
|
||||
|
||||
uint32_t ce_rev;
|
||||
uint64_t ce_kernel_private;
|
||||
uint64_t ce_prom_private;
|
||||
u32 ce_rev;
|
||||
u64 ce_kernel_private;
|
||||
u64 ce_prom_private;
|
||||
};
|
||||
|
||||
struct tioce_kernel {
|
||||
|
|
@ -31,31 +31,31 @@ struct tioce_kernel {
|
|||
spinlock_t ce_lock;
|
||||
struct list_head ce_dmamap_list;
|
||||
|
||||
uint64_t ce_ate40_shadow[TIOCE_NUM_M40_ATES];
|
||||
uint64_t ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
|
||||
uint32_t ce_ate3240_pagesize;
|
||||
u64 ce_ate40_shadow[TIOCE_NUM_M40_ATES];
|
||||
u64 ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
|
||||
u32 ce_ate3240_pagesize;
|
||||
|
||||
uint8_t ce_port1_secondary;
|
||||
u8 ce_port1_secondary;
|
||||
|
||||
/* per-port resources */
|
||||
struct {
|
||||
int dirmap_refcnt;
|
||||
uint64_t dirmap_shadow;
|
||||
u64 dirmap_shadow;
|
||||
} ce_port[TIOCE_NUM_PORTS];
|
||||
};
|
||||
|
||||
struct tioce_dmamap {
|
||||
struct list_head ce_dmamap_list; /* headed by tioce_kernel */
|
||||
uint32_t refcnt;
|
||||
u32 refcnt;
|
||||
|
||||
uint64_t nbytes; /* # bytes mapped */
|
||||
u64 nbytes; /* # bytes mapped */
|
||||
|
||||
uint64_t ct_start; /* coretalk start address */
|
||||
uint64_t pci_start; /* bus start address */
|
||||
u64 ct_start; /* coretalk start address */
|
||||
u64 pci_start; /* bus start address */
|
||||
|
||||
uint64_t *ate_hw; /* hw ptr of first ate in map */
|
||||
uint64_t *ate_shadow; /* shadow ptr of firat ate */
|
||||
uint16_t ate_count; /* # ate's in the map */
|
||||
u64 *ate_hw; /* hw ptr of first ate in map */
|
||||
u64 *ate_shadow; /* shadow ptr of firat ate */
|
||||
u16 ate_count; /* # ate's in the map */
|
||||
};
|
||||
|
||||
extern int tioce_init_provider(void);
|
||||
|
|
|
|||
|
|
@ -21,189 +21,189 @@ struct tiocp{
|
|||
/* 0x000000-0x00FFFF -- Local Registers */
|
||||
|
||||
/* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
|
||||
uint64_t cp_id; /* 0x000000 */
|
||||
uint64_t cp_stat; /* 0x000008 */
|
||||
uint64_t cp_err_upper; /* 0x000010 */
|
||||
uint64_t cp_err_lower; /* 0x000018 */
|
||||
u64 cp_id; /* 0x000000 */
|
||||
u64 cp_stat; /* 0x000008 */
|
||||
u64 cp_err_upper; /* 0x000010 */
|
||||
u64 cp_err_lower; /* 0x000018 */
|
||||
#define cp_err cp_err_lower
|
||||
uint64_t cp_control; /* 0x000020 */
|
||||
uint64_t cp_req_timeout; /* 0x000028 */
|
||||
uint64_t cp_intr_upper; /* 0x000030 */
|
||||
uint64_t cp_intr_lower; /* 0x000038 */
|
||||
u64 cp_control; /* 0x000020 */
|
||||
u64 cp_req_timeout; /* 0x000028 */
|
||||
u64 cp_intr_upper; /* 0x000030 */
|
||||
u64 cp_intr_lower; /* 0x000038 */
|
||||
#define cp_intr cp_intr_lower
|
||||
uint64_t cp_err_cmdword; /* 0x000040 */
|
||||
uint64_t _pad_000048; /* 0x000048 */
|
||||
uint64_t cp_tflush; /* 0x000050 */
|
||||
u64 cp_err_cmdword; /* 0x000040 */
|
||||
u64 _pad_000048; /* 0x000048 */
|
||||
u64 cp_tflush; /* 0x000050 */
|
||||
|
||||
/* 0x000058-0x00007F -- Bridge-specific Configuration */
|
||||
uint64_t cp_aux_err; /* 0x000058 */
|
||||
uint64_t cp_resp_upper; /* 0x000060 */
|
||||
uint64_t cp_resp_lower; /* 0x000068 */
|
||||
u64 cp_aux_err; /* 0x000058 */
|
||||
u64 cp_resp_upper; /* 0x000060 */
|
||||
u64 cp_resp_lower; /* 0x000068 */
|
||||
#define cp_resp cp_resp_lower
|
||||
uint64_t cp_tst_pin_ctrl; /* 0x000070 */
|
||||
uint64_t cp_addr_lkerr; /* 0x000078 */
|
||||
u64 cp_tst_pin_ctrl; /* 0x000070 */
|
||||
u64 cp_addr_lkerr; /* 0x000078 */
|
||||
|
||||
/* 0x000080-0x00008F -- PMU & MAP */
|
||||
uint64_t cp_dir_map; /* 0x000080 */
|
||||
uint64_t _pad_000088; /* 0x000088 */
|
||||
u64 cp_dir_map; /* 0x000080 */
|
||||
u64 _pad_000088; /* 0x000088 */
|
||||
|
||||
/* 0x000090-0x00009F -- SSRAM */
|
||||
uint64_t cp_map_fault; /* 0x000090 */
|
||||
uint64_t _pad_000098; /* 0x000098 */
|
||||
u64 cp_map_fault; /* 0x000090 */
|
||||
u64 _pad_000098; /* 0x000098 */
|
||||
|
||||
/* 0x0000A0-0x0000AF -- Arbitration */
|
||||
uint64_t cp_arb; /* 0x0000A0 */
|
||||
uint64_t _pad_0000A8; /* 0x0000A8 */
|
||||
u64 cp_arb; /* 0x0000A0 */
|
||||
u64 _pad_0000A8; /* 0x0000A8 */
|
||||
|
||||
/* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
|
||||
uint64_t cp_ate_parity_err; /* 0x0000B0 */
|
||||
uint64_t _pad_0000B8; /* 0x0000B8 */
|
||||
u64 cp_ate_parity_err; /* 0x0000B0 */
|
||||
u64 _pad_0000B8; /* 0x0000B8 */
|
||||
|
||||
/* 0x0000C0-0x0000FF -- PCI/GIO */
|
||||
uint64_t cp_bus_timeout; /* 0x0000C0 */
|
||||
uint64_t cp_pci_cfg; /* 0x0000C8 */
|
||||
uint64_t cp_pci_err_upper; /* 0x0000D0 */
|
||||
uint64_t cp_pci_err_lower; /* 0x0000D8 */
|
||||
u64 cp_bus_timeout; /* 0x0000C0 */
|
||||
u64 cp_pci_cfg; /* 0x0000C8 */
|
||||
u64 cp_pci_err_upper; /* 0x0000D0 */
|
||||
u64 cp_pci_err_lower; /* 0x0000D8 */
|
||||
#define cp_pci_err cp_pci_err_lower
|
||||
uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */
|
||||
u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
|
||||
|
||||
/* 0x000100-0x0001FF -- Interrupt */
|
||||
uint64_t cp_int_status; /* 0x000100 */
|
||||
uint64_t cp_int_enable; /* 0x000108 */
|
||||
uint64_t cp_int_rst_stat; /* 0x000110 */
|
||||
uint64_t cp_int_mode; /* 0x000118 */
|
||||
uint64_t cp_int_device; /* 0x000120 */
|
||||
uint64_t cp_int_host_err; /* 0x000128 */
|
||||
uint64_t cp_int_addr[8]; /* 0x0001{30,,,68} */
|
||||
uint64_t cp_err_int_view; /* 0x000170 */
|
||||
uint64_t cp_mult_int; /* 0x000178 */
|
||||
uint64_t cp_force_always[8]; /* 0x0001{80,,,B8} */
|
||||
uint64_t cp_force_pin[8]; /* 0x0001{C0,,,F8} */
|
||||
u64 cp_int_status; /* 0x000100 */
|
||||
u64 cp_int_enable; /* 0x000108 */
|
||||
u64 cp_int_rst_stat; /* 0x000110 */
|
||||
u64 cp_int_mode; /* 0x000118 */
|
||||
u64 cp_int_device; /* 0x000120 */
|
||||
u64 cp_int_host_err; /* 0x000128 */
|
||||
u64 cp_int_addr[8]; /* 0x0001{30,,,68} */
|
||||
u64 cp_err_int_view; /* 0x000170 */
|
||||
u64 cp_mult_int; /* 0x000178 */
|
||||
u64 cp_force_always[8]; /* 0x0001{80,,,B8} */
|
||||
u64 cp_force_pin[8]; /* 0x0001{C0,,,F8} */
|
||||
|
||||
/* 0x000200-0x000298 -- Device */
|
||||
uint64_t cp_device[4]; /* 0x0002{00,,,18} */
|
||||
uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */
|
||||
uint64_t cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
|
||||
uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */
|
||||
uint64_t cp_rrb_map[2]; /* 0x0002{80,,,88} */
|
||||
u64 cp_device[4]; /* 0x0002{00,,,18} */
|
||||
u64 _pad_000220[4]; /* 0x0002{20,,,38} */
|
||||
u64 cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
|
||||
u64 _pad_000260[4]; /* 0x0002{60,,,78} */
|
||||
u64 cp_rrb_map[2]; /* 0x0002{80,,,88} */
|
||||
#define cp_even_resp cp_rrb_map[0] /* 0x000280 */
|
||||
#define cp_odd_resp cp_rrb_map[1] /* 0x000288 */
|
||||
uint64_t cp_resp_status; /* 0x000290 */
|
||||
uint64_t cp_resp_clear; /* 0x000298 */
|
||||
u64 cp_resp_status; /* 0x000290 */
|
||||
u64 cp_resp_clear; /* 0x000298 */
|
||||
|
||||
uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */
|
||||
u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
|
||||
|
||||
/* 0x000300-0x0003F8 -- Buffer Address Match Registers */
|
||||
struct {
|
||||
uint64_t upper; /* 0x0003{00,,,F0} */
|
||||
uint64_t lower; /* 0x0003{08,,,F8} */
|
||||
u64 upper; /* 0x0003{00,,,F0} */
|
||||
u64 lower; /* 0x0003{08,,,F8} */
|
||||
} cp_buf_addr_match[16];
|
||||
|
||||
/* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
|
||||
struct {
|
||||
uint64_t flush_w_touch; /* 0x000{400,,,5C0} */
|
||||
uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */
|
||||
uint64_t inflight; /* 0x000{410,,,5D0} */
|
||||
uint64_t prefetch; /* 0x000{418,,,5D8} */
|
||||
uint64_t total_pci_retry; /* 0x000{420,,,5E0} */
|
||||
uint64_t max_pci_retry; /* 0x000{428,,,5E8} */
|
||||
uint64_t max_latency; /* 0x000{430,,,5F0} */
|
||||
uint64_t clear_all; /* 0x000{438,,,5F8} */
|
||||
u64 flush_w_touch; /* 0x000{400,,,5C0} */
|
||||
u64 flush_wo_touch; /* 0x000{408,,,5C8} */
|
||||
u64 inflight; /* 0x000{410,,,5D0} */
|
||||
u64 prefetch; /* 0x000{418,,,5D8} */
|
||||
u64 total_pci_retry; /* 0x000{420,,,5E0} */
|
||||
u64 max_pci_retry; /* 0x000{428,,,5E8} */
|
||||
u64 max_latency; /* 0x000{430,,,5F0} */
|
||||
u64 clear_all; /* 0x000{438,,,5F8} */
|
||||
} cp_buf_count[8];
|
||||
|
||||
|
||||
/* 0x000600-0x0009FF -- PCI/X registers */
|
||||
uint64_t cp_pcix_bus_err_addr; /* 0x000600 */
|
||||
uint64_t cp_pcix_bus_err_attr; /* 0x000608 */
|
||||
uint64_t cp_pcix_bus_err_data; /* 0x000610 */
|
||||
uint64_t cp_pcix_pio_split_addr; /* 0x000618 */
|
||||
uint64_t cp_pcix_pio_split_attr; /* 0x000620 */
|
||||
uint64_t cp_pcix_dma_req_err_attr; /* 0x000628 */
|
||||
uint64_t cp_pcix_dma_req_err_addr; /* 0x000630 */
|
||||
uint64_t cp_pcix_timeout; /* 0x000638 */
|
||||
u64 cp_pcix_bus_err_addr; /* 0x000600 */
|
||||
u64 cp_pcix_bus_err_attr; /* 0x000608 */
|
||||
u64 cp_pcix_bus_err_data; /* 0x000610 */
|
||||
u64 cp_pcix_pio_split_addr; /* 0x000618 */
|
||||
u64 cp_pcix_pio_split_attr; /* 0x000620 */
|
||||
u64 cp_pcix_dma_req_err_attr; /* 0x000628 */
|
||||
u64 cp_pcix_dma_req_err_addr; /* 0x000630 */
|
||||
u64 cp_pcix_timeout; /* 0x000638 */
|
||||
|
||||
uint64_t _pad_000640[24]; /* 0x000{640,,,6F8} */
|
||||
u64 _pad_000640[24]; /* 0x000{640,,,6F8} */
|
||||
|
||||
/* 0x000700-0x000737 -- Debug Registers */
|
||||
uint64_t cp_ct_debug_ctl; /* 0x000700 */
|
||||
uint64_t cp_br_debug_ctl; /* 0x000708 */
|
||||
uint64_t cp_mux3_debug_ctl; /* 0x000710 */
|
||||
uint64_t cp_mux4_debug_ctl; /* 0x000718 */
|
||||
uint64_t cp_mux5_debug_ctl; /* 0x000720 */
|
||||
uint64_t cp_mux6_debug_ctl; /* 0x000728 */
|
||||
uint64_t cp_mux7_debug_ctl; /* 0x000730 */
|
||||
u64 cp_ct_debug_ctl; /* 0x000700 */
|
||||
u64 cp_br_debug_ctl; /* 0x000708 */
|
||||
u64 cp_mux3_debug_ctl; /* 0x000710 */
|
||||
u64 cp_mux4_debug_ctl; /* 0x000718 */
|
||||
u64 cp_mux5_debug_ctl; /* 0x000720 */
|
||||
u64 cp_mux6_debug_ctl; /* 0x000728 */
|
||||
u64 cp_mux7_debug_ctl; /* 0x000730 */
|
||||
|
||||
uint64_t _pad_000738[89]; /* 0x000{738,,,9F8} */
|
||||
u64 _pad_000738[89]; /* 0x000{738,,,9F8} */
|
||||
|
||||
/* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
|
||||
struct {
|
||||
uint64_t cp_buf_addr; /* 0x000{A00,,,AF0} */
|
||||
uint64_t cp_buf_attr; /* 0X000{A08,,,AF8} */
|
||||
u64 cp_buf_addr; /* 0x000{A00,,,AF0} */
|
||||
u64 cp_buf_attr; /* 0X000{A08,,,AF8} */
|
||||
} cp_pcix_read_buf_64[16];
|
||||
|
||||
struct {
|
||||
uint64_t cp_buf_addr; /* 0x000{B00,,,BE0} */
|
||||
uint64_t cp_buf_attr; /* 0x000{B08,,,BE8} */
|
||||
uint64_t cp_buf_valid; /* 0x000{B10,,,BF0} */
|
||||
uint64_t __pad1; /* 0x000{B18,,,BF8} */
|
||||
u64 cp_buf_addr; /* 0x000{B00,,,BE0} */
|
||||
u64 cp_buf_attr; /* 0x000{B08,,,BE8} */
|
||||
u64 cp_buf_valid; /* 0x000{B10,,,BF0} */
|
||||
u64 __pad1; /* 0x000{B18,,,BF8} */
|
||||
} cp_pcix_write_buf_64[8];
|
||||
|
||||
/* End of Local Registers -- Start of Address Map space */
|
||||
|
||||
char _pad_000c00[0x010000 - 0x000c00];
|
||||
char _pad_000c00[0x010000 - 0x000c00];
|
||||
|
||||
/* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
|
||||
uint64_t cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
|
||||
u64 cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
|
||||
|
||||
char _pad_012000[0x14000 - 0x012000];
|
||||
char _pad_012000[0x14000 - 0x012000];
|
||||
|
||||
/* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
|
||||
uint64_t cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
|
||||
u64 cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
|
||||
|
||||
char _pad_016000[0x18000 - 0x016000];
|
||||
char _pad_016000[0x18000 - 0x016000];
|
||||
|
||||
/* 0x18000-0x197F8 -- TIOCP Write Request Ram */
|
||||
uint64_t cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
|
||||
uint64_t cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
|
||||
uint64_t cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
|
||||
u64 cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
|
||||
u64 cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
|
||||
u64 cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
|
||||
|
||||
char _pad_019800[0x1C000 - 0x019800];
|
||||
char _pad_019800[0x1C000 - 0x019800];
|
||||
|
||||
/* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
|
||||
uint64_t cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
|
||||
uint64_t cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
|
||||
uint64_t cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
|
||||
u64 cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
|
||||
u64 cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
|
||||
u64 cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
|
||||
|
||||
char _pad_01F000[0x20000 - 0x01F000];
|
||||
char _pad_01F000[0x20000 - 0x01F000];
|
||||
|
||||
/* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
|
||||
char _pad_020000[0x021000 - 0x20000];
|
||||
char _pad_020000[0x021000 - 0x20000];
|
||||
|
||||
/* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
|
||||
union {
|
||||
uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
|
||||
uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
|
||||
uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
|
||||
uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
|
||||
u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
|
||||
u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
|
||||
u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
|
||||
u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
|
||||
union {
|
||||
uint8_t c[0x100 / 1];
|
||||
uint16_t s[0x100 / 2];
|
||||
uint32_t l[0x100 / 4];
|
||||
uint64_t d[0x100 / 8];
|
||||
u8 c[0x100 / 1];
|
||||
u16 s[0x100 / 2];
|
||||
u32 l[0x100 / 4];
|
||||
u64 d[0x100 / 8];
|
||||
} f[8];
|
||||
} cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */
|
||||
|
||||
/* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
|
||||
union {
|
||||
uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */
|
||||
uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */
|
||||
uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */
|
||||
uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */
|
||||
u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
|
||||
u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
|
||||
u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
|
||||
u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
|
||||
union {
|
||||
uint8_t c[0x100 / 1];
|
||||
uint16_t s[0x100 / 2];
|
||||
uint32_t l[0x100 / 4];
|
||||
uint64_t d[0x100 / 8];
|
||||
u8 c[0x100 / 1];
|
||||
u16 s[0x100 / 2];
|
||||
u32 l[0x100 / 4];
|
||||
u64 d[0x100 / 8];
|
||||
} f[8];
|
||||
} cp_type1_cfg; /* 0x028000-0x029000 */
|
||||
|
||||
|
|
@ -211,30 +211,30 @@ struct tiocp{
|
|||
|
||||
/* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
|
||||
union {
|
||||
uint8_t c[8 / 1];
|
||||
uint16_t s[8 / 2];
|
||||
uint32_t l[8 / 4];
|
||||
uint64_t d[8 / 8];
|
||||
u8 c[8 / 1];
|
||||
u16 s[8 / 2];
|
||||
u32 l[8 / 4];
|
||||
u64 d[8 / 8];
|
||||
} cp_pci_iack; /* 0x030000-0x030007 */
|
||||
|
||||
char _pad_030007[0x040000-0x030008];
|
||||
|
||||
/* 0x040000-0x040007 -- PCIX Special Cycle */
|
||||
union {
|
||||
uint8_t c[8 / 1];
|
||||
uint16_t s[8 / 2];
|
||||
uint32_t l[8 / 4];
|
||||
uint64_t d[8 / 8];
|
||||
u8 c[8 / 1];
|
||||
u16 s[8 / 2];
|
||||
u32 l[8 / 4];
|
||||
u64 d[8 / 8];
|
||||
} cp_pcix_cycle; /* 0x040000-0x040007 */
|
||||
|
||||
char _pad_040007[0x200000-0x040008];
|
||||
|
||||
/* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
|
||||
union {
|
||||
uint8_t c[0x100000 / 1];
|
||||
uint16_t s[0x100000 / 2];
|
||||
uint32_t l[0x100000 / 4];
|
||||
uint64_t d[0x100000 / 8];
|
||||
u8 c[0x100000 / 1];
|
||||
u16 s[0x100000 / 2];
|
||||
u32 l[0x100000 / 4];
|
||||
u64 d[0x100000 / 8];
|
||||
} cp_devio_raw[6]; /* 0x200000-0x7FFFFF */
|
||||
|
||||
#define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)]
|
||||
|
|
@ -243,10 +243,10 @@ struct tiocp{
|
|||
|
||||
/* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */
|
||||
union {
|
||||
uint8_t c[0x100000 / 1];
|
||||
uint16_t s[0x100000 / 2];
|
||||
uint32_t l[0x100000 / 4];
|
||||
uint64_t d[0x100000 / 8];
|
||||
u8 c[0x100000 / 1];
|
||||
u16 s[0x100000 / 2];
|
||||
u32 l[0x100000 / 4];
|
||||
u64 d[0x100000 / 8];
|
||||
} cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */
|
||||
|
||||
#define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
|
||||
|
|
|
|||
|
|
@ -40,10 +40,10 @@ struct cx_drv {
|
|||
};
|
||||
|
||||
/* create DMA address by stripping AS bits */
|
||||
#define TIOCX_DMA_ADDR(a) (uint64_t)((uint64_t)(a) & 0xffffcfffffffffUL)
|
||||
#define TIOCX_DMA_ADDR(a) (u64)((u64)(a) & 0xffffcfffffffffUL)
|
||||
|
||||
#define TIOCX_TO_TIOCX_DMA_ADDR(a) (uint64_t)(((uint64_t)(a) & 0xfffffffff) | \
|
||||
((((uint64_t)(a)) & 0xffffc000000000UL) <<2))
|
||||
#define TIOCX_TO_TIOCX_DMA_ADDR(a) (u64)(((u64)(a) & 0xfffffffff) | \
|
||||
((((u64)(a)) & 0xffffc000000000UL) <<2))
|
||||
|
||||
#define TIO_CE_ASIC_PARTNUM 0xce00
|
||||
#define TIOCX_CORELET 3
|
||||
|
|
@ -63,10 +63,10 @@ extern int cx_device_unregister(struct cx_dev *);
|
|||
extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
|
||||
extern int cx_driver_unregister(struct cx_drv *);
|
||||
extern int cx_driver_register(struct cx_drv *);
|
||||
extern uint64_t tiocx_dma_addr(uint64_t addr);
|
||||
extern uint64_t tiocx_swin_base(int nasid);
|
||||
extern void tiocx_mmr_store(int nasid, uint64_t offset, uint64_t value);
|
||||
extern uint64_t tiocx_mmr_load(int nasid, uint64_t offset);
|
||||
extern u64 tiocx_dma_addr(u64 addr);
|
||||
extern u64 tiocx_swin_base(int nasid);
|
||||
extern void tiocx_mmr_store(int nasid, u64 offset, u64 value);
|
||||
extern u64 tiocx_mmr_load(int nasid, u64 offset);
|
||||
|
||||
#endif // __KERNEL__
|
||||
#endif // _ASM_IA64_SN_TIO_TIOCX__
|
||||
|
|
|
|||
Loading…
Reference in a new issue